JPS6259403A - Fm demodulator - Google Patents

Abstract

PURPOSE:To obtain a high demodulation sensitivity by forming a pulse signal from n-set of frequency division signals obtained from frequency division of an input signal and synthesizing and smoothing the pulse signals. CONSTITUTION:A limiter amplifier 2 shapes an FM signal inputted to an FM signal input terminal 1 and outputs the result to a 1/2 frequency divider 6. The circuit 6 outputs a signal applying 1/2 frequency division to the input signal at an output terminal 01 and a 1/2 frequency division signal having a phase difference by 180 deg. from that of said signal is outputted at an output terminal 02. Monostable multivibrators 3-1, 3-2 output a pulse signal synchronously with the leading of the 1/2 frequency division signals at the output terminals 01, 02. A synthesis circuit 7 outputs logic 1 when both the two pulse signals is logic 1 or logical 0 and outputs logic 0 when one of them is logic 1. In smoothing the output waveform of the circuit 7 by an LPF, a DC is obtained and it is proportional to the change in the duty ratio of the input waveform, that is, the input signal frequency, then the circuit acts like an FM demodulator, Thus, a high demodulation sensitivity is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is applied to a demodulator for FM signals. In particular, the F
Regarding M demodulator.

〔overview〕

In an FM demodulator that outputs a voltage corresponding to the number of pulses of an input FM signal, the present invention divides the input FM signal, generates a signal with a constant pulse width using each divided signal, and calculates the logical value of this signal. By outputting a composite signal depending on the evenness and oddness of , and further smoothing this signal, an F.
This realizes an M demodulator.

[Conventional technology]

As conventional FM demodulators, Foster-Seeley detectors, ratio detectors, quadrature detectors, etc. are widely used. These demodulators are simple in construction and provide relatively good characteristics. However, since it requires a high frequency coil or a ceramic resonator, it has been difficult to integrate it into a one-chip integrated circuit.

In addition to the above-mentioned FM demodulator, a pulse counting detector is also used. Since the pulse counting detector is constituted by a digital circuit, it is easy to integrate and has the advantage that a good distortion rate can be obtained even without adjustment.

A block diagram of a demodulator is shown.

be done. The output of the limiter amplifier 2 is connected to a monostable multivibrator 3. The output of the monostable multivibrator 3 is connected to a low pass filter 4 which is connected to a low pass filter 5 .

The FM signal input to the FM signal input terminal 1 is shaped into a rectangular wave by the limiter amplifier 2. Generates a monostable signal τ. A time chart showing the relationship between the output of the limiter amplifier 2 and the monostable multivibrator 3 is shown in FIG. The low-pass filter 4 smoothes the pulse train output from the monostable multivibrator 3. As a result, a DC voltage proportional to the human power signal frequency is outputted to the output terminal 5, and the FM signal can be demodulated.

[Problems to be solved by the invention] However, since the demodulation sensitivity of pulse counting detectors is low, sufficient detection output cannot be obtained when demodulating FM signals with small frequency deviations, and noise may be mixed in. It had the disadvantage that the signal-to-noise ratio easily deteriorated. This point will be explained below.

The DC output voltage e obtained at the output terminal 5 is determined by the input signal frequency f and the pulse voltage vH output from the monostable multivibrator 3, as follows: e=”Ko−f −・−・−(
1) Ke = r r'V, 4------'-(
2). Here, Ktl is the demodulation sensitivity and indicates a 1-minute change in the output signal voltage when the input signal changes by IO2.

The input signal is F with center frequency fc and frequency deviation f4.
Considering an M signal, the input signal frequency fc (fc f
a), output voltage e(s e-,
e* is, respectively, e,=, −fc e−=Ko (fc fa ) −−
-----(3) e, = Kn (fe + fa). Therefore, the peak value of the demodulated voltage is (e+
e-) = 6 ・2 fa −・−=−(
4). Here, if the pulse width τ1 is determined so that the output voltage ec becomes VM/2, then from equations (2) and (3), r, = ・−・・−
(5) fc. At this time, equation (4) can be expressed as follows.

For example, in an analog FM demodulator for mobile communications, the center frequency fc is 455kHz and the frequency deviation f4 is 3.5kHz.
Therefore, (f a / f c ) #0.0077. Further, when a CMO8 logic integrated circuit is used as a monostable multivibrator, the pulse voltage V becomes equal to the power supply voltage V0°, which is about 5. Substituting these values into equation (6) yields (e, -e-) #38.5 (Vp-p). Converting this value to an effective value is 13.6mV
r, ■, and s, which are small values.

As described above, the pulse counting detector has a low demodulation sensitivity and can only obtain a small output voltage, so it has the disadvantage that external noise is easily mixed in and the signal-to-noise ratio is easily deteriorated.

In order to solve this drawback, it is necessary to increase the demodulation sensitivity KO, and it is effective to increase the time width τ1 or the pulse voltage vH.The pulse voltage v,4 is limited by the power supply voltage. Therefore, it is practical to increase the pulse width τ1.

However, due to the relationship in equation (5), in order to increase the pulse width τ1, it is necessary to lower the center frequency f of the input signal. Therefore, a method of lowering the center frequency fe by adding a down converter before the pulse counting detector has been conventionally practiced. However, since the down converter includes a mixer and a high frequency filter, its circuit configuration is complicated. In particular, high-frequency filters are difficult to monolithically integrate, and external components must be installed as components.
The advantage of easy integration of the pulse counting detector is halved.

Also, if the center frequency fc is lowered, the pulse repetition frequency of the output of the monostable multivibrator will also be lowered, so
Unless the high-frequency cut-off characteristic of the low-pass filter for smoothing this is made steep, the pulse repetition frequency component will leak to the output and the signal-to-noise ratio will deteriorate. Therefore, it is necessary to increase the order of the low-pass filter, which also has the disadvantage of complicating the circuit.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and provide an FM demodulator that can be easily integrated into a monolithic integrated circuit.

[Means for solving problems]

The FM demodulator of the present invention includes a frequency dividing circuit that divides an input signal and outputs n frequency-divided signals whose phases differ from each other by 360'/n (n is plural), and the n frequency-divided signals. n monostable multivibrators each generating a pulse signal of equal time width as a trigger input, and these n
a synthesis circuit that outputs a binary signal by determining whether the number of logic value outputs of one of the outputs of the monostable multivibrators is even or odd, and a low-pass filter that smoothes the output of this synthesis circuit. It is characterized by having the following.

[Effect]

The FM demodulator of the present invention can increase the pulse width r7 of the output of the monostable multivibrator by n times or more compared to the conventional pulse width τ1, and thereby the demodulation sensitivity can also be increased by n times or more. can. In the present invention, the demodulation sensitivity can be greatly increased without a down converter, and there is no need to increase the order of the smoothing low-pass filter.

〔Example〕

FIG. 1 is a block diagram of an FM demodulator according to a first embodiment of the present invention. This embodiment shows a case where the frequency division number n is 2.

FM signal input terminal 1 is connected to limiter amplifier 2.

The output of the limiter amplifier 2 is connected to a divide-by-two circuit 6.

The first output terminal 01 of the frequency divider circuit 6 is connected to the first monostable multivibrator 3-1, and the second output terminal 02
is connected to the second monostable multivibrator 3-2. The output of the monostable multivibrator 3-1.3-2 is connected to the input terminal 11.12 of the combining circuit 7. The output of the synthesis circuit 7 is connected to the low pass filter 4. The output of the low-pass filter 4 is connected to a demodulation output terminal 5.

The limiter amplifier 2 shapes the FM signal input to the FM signal input terminal 1 into a rectangular wave, and outputs the rectangular wave to the frequency divider circuit 6 .

The frequency divider circuit 6 outputs a signal obtained by dividing the frequency of the input signal by two to a first output terminal 01, and outputs a frequency-divided signal having a phase difference of 180 degrees from this signal to a second output terminal 02. The monostable multivibrators 3-1 and 3-2 output pulse signals with a time width τ2 in synchronization with the rise of the frequency-divided signals of output terminals o1 and o2, respectively.

FIG. 2 is a time chart of the apparatus of this embodiment.

Waveform (a) is the output of limiter amplifier 2, waveform (b) is the frequency-divided signal at output terminal 01 of frequency-divider circuit 6, waveform (C) is the frequency-divided signal at output terminal 02, and waveform (d) is monostable. The output of the multivibrator 3-1, waveform (e) shows the output of the monostable multivibrator 3-2, the waveform ff) shows the output of the synthesis circuit 7, and the waveform (g) shows the output waveform of the output terminal 5.

In this example, monostable multivibrator 3-1.3-
The pulse width τ2 of the output pulse signal of 2 is τ2#3T with respect to the pulse width T (T = 1/2f) of waveform (a).
There is a relationship between Therefore, the waveform (dl) output by the monostable multivibrator 3-1 using the frequency-divided signal of waveform (b) as a trigger signal becomes the logic rOJ when the pulse width τ2 is approximately 3T. This becomes a repetitive pulse train with a time length of approximately T.

9. The waveform +8) outputted by the monostable multivibrator 3-2 using the tricycle signal of the waveform (C) whose phase differs by 18 degrees from the waveform (b) as a trigger signal is the waveform (d).
The waveform is shifted by 2T.

The synthesis circuit 7 observes these two waveforms (dl, (e), and outputs logic "1" when both are logic rOJ or logic "1", and outputs logic "1" when one is logic "1". outputs logic "0". As a result, waveform 1f) is obtained at the output of the synthesis circuit 7.

Here, consider a case where the input signal frequency changes due to frequency modulation. In this case, the time period of logic "0" in the output waveform (d), +8) of the monostable multivibrator 3-1.3-2 changes, and the duty ratio of the waveform (d), te> changes. . As a result, the output waveform of the synthesis circuit 9 (
The duty ratio of f) also changes. Therefore, when the waveform (f) is smoothed by a low-pass filter 4, a DC voltage shown in the waveform (g) is obtained, and this DC voltage is a change in the duty ratio of the waveform (f), that is, a change in the input signal frequency f. , so it operates as an FM demodulator. However, FIG. 2 shows the case without modulation.

Next, the demodulation sensitivity of this FM demodulator will be explained. For the input signal frequency r, the pulse width T of the waveform (al) is 'l' = --------<71 f.Next, the pulse width T of the waveform (al) is as follows: is the waveform (since the repetition period of dl is 4T, 〒=4T−
τ, −−−−−−−(8),
This value is the same for the waveform (el), but
11° is the waveform output from the synthesis circuit 7 (DC averaged over fl)
A voltage, that is, waveform (g) is waveform (f)
By averaging over time 4T: 14T-27
1 e= □V, 1
−・−・−(9) Represented by T. However, ■8 is the pulse voltage output by monostable multivibrator 3-1.3-2.
do. Substituting equations (7) and (8) into this equation, we get
e= (-1-1-I2-f) ・VM
==----Q[I t〒. Therefore, the demodulation sensitivity KDt is as follows, which can be expressed in the same form as the conventional equation (2), where the output voltage ec with respect to the center frequency fc is set at the center of the range of change of the output voltage e. That is, e c -VM/2. Substituting this center frequency fc and output voltage ec into formula 09, the pulse width τ2 becomes τ2 ” −−−・−・
(2) fc. Comparing this equation with equation (5), the pulse width τ:
is three times the pulse width τ1. Therefore, the demodulation sensitivity KD2 is also K, t=3・K, --------
It becomes cloudy. That is, this embodiment can obtain demodulation sensitivity three times that of the conventional example.

Moreover, in this embodiment, since the frequency of the signal waveform (f) applied to the low-pass filter 4 is equal to the input signal frequency f, there is no need to increase the order of the low-pass filter 4. This is a major advantage over conventional FM demodulators that add a down converter to a pulse counting detector.

FIG. 3 is a block diagram of an FM demodulator according to a second embodiment of the present invention. This embodiment shows a case where the frequency division number n is 3.

In this embodiment, a divide-by-three circuit 8 is used instead of the divide-by-two circuit 6. The FM signal input terminal I is connected to a frequency divider circuit 8 via a limiter amplifier 2. Three output terminals 01.02 and 03 of the frequency divider circuit 8 are connected to monostable multivibrators 3-1.3-2 and 3-3, respectively. Monostable multivibrator 3-1.3-2.3-
3 are input terminals 11 and I2 of the synthesis circuit 9, respectively.
, I3.

The output of the synthesis circuit 9 is connected to the demodulation output terminal 5 via the low-pass filter 4.

The divide-by-three circuit 8 divides the frequency of the human input signal by three, outputs a divided-by-three signal having a phase difference of 120 degrees from the output signal of the output terminal 01 to the output terminal 02, and outputs the output signal of the output terminal 01 to the output terminal 03. Outputs a frequency-divided signal with a 240° phase difference from the signal. Monostable multivibrator 3-1'% 3-2.3-3
generate a pulse signal with a pulse width τ3 in synchronization with the rise of output terminals 01.02 and 03, respectively.

Figure 4 shows a time chart of each part.

Waveform (al is the output of limiter amplifier 2, waveform tb> is the frequency-divided signal of the output terminal 01 of the frequency-divider circuit 8, waveform (C1 is the frequency-divided signal of the output terminal 02), waveform (d) is the output Terminal 03 frequency-divided signal, waveform (el is the output of monostable multivibrator 3-1, waveform (fl is the output of monostable multivibrator 3-2, waveform (g) is the output of monostable multivibrator 3-3) , waveform fhl is the output waveform of the synthesis circuit 9 (+1 indicates the output waveform of the output terminal 5.

In this example, monostable multivibrator 3-1.3-
2. Explain the case where the pulse width τ3 of the output of 3-3 has the relationship #5T with the pulse width T of the waveform (aJ. In this case, the frequency divided by three signal of the waveform (b) The waveform output by the monostable multivibrator 3-1 using the trigger signal (el is the time when the logic rlJ is reached, that is, the pulse width is about 5T, and the time below which the logic is "0" is about T) is a repeating pulse train. becomes.

Also, 120° and 240° with respect to waveform (b), respectively.
Monostable multivibrator 3-2.3- using the trigon frequency-divided signals of waveforms fc) and (d) whose phases differ by
The waveforms tr>, fg) outputted by No. 3 are waveforms obtained by shifting the waveform [e) by times 2T and 4T, respectively.

The synthesis circuit 11 observes these three waveforms (e), (f), and (g), and outputs a logic "0" when the logic "1" is zero or an even number of times, and outputs a logic "0" when the logic "1" is When the number is odd, a logic "1" is output. As a result, a signal shown in waveform (h) is obtained at the output of the combining circuit 11.

Here, consider a case where the input signal frequency changes due to frequency modulation. In this case, the timing of logic "0" in the output waveforms (d), fe) of the monostable multivibrators 3-1.3 to 2.3-3 changes, and the waveforms (el, ff)
The duty ratio of and (gl changes. As a result, the duty ratio of the output waveform (h) of the combining circuit 9 also changes.

Therefore, when the waveform (h) is smoothed by the low-pass filter 4, the DC voltage shown in the waveform (1) is obtained, and since this DC voltage depends on the change in the input signal frequency f, it operates as an FM demodulator. .

The demodulation sensitivity of this example can be determined in the same manner as the first example.

In the case of this example, the waveforms (ill), (fl and (
The time of the phantom logic rOJ is 〒=6T−τ3′−−−−−
・-C4). Also, the DC voltage e (waveform (i)) that is the average of waveform (f) is = (-2+τx ・f ) ・VM −−−
--C51. Therefore, the demodulation sensitivity is: K o3=τ3 ′ V M ---(151), which is expressed in the same format as (2) 2 and 00 equations.

Here, the output voltage ec with respect to the center frequency fc is set at the center of the variation range of the output voltage e. That is, e c =VM/2. According to the formula a, the pulse width τ3 is as follows. Comparing this 2 with equation (5), the pulse width τ3 becomes the pulse width τ1
It is five times that of the previous year. Therefore, even if the demodulation sensitivity is 0, Kl+3=5・K, ・−・−0
becomes ω. In other words, this embodiment provides demodulation sensitivity five times that of the conventional example.

In this embodiment, an output signal similar to waveform (h) is obtained from the synthesis circuit 11 even when τ3#3T is used, and it can be used as an FM demodulator. However, in this case, the demodulation sensitivity KDff is the demodulation sensitivity KQ of the first embodiment! is equal to
It remains five times that of the conventional example.

In the above embodiments, cases where the frequency division number n is 2 and 3 have been described, but the present invention can be implemented in the same way even when n≧4.

FIG. 5 shows a block diagram of an FM demodulator according to a third embodiment of the present invention. This example shows the case of n frequency division, which is a generalization of the present invention.

FM signal input terminal 1 is connected to n frequency divider circuit 13 via limiter amplifier 2 . Output terminal o of n frequency divider circuit 13
1 to On are each monostable multivibrator 3-1
~3-n. Monostable multivibrator 3-
Outputs 1 to 3-n are connected to input terminals 1 to In of the synthesis circuit 11, respectively. The output of the synthesis circuit 11 is connected to a low pass filter 4. The output of the low-pass filter 4 is connected to a demodulation output terminal 5.

In this embodiment, the monostable multivibrator 3-
The pulse width τ7 of 1 to 3-n is expressed as r, #(2n -1) ・T -... with respect to the pulse width T of the input signal.
...-Q! By selecting ll, the maximum demodulation sensitivity KDn can be obtained. At this time, demodulation sensitivity KDfi is K
Dn=τ, ・v,= (2n-1)KD −(2
1 m, which can be increased by (2n-1) times compared to the conventional example. Table 1 shows the relationship between the frequency division number n, the pulse width τ·7, and the demodulation sensitivity ratio KDfi/KD.

(Hereinafter, the margin of this page) Table 1, FIG. 6 shows a circuit configuration diagram of the monostable multivibrator used in the above embodiment. This is a conventional circuit that utilizes a time constant based on resistance and capacitance.

The trigger signal input terminal 16 is connected via the trigger circuit 17 to
It is connected to the first input terminal of the NAND circuit 18. NA
An output terminal of the ND circuit 18 is connected to an input terminal of an inverter 21 via a capacitor 19. A connection point between the capacitor 1119 and the input terminal of the inverter 21 is grounded via the resistor 20. The output terminal of the inverter 21 is connected to the second input terminal of the NAND circuit 1 and the input terminal of the inverter 22. An output terminal of the inverter 22 is connected to a pulse output terminal 23. When using the herbal stable multivibrator in the third embodiment, it is necessary to align the n pulse widths to τ7. Since the pulse width is determined by the time constant of the capacitance and resistance, the resistor 20 is made a variable resistor.

However, in this circuit configuration, when the frequency division number n becomes large,
There is a disadvantage that the number of variable resistors increases and the number of adjustment points increases.

FIG. 7 is a circuit diagram of a monostable multivibrator that can solve the above problem.

In this example, an accurate pulse width can be obtained without adjustment by using a timer configuration using a digital circuit.

The trigger signal input terminal 24 is connected via a trigger circuit 26 to
It is connected to the set terminal of the RS flip-flop 27.

An output terminal Q of the RS flip-flop 27 is connected to a first input terminal of an AND circuit 28 and a pulse output terminal 32. A second input terminal of AND circuit 28 is connected to clock input terminal 25 . The output terminal of the AND circuit 28 is connected to the clock terminal of the counting circuit 29. Counting circuit 2
The output of 9 is connected to the input terminal A of the one-loss detection circuit 301. - The input terminal B of the number output circuit 30 is connected to the pulse width setting terminal 31. - The output of the number output circuit 30 is connected to the glue set terminal of the RS flip-flop 27 and the counting circuit 29.
Connected to the recess/node terminal of the

A pulse signal is input to the trigger signal input terminal 24.
[Then, at the rise of this signal, the trigger circuit 26 generates a positive pulse with a time width of about 100 n5ec = 1 jlsec. −
:1, and outputs the state "1" to its output terminal Q. At this time, the output of the AND circuit 28 receives the clock signal applied to the clock input terminal 25.
Since the clock signal is transmitted as is, the counting circuit 29 starts counting the clock signal. The count value of the counting circuit 29 is input to the input terminal A of the coincidence detection circuit 30, and the number M of clock pulses corresponding to the pulse width τ7 of the monostable multipibre and kneader is input to the input terminal B of the -number output circuit 30. has been done. - The number output circuit 30 outputs rOJ when the two inputs are different, and outputs "1" when they are equal. Therefore, when the count value of the counting circuit 29 becomes equal to the set value M, "1" is output from the - number calculation circuit 30,
This output resets the RS flip-flop 27 and the counting circuit 29. As a result, the output of the output terminal Q of the RS flip-flop 27 returns to "0", and the count value manually input to the -number output circuit 30 also returns to zero. Further, since the clock signal is no longer transmitted to the output of the AND circuit 28, the counting operation of the counting circuit 29 is stopped.

With the above operation, "1" is output to the pulse output terminal 32 for a certain period of time from the rise time of the human input signal until the counting circuit 29 finishes counting M pieces.

Here, if the clock frequency is r, and the number of clock pulses M is selected so that M=f, ・I7 −・−■, it is possible to obtain a pulse signal with a time width τ1 that is synchronized with the rising edge of the input signal. .

By using a digital circuit, this monostable multivibrator can obtain a pulse signal with a very specific time width without adjustment. The precision of the pulse width is determined by the stability of the clock signal, and when a crystal oscillator is used as the clock signal, a stability of about ±lXl0-' can be easily obtained.

Next, the synthesis circuit will be explained. Examples of synthesis circuits are shown in FIGS. 8 to 10.

FIG. 8 shows a synthesis circuit used in the first embodiment in which the frequency division number n is 2. If the frequency division number n is 2, the two input terminals 1
It outputs "1" only when "1" is input to both I2 and I2. Therefore, a synthesis circuit can be realized using a three-input AND circuit.

FIG. 9 shows a synthesis circuit where the frequency division number n is 3 and is suitable for r3#5T. In this case, input terminal 11, I2.1
When "1" is input to all 3, rlJ is output. Therefore, the configuration circuit can be realized using a three-input AND circuit.

FIG. 10 shows a synthesis circuit suitable for the case where the frequency division number n is 3 and I3''3T. In this case, it is necessary to determine whether the number of "1"s is - or two.

Therefore, for example, a combination circuit is constructed by combining exclusive OR circuits. Input terminals 11, I2, and
Table 2 shows the relationship between the value input to I3 and the output of the synthesis circuit.

The synthesis circuit shown in Figure 10 of Table 2 performs a parity check to determine whether the number of "1"s is zero, an even number, or an odd number, and can be used for either τ, #3T, or 5T. .

Generally, when the pulse width .tau.7 is selected to be approximately (2n-1)T, a synthesis circuit in the case of frequency division by n outputs "1" only when the input terminals 1-In are all "1". Therefore, a synthesis circuit can be realized using an n-input AND circuit. Also,"
A parity check circuit combined with an exclusive OR circuit can be used as a synthesis circuit for determining whether the number of "1" is zero, an even number, or an odd number.

In the above embodiments, the monostable multivibrator operates in synchronization with the rising edge of the frequency-divided signal, but the present invention can be similarly implemented even if the monostable multivibrator operates in synchronization with the falling edge of the frequency-divided signal.

Regardless of whether the rising edge or the falling edge is used, the monostable multivibrator uses only information from either the rising edge or the falling edge of the frequency-divided signal. When the rising edge is used as a trigger signal, the phases of the n frequency-divided signals at the rising time are 360'/n
It is sufficient that they are different, and the phase relationship at the falling time has no effect. The same applies to the duty ratio. Conversely, when using the falling edge as a trigger signal, it is sufficient that the phases of the n frequency-divided signals at the falling time differ from each other by 360'/n, and the phase relationship at the rising time has no effect. do not. The same applies to the duty ratio.

Therefore, as an n frequency divider circuit, the phases are 36
The present invention can be similarly implemented in any circuit as long as it can obtain n frequency-divided signals that differ by 06/n.

〔Effect of the invention〕

As explained above, the FM demodulator of the present invention is easy to integrate and has high demodulation sensitivity, so it is resistant to external noise. Moreover, since the circuit configuration is digital, N
Good characteristics can be obtained through adjustment, and operation is extremely stable. Therefore, the present invention provides various FM communication devices,
When used in radios, etc., it has the great effect of making equipment smaller and cheaper.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an FM demodulator according to a first embodiment of the present invention. FIG. 2 is a timing chart of the first embodiment. FIG. 3 is a block diagram of an FM demodulator according to a second embodiment of the present invention. FIG. 4 is a timing chart of the second embodiment. FIG. 5 is a block diagram of an FM demodulator according to a third embodiment of the present invention. Figure 6 is a circuit diagram of a monostable multivibrator. 1′″@5zqtv+′<< y v −y oWJB
tmtc 1 diagram. FIG. 8 is a diagram showing an example of a synthesis circuit.
1. FIG. 9 is a diagram showing an example of a synthesis circuit.
1 FIG. 10 is a diagram showing an example of a synthesis circuit. FIG. 11 is a block diagram of a conventional FM demodulator. FIG. 12 is a timing chart of a conventional example. ■...FM signal input terminal, 2...Limiter amplifier,
3.3-1 to 3-n...monostable multivibrator,
4...Low pass filter, 5...Demodulation output terminal, 6
...Divide-by-two circuit, 7...Composition circuit, 8...Divide-by-three circuit, 9...Composition circuit, 10...N frequency division circuit, 11
... Synthesis circuit, 16 ... Trigger signal input terminal, 17
...Trigger circuit, 18...NAND circuit, 19...
・Capacity, 21. 22... Inverter, 23... Pulse output terminal, 24... Trigger signal input terminal, 25...
・Clock input terminal, 26...Trigger circuit, 27...
・RS flip-flop, 28... AND circuit, 29
...Counting circuit, 30...-Number calculation circuit, 31...
Pulse width setting terminal, 32...Pulse output terminal. Patent Applicant Nippon Telegraph and Telephone Corporation Agent Patent Attorney Nao Ide Takashi 1st Embodiment LI φ--4T--Dispute,': χ 2 times, 2nd Embodiment 3rd Embodiment Ivy 5 Figure Monostable Multivibrator child 6 Diagram Monostable multivibrator synthetic circuit Synthetic circuit Synthetic circuit Tsuta 1o diagram

Claims (1)

[Claims] (1) A frequency dividing circuit that divides an input signal and outputs n (n is plural) frequency divided signals whose phases differ from each other by 360°/n, and each of these n frequency divided signals is used as a trigger input. n monostable multivibrators that generate pulse signals of equal time width, and a binary signal by determining whether the number of logical value outputs of one of the outputs of these n monostable multivibrators is even or odd. An FM demodulator comprising: a synthesis circuit for outputting an output; and a low-pass filter for smoothing the output of the synthesis circuit.