JPS6257327A - Line setting circuit - Google Patents

Abstract

PURPOSE:To save the entire hardware and to use a conventional CMOS memory by giving read control information of a data memory circuit detected with a fault to a spare data memory circuit based on the failure information of a data memory circuit for setting line. CONSTITUTION:The spare data memory circuit 25 is constituted by the same circuit as the data memory circuit 24 and input signals IN1-IN4 are led similarly as the data memory circuit 24. The spare data memory circuit 25 applies similar operations as other data memory circuits 24-1-24-4 but differs in giving read control information 29-5 for the read. Information 32 such as data memory part failure information or forced changeover instruction information sent from the data memory circuits 24-1-24-4 is received and proper changeover information 33 is sent by the control circuit 34 to select read control information 29-5 by a selection circuit (SEL) 35. The selected read control information 29-5 is given to the spare data memory circuit 25.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a line setting circuit for a synchronous multiplex converter in a digital transmission network.

(Conventional technology) Conventionally, the technology in this field is as described in Teranishi et al., "Transmission Facility Design for Digital Networks" (Telecommunications Association of Japan, p.
iai ~ 188,) and Nakaon et al.'s ``Digital synchronous terminal station system for long distances'' (edited by Nippon Telegraph and Telephone Public Corporation t1M station establishment).
Some of them are described in Facility J Vol. 33 No. 11, P95-106). The explanation will be given below according to these.

In digital transmission networks, instead of the spatial line setting using distribution racks, which was conventionally carried out in analog transmission networks, it is now possible to set up lines temporally by exchanging time slots on the digital multiplex level. A synchronous multiplex conversion device as disclosed in the above-mentioned document is in practical use.

The synchronous multiplex converter terminates a 1.544 Mb/s or 312 Mb/s digital transmission line, performs line setting in units of 6 channels (line setting unit), and terminates the line in the same unit. 8.192Mb/s
, or connected to a digital exchange by a 2.048 Mb/s intraoffice interface. The line setting function of the synchronous multiplex converter is a line setting circuit (TS
I: Time 5lOt InterChan(
A semi-fixed time switch is realized by configuring the time slot switching order to be externally controllable.

The digital transmission path accommodated by the synchronous multiplex converter is 1.
544M b/s primary group transmission line, and 6.31
It is a 2 Mb/s secondary group transmission line, and the channel capacity of each transmission line interface is 24 channels and 96 channels, respectively, in terms of a 64 Kb/S telephone channel. on the other hand,
The interface with the exchange is a 2.048 Mb/s or 8°192 Mb/s intra-office interface, and the channel capacity of each intra-office interface is 30 channels and 120 channels, respectively.

Due to these transmission path and intra-office interface conditions, the synchronous multiplex converter is capable of converting the signal speed and channel capacity of each interface in addition to the aforementioned transmission line termination function, line setting function, line termination function, and intra-office interface function. Multiple conversion functions are required.

Next, the configuration of a circuit that implements line setting and multiplex conversion in the synchronous multiplex converter will be described. Hereinafter, in order to avoid complicating the explanation, the transmission path interface will be described in 6.
Although the 312Mb/82nd order group interface and the intra-office interface are limited to the 8.192Mb/s intra-office interface, the present invention can be similarly applied to cases where other transmission path interfaces and intra-office interfaces are accommodated. It goes without saying that it is possible.

FIG. 2 is a block diagram showing an example of the configuration of the line setting and multiplex conversion function section of the synchronous multiplex converter.
This figure shows a circuit that performs line settings in the intra-office direction (R direction). In FIG. 2, INz+-1 to 40) are 6.
This is an input signal (line) consisting of a 96-channel multiplexed signal received from a 312 M b /s secondary group transmission line interface and speed-converted to 8.192 M b /S. Further, 0LITi (i=1 to 32) is stagnated as an output signal consisting of a 120-channel multiplexed signal with a signal rate of 8.192 Mb/S, and is sent to the in-office interface. The line setting function section shown in FIG. 2 has 96 channels x 4G of input signals IN1 (i-1 to 40), a total of 3840 channels (=640 handling groups:
1-IG), this signal is first multiplexed into 120 channels x 32 signals, and then these signals are set up by time slot swapping to output 120 channel V channel multiplexed signals x 32 signals. Signal (line) OUTi (
i=1 to 32).

A detailed explanation will be given below with reference to FIG.

, In Fig. 2, 1 to 8 are multiplex conversion circuits (hereinafter referred to as 5) that convert five 96-channel multiplexed signals (lines) sent from the transmission line side into four 120-channel multiplexed signals (lines). /4 conversion circuit). These 5/4 conversion circuits 1 to 8 convert input signals lN consisting of 40 96-channel multiplexed signals sent from the transmission line side.
1 (i-1 to 40) are multiplex-converted into signals consisting of 32 120-channel multiplexed signals. 9 is the line setting circuit (
TSI), and HG (6
times I by replacing time slots for each channel)
I setting and output signal 0LITi (i=1~32
) of 120. Sends channel multiplexed signals.

In the above explanation, we have described the multiplex conversion and line settings in the direction from the transmission line to the intra-office direction (R direction), but in the direction from the intra-office to the transmission line (S direction), the configuration is completely symmetrical to the R direction, that is, 415 conversion This is realized by a circuit and a circuit setting circuit.

Since the line setting circuit 9 has a function of rearranging the temporal order of input data and outputting the same, it requires some kind of memory function. Its basic configuration is shown in FIG. In FIG. 3, 10 is a data memory, and 11 is a data memory 10.
12 is an address counter, 13 is a west address, 14 is an address control memory, 15 is a read address, and 16 is an output of the data memory 10. The data IN that has arrived at the input 11 of the data memory 10 is sequentially transferred to the data memory 10 according to the write address 13 that is the output of the address counter 12.
written to. The write address 13 is also given to the address control memory 14 at the same time, and the address control memory 14 gives the data memory 10 a read address 15 written in advance in correspondence with the given address 13. The data memory 10 reads data to the output 16 according to the read address 15, and sets the data as OUT. That is, the phase conversion information between the input and output of the data memory 10 is stored in the address control memory 14, and the order of reading data from the data memory 10 is random according to this phase conversion information.

FIG. 4 shows a conventional line setting circuit, which has a 3840 channel. Input signals (lines) IN1 to IN4 each have an old note of 960 channels (8 Mb/s serial signal after 5/4 conversion
This is an 8 Mb/s octet parallel signal obtained by converting a book into serial/parallel data, and the multiplexer (MLIX) 18F multiplex a, 3
2Mb/Stri? becomes a parallel signal. This signal is sequentially written into the data memory section (DM) 19, changed channel arrangement and read out by the address control memory (ACM) 20, and is read out by the address control memory (ACM) 20.
X>21F4+7) 8Mb/st quartet Parallel signal output signals (lines) are separated into OUT1 to OUT4. Therefore, the function of the data memory section (DM) 19 that stores all the input information of 3840 channels is very important, and normally N
(normal) type memory section 19-1, E (81
erQenCV ) system memory section 19-2 is prepared, and if any failure such as a parity error occurs in the data memory section during N system operation, it will immediately switch to the E system side.
It is designed to improve the reliability of the device.

(Problems to be Solved by the Invention) However, in the device with the above configuration, the data memory section is a memory with a high operating speed, for example, an ECL with high power consumption.
It had to be constructed from memory, and as a result, the external circuit had to use an ECL circuit as well. Furthermore, since data memory sections for N and E systems having the same channel capacity are provided as a redundant configuration, the number of hardware units is doubled, which is uneconomical. Furthermore, since the multiplexing section and the demultiplexing section are provided outside the data memory section, there are problems in that the amount of hardware increases and the reliability inevitably decreases.

The present invention eliminates the above-mentioned problems such as the need for high-speed memory, the increase in hardware due to two systems of N and E systems, and the increase in hardware for external circuits, and allows the use of general-purpose CMOS memory. The objective is to provide a low power consumption and highly reliable line setting circuit that can also reduce the amount of hardware.

(Means for Solving the Problems) In order to solve the above-mentioned problems, in the present invention, in a line setting circuit of a synchronous multiplex converter that sets up lines by exchanging time slots of digital multiplexed signals, the total line setting capacity is N line setting data memory circuits having a capacity of 1/N of , and a spare data memory circuit having the same capacity as the vA setting data memory circuit are connected in parallel to the input line, respectively. Connect, the previous time I! A signal selection circuit that selectively sends outputs from the setting and backup data memory circuits to an output line, read control information that controls reading from the line setting data memory circuit, and a signal selection circuit. and an address control circuit that transmits switching information for switching control, and based on fault information of the data memory circuit for line setting, read control information of the data memory circuit in which the fault has been detected is transmitted to the spare data memory. I added it to the circuit.

(Operation) According to the present invention, without multiplexing signals on a line,
The contents of the N data memory circuits are written in parallel as they are, and the contents of the N data memory circuits are sequentially read out according to the read control information, and the signal selection circuit performs time slot conversion by switching and sending out the original signal. Output as a signal with the same transmission speed as .

(Embodiment) FIG. 1 is a block diagram showing an embodiment of the present invention,
Input signal (Line > IN1 to IN4 are 8 Mb/s octet parallel signals and each has 960 channels of signal, and the line setting data has a capacity of 1/4 of the total line setting capacity, here 3840 channels. Memory circuit 2
It is led in parallel to four circuits 4-1 to 24-4. The spare data memory circuit 25 is composed of the same circuit as the data memory circuit 24, and similarly to the data memory circuit 24, input signals IN1 to IN4 are guided thereto. Data memory circuit 24
The operations of -1 to 24-4.25 are basically the same as those explained in FIG. Write sequentially to -1 to 26-4. Therefore, all 3840 channels of input signals are stored in the data memory sections 26-1 to 26-4. Reading from the data memory sections 26-1 to 26-4 is performed by the address control memory (ACM) 2 of the address control circuit 27.
Read control information 29-1 to 29-4 of 8-1 to 28-4
is applied to the data memory units 26-1 to 26-4 for execution. The information read from the data memory sections 26-1 to 26-4 is selected by a selection circuit (SEL>30).
is selected for each bit of 8 Mb/s and becomes the output signal 31. Therefore, one of the data memory circuits 24-1 to 24-4 can select any 9 of the 3840 channels.
Since 60 channels are read out after time slot conversion, a line setting circuit for 3840 channels can be realized using four data memory circuits 24-1 to 24-4. Note that the operating speed of this data memory circuit is 8 Mb/write speed.
Since the reading speed is 8 Mb/s, a general-purpose CVOS memory can be used with low power consumption in either the parallel double buffer circuit or the serial double buffer circuit.

The spare data memory circuit 25 operates in the same way as the other data memory circuits 24-1 to 24-4, but differs in the way it provides read control information 29-5 for reading. Information 3 such as data memory unit failure information and forced switching command information sent from each data memory circuit 24-1 to 24-4
2 and sends out appropriate switching information 33 (
CONT) 34, the read control information 29-5 is selected by the selection circuit (SEL) 35. This selected read control information 29-5 is given to the spare data memory circuit 25.

Therefore, the faulty data memory circuits 24-1 to 24-4
The read control information that had been given to the faulty circuit is given to the backup data memory circuit 25, which performs the same function as the faulty data memory circuit.

Further, the switching information 33 is given to a signal selection circuit (SEL) 36. In the signal selection circuit 36, the data memory circuit 24
The four output signals read from -1 to 24-4,
One signal read out from the preliminary circuit is switched using the switching information 33, and four output signals 0tJT1 to 0t are generated.
Send as JT4.

By controlling these switching functions in consideration of the operating frame of the line setting circuit, lines can be switched without momentary interruption.

(Effects of the Invention) As explained above, according to the present invention, the line setting memory has a parallel configuration that can be processed at low speed, so a general-purpose CMOS memory can be used, and input signals can be multiplexed. Since there is no need to do this, there is no need for a large-scale external circuit.

In addition, as a redundant configuration, there is no need for memory of the same capacity as the total line setting capacity as in the past, but 1/N of the line setting total capacity.
Since it is only necessary to provide a memory with the same capacity as the memory for setting the line, the overall amount of hardware can be reduced, and there are advantages such as being able to provide a highly reliable circuit with low power consumption.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the line setting circuit of the present invention, Fig. 2 is a block diagram showing the line setting and multiple conversion function section of a synchronous multiplex converter, and Fig. 3 is the basics of the line setting circuit. FIG. 4 is a block diagram showing the structure of a conventional line setting circuit. 24-1 to 24-4... Data memory circuit for line setting, 25... Data memory circuit for backup, 26-1 to
26-4...Data memory section, 27...Address control circuit, 28-1 to 28-4...Address control memory, 29-1 to 29-5...Reading control information,
33...Switching information, 36...Signal selection circuit. Patent Applicant Oki Electric Industry Co., Ltd. Nippon Telegraph and Telephone Corporation Agent Patent Attorney Furu 1) Sei Takashi 1゜Figure 3 18: Tata grip Deich 17' 21: Minutes @ Rabbit Figure 4

Claims (1)

[Scope of Claims] In a line setting circuit of a synchronous multiplex converter that sets up lines by exchanging time slots of digital multiplexed signals, N lines for setting up N lines having a capacity of 1/N of the total line setting capacity are provided. A data memory circuit and a spare data memory circuit having the same capacity as the line setting data memory circuit are connected in parallel to the input line, and data from the line setting and spare data memory circuits is connected in parallel to the input line. A signal selection circuit that selectively sends an output to an output line, read control information that controls reading from the line setting data memory circuit, and address control that sends switching information that controls switching of the signal selection circuit. circuit, and based on the fault information of the data memory circuit for line setting,
A line setting circuit characterized in that the read control information of the data memory circuit in which the fault has been detected is given to the backup data memory circuit.