JPH04277952A - Cross-connecter - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

(Table of Contents) Industrial Application Fields Prior Art (FIG. 5) Problems to be Solved by the Invention Means for Solving Problems (FIG. 1) Working Example (a) Description of One Embodiment (FIG. 2) 4) (b) Description of other embodiments Effects of the invention

0002

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cross-connect device for transmitting frame signals from each of a plurality of multiplex transmission paths to a set multiplex transmission path.

[0003] With the expansion of networks in recent years, it is desired to operate the networks efficiently.

[0004] In order to operate a network efficiently, it is necessary to efficiently transfer signals on multiple transmission paths to a predetermined transmission path. A cross-connect device is used that sends out signals to multiplexed transmission paths set up.

[0005] In addition to sending the frame signal of each multiplex transmission path to another set multiplex transmission path, this cross-connect device also exchanges the time slot of the frame signal of each multiplex transmission path with the time slot of the broadcast path. , the frame signals of each multiplex transmission path are separated, the signals to the same channel are extracted, and the frame signals are assembled or multiplexed into empty time slots.

[0006] Such a cross-connect device is required to have high reliability because it accommodates a large number of transmission lines.

[0007]

2. Description of the Related Art FIG. 5 is an explanatory diagram of the prior art.

As shown in FIG. 5, a cross-connect device 1
The system exchanges signals on each multiplex transmission path of the multiplexing device 2 that multiplexes the signals of the exchange 3 and the transmission device 4, and sends the signal of one multiplex transmission path to the other set multiplex transmission path. be.

This cross-connect device 1 includes interface sections 11 to 1n that interface with each transmission path, a control section 21 that sends out path setting information, and a frame signal from each interface section 11 to 1n based on the path setting information. It has a switch section 20 that sends out the signal to the interface sections 11 to 1n of channels set in units of time slots.

The switch section 20 is composed of a memory and a memory control circuit, writes the frame signals of each interface section 11 to 1n into the memory, reads the signal to be output based on the path setting information from the control section 21, The signal is multiplexed into the time slot of the set channel and sent to the interface sections 11 to 1n of that channel.

[0011]

[Problems to be Solved by the Invention] However, this prior art has the following problems.

[0012] Since the switch section 20 is common, if a failure occurs in the switch section 20, it will affect all the transmission lines accommodated, and the system will go down.

(2) Since the switch section 20 is common, the device becomes large and it is difficult to downsize the device.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a cross-connect device that can continue operating even if a failure occurs in the switch section and can be made smaller.

[0015]

[Means for Solving the Problems] FIG. 1 is a diagram showing the principle of the present invention.

[0016] Claim 1 of the present invention has a plurality of interface sections 11-1n each connected to a transmission path, and the interface sections 11-1n of a discharge path are set to receive input signals from the interface sections 11-1n. 1n, inputs the input signals of the respective interface sections 11 to 1n to the respective interface sections 11 to 1n, and selects the input signals from the respective interface sections 11 to 1n based on setting information. , a switch section 10 for setting a discharge path is provided in each of the interface sections 11 to 1n.

[0017] Claim 2 of the present invention provides the following in claim 1:
The switch unit 10 connects each of the interface units 11 to
It is characterized by having a plurality of memories 101a to 10nb corresponding to 1n, and a selection circuit 100 that selects outputs from the plurality of memories 101a to 10nb based on setting information.

[0018] Claim 3 of the present invention provides the following:
The present invention is characterized in that each of the plurality of memories 101a to 10nb is constituted by a pair of memories that can be read and written to alternately.

Claim 4 of the present invention provides the following:
The present invention is characterized in that it includes a memory control section 110 that controls the reading order of the plurality of memories 101a to 10nb, and multiplexes and outputs signals to be output in designated time slots.

[0020]

[Operation] According to claim 1 of the present invention, each interface section 1
1 to 1n input signals to the respective interface sections 11 to 1n.
At the same time, the switch unit 10 for setting the discharge path by selecting the input signal from each interface unit 11 to 1n based on the setting information is connected to each interface unit 11 to 1n.
1n, and the switch sections are distributed in each interface section.

Therefore, even if a failure occurs in the switch section,
Since the influence of the failure can be limited to only a part of the transmission path, and the entire system is not brought down, the device can be made smaller because it is distributed.

In claim 2 of the present invention, since the switch section is constituted by a plurality of memories and a selection circuit, it is possible to easily multiplex and output signals in designated time slots even in a distributed configuration.

According to claim 3 of the present invention, since the memory of the switch section is constituted by a pair of memories, continuous multiplexed signals can be continuously output to the air.

[0024] According to the fourth aspect of the present invention, since a memory control section is provided to control the reading order of the memory of the switch section, the signals to be output can be easily multiplexed and output in a designated time slot.

[0025]

Embodiment (a) Description of an Embodiment FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a block diagram of a switch section of an embodiment of the present invention.

In the figures, the same parts as those shown in FIGS. 1 and 5 are indicated by the same symbols.

In FIG. 2, each interface section 11 to
1n is a code conversion unit 30 that converts a frame input signal from a transmission path into a common code, a frame synchronization unit 31 that synchronizes the code-converted frame signal, and an elastic memory that stores the synchronized frame signal. 32 and frame signals from each of the interface units 11 to 1n are input, and according to path setting information from the control unit 21 (see FIG. 1), signals to be output are selected and multiplexed into designated time slots. A switch unit (data memory) 10 and a frame configuration unit 33 that configures a selected signal into a frame.
and a code conversion unit 34 that converts the frame signal into a transmission line code.

Therefore, each of the interface sections 11 to 1n includes a switch section 10 to which the frame signal of the transmission line from each of the interface sections 11 to 1n is input.

As shown in FIG. 3, this switch unit 10 includes a pair of memories 101a, 101b to 10na, 10nb provided corresponding to each interface unit 11 to 1n.
, a selection circuit 100 that selects the readout output of the memories 101a, 101b to 10na, and 10nb, and a selection circuit 100 that selects the readout outputs of the memories 101a, 101b to 10nb according to the path setting information of the control unit 21.
0na, 10nb write/read control and selection circuit 1
Memory (read/write) control unit 1 that instructs selection to 00
10.

[0030] These memories 101a, 101b to 10na
, 10nb each have a capacity for one frame and form a double buffer structure, and write/read is alternately repeated in units of transmission line frames. At the time of writing, the received data from the interface units 11 to 1n are sequentially written in the order of input, and at the time of reading, the memory is randomly accessed and read based on the path setting information, and the selection circuit 10
0 selects the memory output, frames are constructed in the specified time slot order, and transmitted.

FIG. 4 is an explanatory diagram of the operation of one embodiment of the present invention.

[0032] The frame signals from each transmission path are input to the code conversion unit 30 of each interface unit 11 to 1n, where they are code converted, frame synchronized by the frame synchronization unit 31, and stored in the elastic memory 32. Thereafter, the signal is input to the switch section 10 of each interface section 11 to 1n.

In each switch section 10, as shown in FIG.
b, and the other memory 101b to 10nb or 1
01a to 10na are read out according to the path setting information.

This path setting information is a transmission path number and a time slot number for each time slot number of the transmission path of the interface section that has been released, and the memory control section 110 sets the address of the time slot number of the read side memory. After reading the position, the selection circuit 100 selects the memory corresponding to the transmission line number.

For example, in the example of FIG. 4, while data of one frame from "a" to "x" is being written to the memory 101a, the data of the memory 101b is read out, and then the data of the memory 101a is read out. Write data to memory 101b.

At this time, reading of the memory is performed according to the path setting information, and in the example of FIG. will be held.

The output of the selection circuit 100 is sent to the frame configuring section 33 where it is constructed into a frame, code-converted by the code converting section 34, and output to the transmission line.

In this way, each interface section 11
By distributing the switch units 10 that receive the outputs of the interface units 11 to 1n as inputs, even if a failure occurs in one switch unit, it will not affect the entire transmission path, thereby improving system operation. I can take care of it.

(b) Description of other embodiments In addition to the embodiments described above, the present invention can be modified as follows.

(2) Although the memory of the switch unit has been described as a double buffer type, it may also be a multi-stage buffer type.

(2) A memory or the like is used to make each switch section 10 have a common configuration, but a combination of switches may also be used.

The present invention has been explained above using examples, but
Various modifications are possible within the scope of the present invention, and these are not excluded from the scope of the present invention.

[0043]

[Effects of the Invention] As explained above, according to the present invention,
It has the following effects.

■ Inputting the input signals of each interface section 11 to 1n to each interface section 11 to 1n, and selecting the input signal from each interface section 11 to 1n based on setting information to set a discharge path. Since the switch unit 10 is provided in each interface unit 11 to 1n,
The switch units can be distributed and arranged in each interface unit, and even if a switch unit fails, the effect of the failure can be limited to only a part of the transmission path, and does not cause the entire system to go down.

(2) Since the switch sections are distributed, the device can be made compact.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is a configuration diagram of a switch section according to an embodiment of the present invention.

FIG. 4 is an explanatory diagram of the operation of one embodiment of the present invention.

FIG. 5 is an explanatory diagram of the prior art.

[Explanation of symbols]

1 Cross-connect device 11~1n Interface part 10 Switch part 21 Control section

Claims (4)

[Claims] Claim 1: A plurality of interface sections (11 to 1n) each connected to a transmission path, and an input signal from the interface section (11 to 1n) is set to a discharge path interface section (11 to 1n). ), in which input signals from each interface section (11 to 1n) are input to each interface section (11 to 1n), and input signals from each interface section (11 to 1n) are input to each interface section (11 to 1n). A cross-connect device characterized in that each of the interface sections (11 to 1n) is provided with a switch section (10) for selecting and setting a release path based on setting information. 2. The switch unit (10) includes a plurality of memories (101a to 10nb) corresponding to each of the interface units (11 to 1n), and a plurality of memories (101a to 10nb) corresponding to the respective interface units (11 to 1n).
2. The cross-connect device according to claim 1, further comprising a selection circuit (100) for selecting an output from the 10nb) based on setting information. 3. The plurality of memories (101a to 10n
3. The cross-connect device according to claim 2, wherein each of (b) comprises a pair of memories that can be read and written alternately. 4. The plurality of memories (101a to 10n
3. The cross-connect device according to claim 2, further comprising a memory control unit (110) for controlling the reading order in step (b), and multiplexing and outputting the signals to be output in designated time slots.