JPS6255314B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a field effect transistor in which the flow rate of carriers distributed in a quasi-one-dimensional state with high mobility is controlled by an electric field.

FIG. 1 shows an example of a conventional field effect semiconductor device in which the flow rate of carriers distributed in a quasi-one-dimensional state is controlled by an electric field. In Figure 1, 1 is 1
Epitaxial P-GaAlAs with a thickness around μm
The layers 2 are a P-GaAs layer of about 200 Å, 3 a P-GaAlAs layer of about 1000 Å, 4 an insulator thin film layer, 5 a gate electrode, and 6 an n-type inversion layer.

The positive bias voltage applied to the gate electrode 5 inverts the P--GaAs layer 2 to a depth of about 100 A through the insulator thin film 4, forming two channel layers on the left and right for electrons distributed in a quasi-one-dimensional state.

Generally, there are quite a lot of interface states formed at the junction interface between GaAs and an insulator, so the structure shown in FIG. 1 has a drawback in that it is not easy to form the inversion layer 6.

In addition, the bonding interface between GaAs and the insulating layer is generally uneven at the atomic level, and the P-GaAs layer 2
quasi-one-dimensional electrons in the inversion layer 6 formed at the interface of the insulator thin film layer 4 When a flow occurs, electrons are scattered at this rough junction interface, resulting in a decrease in mobility.

This invention was made in order to eliminate the above-mentioned conventional drawbacks, and provides a field effect transistor that is capable of high-speed switching operation at a low temperature of about 77K and that enables high-speed operation when used in an arithmetic circuit of an electronic computer. The purpose is to

Embodiments of the field effect transistor of the present invention will be described below with reference to the drawings. FIG. 2a is a perspective view showing the structure of one embodiment. This second
In Figure a, 21 is an impurity-free GaAs layer with a thickness of about 1 μm epitaxially grown on a semi-insulating GaAs substrate. On this GaAs layer 21, n ⁺
−Ga ₀ . ₇ Al ₀ . ₃ As layer 22, GaAs layer 23, n ⁺ −
A Ga _{0 .7} Al _{0 .3} As layer 22 and a GaAs layer 24 are formed by laminating one after another, forming a superlattice structure.

The n ⁺ −Ga ₀ . ₇ Al ₀ . ₃ As layer 22 is a 5× layer with Si added.
The GaAs layer 23 is formed to a thickness of about 200 Å with an electron density of about 10 ¹⁷ cm ^-3 , and the GaAs layer 23 is about 100 Å thick without any impurities added. It has a thickness of approximately 1000 Å. 25 is a Schottky junction with a depth of about 1500
26 is a Pt gate electrode with a width of 2000 Å, and a fine pattern of PMMA resist that is sensitive to the deep ultraviolet region is created on the GaAs surface using a mask made by electron beam exposure and deep ultraviolet light. Approximately 2000 Å width of approximately 2000 Å left by etching with energetic Ar ion beam
It is a plateau with almost vertical walls at a depth of .

27 is the impurity-free GaAs in this plateau 26
Formed in the layers 21, 23, and 24, the extent in the depth direction is approximately 100 Å, and the extent in the direction of the gate electrode is approximately 500 Å.
It is a channel of electrons in a quasi-one-dimensional state of Å.

FIG. 2b is an energy band diagram in a direction along the front sectional view of FIG. 2a. In the state shown in Figure 2 a
FET in depression mode at low temperature of about 77K
If the width of the plateau 26 is narrowed or the electron density of the n ⁺ _{-Ga 0.7} Al _0.3 As layer ₂₂ is somewhat reduced, an enhancement mode FET can be operated at a low temperature of about 77K. .

To make this work, a high concentration of Si was added.
Highly concentrated electrons supplied from donor atoms in the n ⁺ _−Ga 0 . ₇ Al ₀ . ₃ As layer 22 are diffused into the GaAs channel 27 to create a quasi-one-dimensional electron distribution and form a Schottky junction. The amount of current flowing is controlled by widening or narrowing the width of the channel 27 according to the bias voltage applied to the gate electrode 25.

Such a structure can be realized by changing the combination _of GaAs and Ga _0.7 Al _0.3 As, for example _,
In _0.53 Ga _0.47 As/instead of GaAs _{/ Ga 0.7 Al 0.3 As
Examples include InP and Ga 0.47 In 0.53} As/ _{Al 0.48 In 0.52 As .}

As explained above, in the first embodiment, three layers of electron channels 27 in a quasi-one-dimensional state are formed between two gate electrodes 25 forming a Schottky junction. Electrons in a quasi-one-dimensional state flow due to the electric field applied between the source and drain, but their movement direction is only allowed in one-dimensional direction, so they are scattered by impurity ion scattering, which is the dominant electron scattering source at 77K. Probability decreases. Therefore, the mobility of an electron in a quasi-one-dimensional state becomes larger than that of a three-dimensional electron or a quasi-two-dimensional electron at 77K.
The operating speed of the FET shown in Figure 2a is compared to that of conventional GaAs.
It is possible to make it considerably larger than FET.

In addition, in FIG. 2a, since the gate electrode 25 of the Schottky junction is arranged so as to sandwich the channel 27 from both sides, a quasi-one-dimensional electron distribution is formed in the semiconductor, and electrons are scattered by the rough Schottky junction interface. High-speed operation is possible because it can flow without being affected.

FIG. 3a is a perspective view showing the configuration of a second embodiment of the present invention, FIG. 3b is a cross-sectional view taken along line BB in FIG. 3a, and FIG. FIG. 3 is a sectional view taken along line CC of FIG. In FIGS. 3a to 3c, the contents indicated by numerals 21 to 26 are the same as the contents indicated by the same numbers in FIG. 2a.

28 and 29 are made of GaAs using the same photolithography technique as explained in the first embodiment.
A depression with a depth of about 2000 Å reaching the deepest part of layer 23 was made, and about 2000 Å was buried in the depression.
28 is a source electrode and 29 is a drain electrode. Also,
Reference numeral 30 denotes an Au gate electrode that connects the four gate electrodes 25.

In this second embodiment, there are five layers in the depth direction of channels having quasi-one-dimensional electron distribution, and three examples of plateaus 26 in the direction parallel to the layers. Therefore, a total of 15 channels of electrons in a quasi-one-dimensional state are formed, and the resistance value between the source and drain decreases. If the number of GaAs layers 23 and the number of plateaus 26 are further increased, the resistance between the source and drain will be greatly reduced, and the resistance between the source and drain will be sufficient for practical use.

This second embodiment is similar to the first embodiment.
The combination of GaAs/ _{Ga 0.7} Al _{0.3 As}
In _{0. 53} Ga _{0. 47} As/InP and Ga _{0. 47} In _{0. 53} As/
_It can be _{Al0.48In0.52As , etc.}

As described above, according to the field effect transistor of the present invention, a channel with high free electron density and high electrical conductivity through which carriers in a quasi-one-dimensional state flow is formed at a position deeper than the semiconductor surface, and the channel is arranged parallel to the channel. Since the flow rate of the carrier in the channel sandwiched between the gate electrodes is controlled by the bias voltage applied to the gate electrodes of the two Schottky junctions, high-speed switching operation is possible at a low temperature of about 77K. be. Therefore, by using it in an arithmetic circuit of an electronic computer, high-speed calculation becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a conventional quasi-one-dimensional channel MISFET formed in a V-shaped groove, FIG. 2a is a perspective view showing the structure of an embodiment of a field effect transistor of the present invention, and FIG. 2b is the energy band diagram of FIG. 2a, FIG. 3a is a perspective view of the second embodiment of the field effect transistor of the present invention, and FIG.
BB line sectional view in Figure a, Figure 3 c is C in Figure 3 a
-C line sectional view. 21, 23, 24...GaAs layer, 22...n ⁺ -
_{Ga0.7Al0.3As layer} , 25 _... gate electrode, 26 _...
Plateau, 27... Channel, 28... Source electrode, 29... Drain electrode, 30... Gate coupling electrode.

Claims (1)

[Claims] 1 At least one layer consisting of an n or n ⁺ semiconductor layer with a relatively low electron affinity and a first layer with a sufficiently low impurity density and a high free electron density and a high electrical conductivity channel with a relatively high electron affinity. There are two parallel pairs of superlattice structures formed by stacking the above layers alternately and Schottky junctions arranged on the side surface perpendicular to the interface of this superlattice structure so as to sandwich this superlattice structure. The distance was set so that the electrons accumulated in the first layer sandwiched between the Schottky barrier potentials of It consists of a gate electrode, and a source electrode and a drain electrode formed in the superlattice structure so as to sandwich the gate electrode, and by applying a voltage between the source electrode and the drain electrode, the quasi-one-dimensional electron gas is generated. A field-effect transistor characterized in that the flow rate of quasi-one-dimensional electron gas is controlled by a bias voltage applied to the gate electrode and flowing in the direction along the gate electrode surface and the first layer.