JPS5931071A - field effect transistor - Google Patents

Abstract

PURPOSE:To enable high speed switching action at a low temperature of approx. 77K by a method wherein the amount of flow of carriers distributed in a quasi one-dimensinal state having high mobility is controlled by an electric field. CONSTITUTION:An N<+>-GaAlAs layer 22, GaAs layer 23, an N<+>-Ga0.7Al0.3As layer 22, and a GaAs layer 24 are successively laminated and formed on an impurity non-doped GaAs layer 21 epitaxially grown on a semi-insulation GaAs substrate, and accordingly an ultra lattice structural part is formed by means of them. The layer 22 is formed to a thickness of approx. 200Angstrom having the electron density of approx. 5X10<17>cm<-3> doped with Si, and the layer 23 is not doped with impurity and has a thickness of 100Angstrom approx. The layer 24 is not doped with impurity and has a thickness of 1,000Angstrom . Pt gate electrodes 25 has Schottky junctions. The expansion in the depth direction formed in the GaAs layers 21, 23, and 24 in a plateau 26 is an electron channel in the quasi onedimensional state. Then, the flow of current is controlled by controlling the bias voltage of the electrodes 25.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a field effect transistor in which the flow rate of carriers distributed in a quasi-dimensional state with high mobility is controlled by an electric field.

FIG. 1 shows an example of a conventional field effect semiconductor device in which the flow rate of carriers distributed in a quasi-dimensional state is controlled by an electric field. In Fig. 1, 1 is an epitaxial P-GaAtAs layer e with a thickness of about 1 μm, 2 is a P-GaAs layer with a thickness of about 200X, and 3 is a P-GaAs layer with a thickness of about 100X.
4 is an AtAs layer, 4 is an insulating thin film layer, 5 is a dart electrode, and 6 is an n-type inversion layer.

The positive bias voltage applied to the dart electrode 5 inverts the P-GaAs layer 2 to a depth of about 100 A through the entire insulator thin film 4, forming two electron channels NII on the left and right that are distributed in a quasi-dimensional state. do.

Since there are many p interface states formed at the junction interface between general KQaAs and an insulator, the structure shown in FIG. 1 has the disadvantage that it is not easy to form the inversion layer 6.

Furthermore, the bonding interface between GaAs and the insulating layer is generally uneven in size at the atomic level, and the quasi-dimensional electrons (inverted (Electrons that are in a state where the spread of electrons accumulated in layer 6 in the direction of the interface is shorter than the mean free path of the electrons)
When a flow occurs, electrons are scattered at this rough junction interface, resulting in a decrease in mobility.

This invention was made in order to eliminate the above-mentioned drawbacks of the conventional technology, and it uses a field effect transistor that is capable of high-speed switching operation at a low temperature of about 77°C, and that enables high-speed operation when used in an arithmetic circuit of an electronic computer. The purpose is to provide.

Embodiments of the field effect transistor of the present invention will be described below with reference to the drawings. FIG. 2(a) is a perspective view showing the configuration of one embodiment. In FIG. 2(a), 21 is an impurity-free GaAs layer with a thickness of about 1 μm epitaxially grown on a semi-insulating GaAs substrate.

On this GaAs layer 21 is n+-Ga (1,7Ato,
3As layer 22, GaAs layer 23, n+-Ga
o, 7Ato, 3As layers 22 and GaAsN 24 are sequentially stacked to form a superlattice structure.

n+-Gao, 2At (1,3As layer 22 is Si k doped with about 5x10 cm of electrons)
The GaAs layer 23 is formed to a thickness of about
The aAs layer 24 does not contain any impurities and has a thickness of about 1000H. 25 is about 1 inch deeper than the Schottky junction.
50 OA, tJullf%2000A(D pt
(Dy-meter electrode, 26 is made of 9 fine f-turn fGaAs made of PMMA Lenost which has a photosensitizing effect in the far ultraviolet region using a mask made by electron beam exposure and deep ultraviolet light.
It is a plateau with approximately vertical walls approximately 200 OA wide and approximately 2000× deep, created on the surface and left by etching with a low-energy Ar ion beam.

Impurity-free GaAs layer 21°23 within this plateau 26
．． The depth direction spread 9 formed within 24 is approximately 10OA,
) f″-t is a channel of electrons in a quasi-dimensional state with a polar extent of about 50 OA.

FIG. 2(b) is an energy band diagram in a direction along the front sectional view of FIG. 2(a). In the state shown in Figure 2(a), 7
Either operate the FET in depression mode at a low temperature of about 7 K and narrow the width of the plateau 26.
If the electron density of Ga(1,7Ato4As/122) is reduced somewhat, it will operate as an enhancement mode FET at a low temperature of about 77°C.

To make this work, n Gao, 7Ato, aAB
By doping St in layer 22 at a high concentration, fr-n-Gao, 7
Highly concentrated electrons f supplied from inner atoms in the Ato, BAsAs layer 2 are diffused into the channel 7 of GaAs, creating an electron distribution in a quasi-dimensional state, and are applied to the dart electrode 25 forming a Schottky junction. The amount of current flowing is controlled by widening or narrowing the width of the channel 270 using a bias voltage.

Such structures include GaAs, Gao, 7Ato, 3As
It can also be realized by changing the combination of - For example, QaA
, s/Ga□, 7Ato, Ino instead of 3As, 5
3Gao, 47As/InP and Gao, 47In
o, 5aAs/Ato, taIno, 52As, etc.

As explained above, in the first embodiment, three layers of electron channels 27 in a quasi-dimensional state are formed between gate voltages 25 forming two Schottky junctions.

Electrons in a quasi-dimensional state flow due to the electric field applied between the source and drain, but since the direction of movement is only allowed in one dimension, the scattering probability due to impurity ion scattering, which is the dominant electron scattering source in 77. decreases. Therefore, the mobility of an electron in a quasi-dimensional state is Q larger than that of a three-dimensional electron or a quasi-two-dimensional electron at 77K, as shown in Figure 2 (
a) The operating speed of the FET shown in K is compared to that of the conventional GaAs FET.
It is possible to make it considerably larger than ET.

In addition, in FIG. 2(a), since the Schottky junction f-) electrodes 25 are arranged so as to sandwich the channel 27 from both sides, a quasi-dimensional electron distribution is formed in the semiconductor, and the electrons become rough. High-speed operation is possible because it can flow without being scattered by the Schottky junction interface.

FIG. 3(a) is a perspective view showing the configuration of a second embodiment of the present invention, and FIG. 3(b) is a sectional view taken along line A-A in FIG. 3(a). FIG. 3(e) is a sectional view taken along the line CC in FIG. 3(a). In these Figures 3(a) to 3(C), the contents indicated by the symbols 21 to 26 are shown in Figure 2(a).
) is the same as the content indicated by the same number.

28 and 29 utilize the same photolithography technique as explained in the first embodiment to fabricate a depression with a depth of about 200 OA reaching the deepest part of the QaAs layer 23, and to fill it in the depression. approximately 2000X thick AuG
e/Ni ohmic electrode, 28 is the source electrode, 2
9 is a drain electrode.

In addition, 30 is an Au r that connects the four dart electrodes 25.
-) It is an electrode.

In this second embodiment, the channel with the distribution of electrons in the quasi-dimensional state is 5 m deep and there are three plateaus 26 in the direction parallel to the layer. Therefore, a total of 15 quasi-dimensional electron channels are formed, and the resistance value between the source and drain is reduced. G a A,
If the number of s-layers 23 and the number of plateaus 26 are further increased, the resistance between the source and drain will be greatly reduced, and the resistance between the source and drain will be sufficient for practical use.

This second embodiment uses a GaAs layer like the first embodiment.
Ga(1,7At(1,3Aa combination Ino,
5aGao, nAs/InP and Gao, 47Ino
, 5aAs/Ato, 4BIno, 52As, etc.

As described above, according to the field effect transistor of the present invention, a channel having a high free electron density and high electrical conductivity through which carriers in a quasi-dimensional state flow is formed at a position deeper than the semiconductor surface, and is arranged parallel to the channel. The flow of carriers in the channel sandwiched between the gate electrodes was controlled by the bias voltage applied to the two Schottky junction gate electrodes. High-speed switching operation is possible. Therefore, by using it in an arithmetic circuit of an electronic computer, high-speed calculation becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a conventional quasi-dimensional channel MISFET formed in a V-shaped groove, and FIG. 2(a) is a perspective view showing the configuration of an embodiment of a field effect transistor of the present invention.
FIG. 2(b) is the energy band diagram of FIG. 2(a), FIG. 3(a) is a perspective view of the second embodiment of the field effect transistor of the present invention, and FIG. FIG. 3(C) is a sectional view taken along line B-B in FIG. 3(a), and FIG. 3(C) is a sectional view taken along line C-C in FIG. 21, 23, 24-GaAs layer, 22-・n''-G
ao, 7Ato, 3Aa NIJ, 25-? −)
Electrode, 26-...Plateau, 27...Channel, 28-
...Source electrode, 29...Drain electrode, 30...
Kate-coupled electrode. Patent Applicant Oki Electric Industry Co., Ltd. Procedural Amendment May 1-8, 1980 Kazuo Wakasugi, Commissioner of the Patent Office1, Indication of the Case 1981 Patent Application No. 1396862, Title of Invention Field Effect Transistor 3. Relationship with the case of the person making the amendment Patent Applicant (029) Oki Electric Industry Co., Ltd. 4, Agent 5, Date of amendment order Showa Year Month El (
Voluntary) 6. Claims and Detailed Description of the Invention column of the specification to be amended and part of the drawings 7. Contents of the amendment As shown in the attached sheet 7. Contents of the amendment 1) ``2. "Range" is corrected as shown in the attached sheet. 2) Specification page 4 line 7 r Gao, 2J f r Gao
, y J. 3) On page 4, line 13, rptJ is corrected to rPtJ. 4) Correct “this plateau” on page 5, line 1 to “27 is this plateau” 1゜5) Page 5, lines 12 and 13 r n+Gao, 7At
o, 3As layer 22' is deleted. 6) On page 5, line 15, "7" is corrected to "27". 7) On page 7, line 4, correct "rA-A line" to "rB-B line". 8) On page 8, lines 16 and 17, "flow" is corrected to "flow rate." 9) Correct the drawing Figure 2 (a) as shown in the attached sheet. 2. Claims: an n or n semiconductor layer with a relatively low electron affinity; a first layer with a relatively high electron affinity and a channel having a sufficiently low impurity density and high free electron density and high electrical conductivity; A superlattice structure formed by alternately stacking at least one or more layers of and a quasi-dimensional electron state in which the spread of electrons accumulated in the first layer formed between two Schottky barrier potentials in the direction of the interface is shorter than the mean free path of the electrons. The superlattice structure consists of a gate electrode with a distance set so that The quasi-dimensional electron gas is caused to flow in a direction toward the gate electrode surface and the first layer 7, and the flow rate of the quasi-dimensional electron gas is controlled by a bias voltage applied to the gate electrode. Field effect transistor.

Claims (1)

[Claims] An n or n1 conductor layer with a relatively low electron affinity, a first layer with a relatively high electron affinity and a channel having a sufficiently low carrier density and high free electron density and high electrical conductivity; A superlattice structure formed by laminating at least one or more layers alternately, and a parallel pair of Schottky junctions arranged on sides perpendicular to the interface of this superlattice structure so as to sandwich this superlattice structure. This is a complaint of quasi-dimensional electrons in which the spread of electrons accumulated in the first layer sandwiched between two Schottky barrier potentials in the direction of the interface is shorter than the mean free path of the electrons. The distance between the P-) electrode, which is set at a distance such as By applying a voltage to , the quasi-dimensional electron gas flows in the direction along the P-) electrode surface and the first layer, and f
-) A field effect transistor, characterized in that the flow rate of the quasi-dimensional electron gas is controlled by a bias voltage applied to the electrodes.