JPS6252953A - Plug-in package and manufacture of the same - Google Patents
Plug-in package and manufacture of the sameInfo
- Publication number
- JPS6252953A JPS6252953A JP60192723A JP19272385A JPS6252953A JP S6252953 A JPS6252953 A JP S6252953A JP 60192723 A JP60192723 A JP 60192723A JP 19272385 A JP19272385 A JP 19272385A JP S6252953 A JPS6252953 A JP S6252953A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- adhesive
- substrate
- temperature
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000000853 adhesive Substances 0.000 claims abstract description 36
- 230000001070 adhesive effect Effects 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000004033 plastic Substances 0.000 claims abstract description 16
- 229920003023 plastic Polymers 0.000 claims abstract description 16
- 229920001187 thermosetting polymer Polymers 0.000 claims abstract description 14
- 238000010438 heat treatment Methods 0.000 claims abstract description 6
- 239000004020 conductor Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 abstract description 8
- 229920005989 resin Polymers 0.000 abstract description 3
- 239000011347 resin Substances 0.000 abstract description 3
- 239000011231 conductive filler Substances 0.000 abstract description 2
- 239000011810 insulating material Substances 0.000 abstract 1
- 238000005476 soldering Methods 0.000 description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000005011 phenolic resin Substances 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 229920001342 Bakelite® Polymers 0.000 description 1
- 229920000049 Carbon (fiber) Polymers 0.000 description 1
- 239000004859 Copal Substances 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 241000782205 Guibourtia conjugata Species 0.000 description 1
- 229920000180 alkyd Polymers 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000004637 bakelite Substances 0.000 description 1
- QHIWVLPBUQWDMQ-UHFFFAOYSA-N butyl prop-2-enoate;methyl 2-methylprop-2-enoate;prop-2-enoic acid Chemical compound OC(=O)C=C.COC(=O)C(C)=C.CCCCOC(=O)C=C QHIWVLPBUQWDMQ-UHFFFAOYSA-N 0.000 description 1
- 239000004917 carbon fiber Substances 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002845 discoloration Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000010419 fine particle Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920001225 polyester resin Polymers 0.000 description 1
- 239000004645 polyester resin Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 229920002803 thermoplastic polyurethane Polymers 0.000 description 1
- 150000003918 triazines Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（発明の分野）
本発明はプラスチック製基板から成る半導体搭載用プラ
グインパッケージの改良に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of the Invention) The present invention relates to improvements in plug-in packages for mounting semiconductors made of plastic substrates.
（従来技術）
従来から知られるプラグインパッケージの例を第１図に
示す。(Prior Art) An example of a conventionally known plug-in package is shown in FIG.
プラグインパッケージｌには複数の７レイ状に配列する
ホール状支持部２、例えばスルーホールが形成された基
板３上に導体パターン４が形成さレル。導体パターン４
の各々の端部の片方はスルーホール２と接続され、他方
は基板上に搭載された半導体５と、ワイヤーポンド６に
よって接続される。スルーホー／Ｌ／２自体は導電処理
され、入出力ピン７がスルーホール２に嵌入され、ラン
ド部８にて固定される。In the plug-in package 1, a conductor pattern 4 is formed on a substrate 3 in which a plurality of hole-shaped supporting parts 2, for example, through holes, are formed in a plurality of seven layers. Conductor pattern 4
One end of each is connected to the through hole 2, and the other end is connected to the semiconductor 5 mounted on the substrate by a wire pond 6. The through hole/L/2 itself is treated to be conductive, and the input/output pin 7 is fitted into the through hole 2 and fixed at the land portion 8.
通常、このようなプラグインパッケージニ用いられる基
板としてはセラミック製のものがその高信頼性の点から
活用されつつあるが、セラミック自体が脆い、また加工
が困難である、製造上の寸法安定性に劣る、比重が大き
い、高価である等の欠点から、プラスチック製基板が有
望視されている。Usually, ceramic substrates are being used for such plug-in packages due to their high reliability, but ceramics themselves are brittle, difficult to process, and have poor dimensional stability during manufacturing. Plastic substrates are viewed as promising due to drawbacks such as poor performance, high specific gravity, and high cost.
従来、このようなプラグインパッケージにおける入出力
ピンの固定はスルーホールに対し、入出力ピンを圧入、
かしめ、ハンダ付、銀ロウ付等の方法によって行なわれ
ていた。Conventionally, the input/output pins in such plug-in packages were fixed by press-fitting the input/output pins into through holes.
This was done by caulking, soldering, silver soldering, etc.
しかしながら、圧入のみの固定では、固定強度が弱く、
かしめによる固定では基板に割れやかけが発生し易く、
特にプラスチック製基板に対しては基板の変形や、ラン
ド部の断線などを招く恐れがある。ハンダ付は固定強度
は優れるものの、後工稽
工程としてフラックスの洗浄が必要となり製ｉ項雑とな
シ、しかもパッケージをマザーボードにハンダフローで
電気的に接合する際に、加熱によりハンダが再溶融して
、ピンの揺れ、抜は等が発生し易く、作業に支障をきた
していた。そのため高融点のハンダを用いられているが
プラスチック製基板においては基板等に熱劣化を及ぼす
恐れがあった。また銀ロウ付による固定では使用温度が
更に高温であるためプラスチック製基板のパッケージに
は適用できない。However, fixing by press-fitting only has weak fixing strength.
When fixing by caulking, the board is likely to crack or chip.
In particular, for plastic substrates, there is a risk of deformation of the substrate and breakage of the land portion. Although soldering has excellent fixing strength, it requires cleaning the flux as a post-work process, making the manufacturing process complicated.Moreover, when electrically bonding the package to the motherboard using solder flow, the solder may remelt due to heating. As a result, the pins tend to swing or come loose, which hinders work. For this reason, solder with a high melting point is used, but in the case of plastic substrates, there is a risk of thermal deterioration of the substrate. Furthermore, fixing by silver soldering requires a higher operating temperature, so it cannot be applied to packages made of plastic substrates.
（発明の概要）
本発明者等は上記現状に鑑み研究の結果、デフスチック
製の基板に設けられた導電性スルーホールに対し、特定
の有機系接着剤を用いて入出力ピンを固定することＫよ
って、優れた固定強度が侵収
りするとともに製造工程も簡略されることによって高信
頼性の安価なプラグインパッケージが得うれることを知
見した。(Summary of the Invention) In view of the above-mentioned current situation, the present inventors have conducted research and found that it is possible to fix input/output pins using a specific organic adhesive to conductive through holes provided in a differential plastic substrate. Therefore, it has been found that a highly reliable and inexpensive plug-in package can be obtained by providing excellent fixing strength and simplifying the manufacturing process.
即ち、本発明によれば複数個の導電性のホール状固定部
を備えたプラスチック基板と、該基板上に設けられ該ホ
ール状固定部と目的に接続された導体パターンと、該ホ
ール状固定部に嵌入され、該導体パターンと［気的に接
続された入出力ピンを少なくとも具備したプラグインパ
ッケージにおいて、
前記入出力ピンが２００℃以下で硬化可能な熱硬化型導
電性接着剤によって前記ホール状固定部に接着固定され
たことを特徴とするプラグインパッケージが提供される
。That is, according to the present invention, there is provided a plastic substrate having a plurality of conductive hole-shaped fixing parts, a conductive pattern provided on the substrate and connected to the hole-shaped fixing parts, and the hole-shaped fixing part. In a plug-in package having at least an input/output pin fitted into the conductor pattern and electrically connected to the conductive pattern, the input/output pin is connected to the hole shape by a thermosetting conductive adhesive that can be cured at 200° C. or less. A plug-in package is provided that is adhesively fixed to a fixed part.
さらに、本発明によれば複数個の導電性のホール状支持
部と、該ホール状支持部とｔ９Ｃ的に接続され九導体パ
ターンを少なくとも具備したプラスチック製基板に対し
、入出力ピンを２００℃以下で硬化可能な熱硬化型導電
性接着剤によって前記ホール状支持部に装着する工程と
、
該基板を２００℃以下の範囲で加熱して前記接着剤を硬
化させ、前記入出力ピンを前記ホール状支持部に固定す
る工程と、
を具備したプラグインパッケージの製造方法が提供され
る。Furthermore, according to the present invention, the input/output pins are heated at a temperature below 200° C. with respect to a plurality of conductive hole-shaped support portions and a plastic substrate connected to the hole-shaped support portions in a t9C manner and provided with at least nine conductor patterns. attaching the input/output pins to the hole-shaped support by heating the substrate at a temperature of 200° C. or less to cure the adhesive; A method of manufacturing a plug-in package is provided, comprising a step of fixing it to a support.
本発明によれば、接着剤として、特に熱カ梅接着剤を用
い、しかも、硬化温度が基板の耐熱温度よシも低く、特
に２００℃以下、好ましくは１８０ ℃以下で硬化可能
な熱硬化型導電性ｐ接着剤を用いることか極めて重要で
ある。このような接着剤による入出力ピンの固定によれ
ば、ハンダ固定のようにフラックスを洗浄する必要がな
く、しかも一旦硬化した接着剤は、その後硬化時の温度
以上になっても再溶融することがないため、マザーボー
ドへの接合に際してもピンの揺れ、抜は等は発生するこ
とはない。According to the present invention, a thermosetting adhesive is used as the adhesive, and the curing temperature is lower than the heat-resistant temperature of the substrate, and in particular, a thermosetting type that can be cured at 200° C. or lower, preferably 180° C. or lower. It is extremely important to use a conductive p-adhesive. By fixing the input/output pins with such an adhesive, there is no need to clean the flux unlike with solder fixing, and once the adhesive has hardened, it will not melt again even if the temperature exceeds the temperature at which it hardens. There is no pin shaking or disconnection when bonding to the motherboard.
熱硬化型導電性接着剤の硬化可能な温度即ち、硬化最低
温度が２００℃を超えると、入出力ピンの固定時、基体
を２００℃を超える温度にさらすため、加熱によってプ
ラスチック製基板が変形等を生じ易く、基板上の導体パ
ターンの基板への接着強度劣化、または導体パターン自
体の酸化劣化あるいは、導体パターン上く形成されたレ
ジスト等が劣化、変色し易いため、高信頼性が要求され
るパッケージとしては好ましくない。なお、この接着剤
は取扱い、作業性の点から、硬化最低温度が５０℃以上
であることが望ましい。If the temperature at which the thermosetting conductive adhesive can be cured, that is, the minimum curing temperature, exceeds 200°C, the substrate will be exposed to temperatures exceeding 200°C when fixing the input/output pins, and the plastic board may become deformed due to heating. High reliability is required because the adhesive strength of the conductor pattern on the substrate to the substrate deteriorates, the conductor pattern itself deteriorates due to oxidation, or the resist formed on the conductor pattern deteriorates and discolors. I don't like it as a package. Note that, from the viewpoint of handling and workability, it is desirable that the minimum curing temperature of this adhesive is 50° C. or higher.
また、本発明において用いられる接着剤が絶碌性である
と、入出力ピンが固定されるヌルーホーＡ／またはラン
ド部が導電性ではあるがスルーホールと、入出力ピンと
の間の抵抗が大きいため、信号の伝達速度が遅くなる等
の不都合が生じる。よって、本発明の接着剤の体積固有
抵抗はｌ×１０Ω・１以下であることが望ましい。In addition, if the adhesive used in the present invention is durable, although the null hole A/or land portion to which the input/output pin is fixed is conductive, the resistance between the through hole and the input/output pin is large. , problems such as a slow signal transmission speed occur. Therefore, it is desirable that the volume resistivity of the adhesive of the present invention is 1×10Ω·1 or less.
本発明において用いられる有機系接着剤としてはエポキ
シ樹脂、フェノール樹脂、アクリル樹脂、ポリエステル
樹脂、アルキッド樹脂、ウレタン樹脂シリコン樹脂、そ
の他多くの熱硬化性樹脂を主成分をするものであって、
それ自体では絶縁性に近いために、導電性フィラーを混
合することによって、抵抗値を制御することができる。The organic adhesives used in the present invention include epoxy resins, phenolic resins, acrylic resins, polyester resins, alkyd resins, urethane resins, silicone resins, and many other thermosetting resins as main components.
Since it is almost insulating by itself, the resistance value can be controlled by mixing it with a conductive filler.
用いられるフィラーとしては金粉、ｇｉ粉、銅粉、アル
ミニウム粉汗ツケル粉、カーボン粉、グラファイト、カ
ーボン繊維、銀メツキ微粒子等が挙げられる。Examples of fillers that can be used include gold powder, GI powder, copper powder, aluminum powder, carbon powder, graphite, carbon fiber, and silver plating fine particles.
これらの中でも特に銀ペーストのエポキシ樹脂が好まし
い。このような接着剤は下記に示す商品名で市販されて
いる。Among these, silver paste epoxy resin is particularly preferred. Such adhesives are commercially available under the trade names shown below.
住友ベークライト ＣＲＭ−１０３３５Ｘ１０ＣＲＭ
−１０５０２Ｘ １０−’
神東塗料 ｐ−５ｏｒ、ｏ四３０８３ ４ Ｘ １０
束レバイソ−／Ｉ／ＫＯ０１０８３Ｘ１０−’ア ミ
コ ン Ｃ−８０５−１１ＸＩＯ”
６０．−０ ５０Ｊ
Ｉ ６０−Ｌ
１０１１ ５９−ＣｌＸｌ０また、
本発明において用いられるプラスチック製基板としては
、ガラヌーエボキシ樹脂、紙−フェノール樹脂、紙−エ
ポキシ樹脂、ポリイミド樹脂、変性トリアジン樹脂等の
いずれでも使用できる。Sumitomo Bakelite CRM-10335X10CRM
-10502X 10-' Shinto Paint p-5or, o4 3083 4 X 10
Bundle Reviso/I/KO01083X10-'Amicon C-805-11XIO'
60. -0 50J
I60-L
1011 59-ClXl0 Also,
As the plastic substrate used in the present invention, any of galanu epoxy resin, paper-phenol resin, paper-epoxy resin, polyimide resin, modified triazine resin, etc. can be used.
本発明において、プラグインパッケージの製造方法とし
ては入出力ピンの接着以外は公知の手段によって行なう
ことができる。例えば、所望のガラスチック基板に対し
、スルーホールおよびザグリ加工を施した後、メッキ後
、エツチングして導体パターンを形成し、熱硬化型ある
いは感光性ＵＶフィルムにてレジストを形成する。その
後、入出力ピンをスルーホールに接続固定する。In the present invention, the plug-in package can be manufactured by any known means except for bonding the input/output pins. For example, a desired glass substrate is processed with through holes and counterbore, then plated and etched to form a conductor pattern, and a resist is formed using a thermosetting or photosensitive UV film. Then, connect and fix the input/output pins to the through holes.
本発明によれば入出力ピンの接続固定はまず前述したよ
うな熱硬化性接着剤によってスルーホールおよび／また
はランド部に装着する。この時接着剤は、スクリーン印
刷によってスルーホールまたはランド部にスクリーン印
刷等の手段によって塗布するか、およびまたは入出力ピ
ンの先端部に塗布して、スルーホールに嵌入させて装着
すれば良い。According to the present invention, the input/output pins are connected and fixed by first attaching them to the through holes and/or land portions using a thermosetting adhesive as described above. At this time, the adhesive may be applied to the through hole or land portion by screen printing or the like, or it may be applied to the tip of the input/output pin, and the adhesive may be fitted into the through hole.
入出力ピンが装着された基板は、次にオーブン等の加熱
手段によって加熱され、入出力ピンはスルーホールに固
定される。この時、接着剤の硬化最低温度よりも高い温
度に設定すれば接着剤の硬化に伴う入出力ピンの固定は
可能ではあるが前述したような理由によって硬化時の温
度は２００℃以下、特に１８０℃以下であることが望ま
しい。The board on which the input/output pins are attached is then heated by heating means such as an oven, and the input/output pins are fixed in the through holes. At this time, if the temperature is set higher than the lowest temperature for curing the adhesive, it is possible to fix the input/output pins as the adhesive hardens, but for the reasons mentioned above, the temperature at the time of curing is below 200°C, especially at 180°C. It is desirable that the temperature is below ℃.
本発明によれば入出力ピンの固定工程終了後、基板を最
終的にフレオン等で洗浄し、脱脂することが望ましい。According to the present invention, after the step of fixing the input/output pins is completed, it is desirable to finally clean the board with Freon or the like and degrease it.
本発明によれば、プラグインパッケージとしては上述し
た形態のものに限られるものでなく、入出力ピンをホー
ル状に形成された固定部に対し、入出力ピンを固定する
形態のものであれば、いずれでも適用されるものであり
、製造方法においても上述の方法に限られるものでなく
、例えば入出力ピンの接続の際の接着剤の塗布において
も、場合によっては全面塗布、あるいはホール中に接着
剤を注入する等あらゆる方法を採用し得るものである。According to the present invention, the plug-in package is not limited to the above-mentioned form, but can be any type in which the input/output pin is fixed to the fixing part formed in the shape of a hole. The manufacturing method is not limited to the above-mentioned method, for example, when applying adhesive when connecting input/output pins, depending on the case, it may be applied to the entire surface or in the hole. Any method can be used, such as injecting an adhesive.
以下、本発明を次の例で説明する。The invention will now be explained with the following examples.
実施例
ガラス繊維−エポキシのプラスナック製基板（３３，４
１ＲＭ角）に、導体パターンを形成し、さらに導体パタ
ーン上にレジストを設けた基板のスルホール周辺に設け
られたランド部にスクリーン印刷によって第１表の接着
剤を塗布し、コパール製入出力ピンを第１表の硬化条件
によって接続固定した。Example glass fiber-epoxy plastic nac substrate (33,4
A conductor pattern is formed on a 1RM square), and the adhesive shown in Table 1 is applied by screen printing to the lands provided around the through-holes of the board with a resist provided on the conductor pattern, and copal input/output pins are attached. The connection was fixed according to the curing conditions shown in Table 1.
得られた基板に対し、リード抵抗、およびピン引抜き強
度を調べた。なおリード抵抗は、固定ピン先端から導体
パターンの半導体素子と接続される部位即ち、ポンディ
ングフィンガーまでの抵抗であり、１００ （＊Ω）以
下をＯ，ｔｏｏ−１０００（屑Ω）Ｑ１００Ｏ（ｍ Ｑ
）以上をＸ印として示した。The resulting board was examined for lead resistance and pin pullout strength. The lead resistance is the resistance from the tip of the fixed pin to the part of the conductive pattern connected to the semiconductor element, that is, the bonding finger.
) The above is shown as an X mark.
測定結果は、第１表に示した。The measurement results are shown in Table 1.
第１表から明らかなように、接着剤の抵抗値が高いもの
はリード抵抗が１０００ ｍΩを超えるものであり、パ
ッケージとしての性能に問題があった。As is clear from Table 1, adhesives with high resistance values had lead resistances exceeding 1000 mΩ, and had problems in performance as packages.
また、接着剤の硬化条件において温度が２００℃を超え
る場合、基板の表面のレジスト層が変色劣化した。これ
らの比較例に対し、本発明のパッケージは、￥−ド抵抗
も低く、ピンの引抜き強度、外観いずれも問題なく品質
的に優れたものであった。Further, when the temperature exceeds 200° C. under the adhesive curing conditions, the resist layer on the surface of the substrate deteriorated due to discoloration. In contrast to these comparative examples, the package of the present invention had low lead resistance, no problems in pin pull-out strength, and appearance, and was excellent in quality.
（発明の効果）
本発明によればプラグインパッケージの入出力ピンの固
定を特定の熱硬化性接着剤を用いて行なうことにより、
優れた固定強度が得られるとともに製造工稈上ハンダ固
定のよりなフフックス洗浄工程を省略できる他、接着剤
の再溶融が起きないことにより、パッケージをマザーボ
ードへ装着する際にも入出力ピンの揺れ、抜は等が発生
しないため、作業性に優れ、しかも高信頼性で安価なデ
フゲインパッケージが得られる。(Effects of the Invention) According to the present invention, by fixing the input/output pins of the plug-in package using a specific thermosetting adhesive,
Not only does it provide excellent fixing strength, it also eliminates the additional cleaning process required for soldering on the manufacturing process, and since the adhesive does not re-melt, the input/output pins do not shake when the package is attached to the motherboard. , removal, etc. do not occur, so a differential gain package with excellent workability, high reliability, and low cost can be obtained.
【図面の簡単な説明】
第１図は従来から知られるデフゲインパッケージの一例
を示すｔＪｆｒｍ図である。
ｌ・・・デフゲインパッケージ、２・・・ホール状支持
部、３・・・プラスチック基板、４・−導体パターン、
７・・・入出力ピンBRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a tJfrm diagram showing an example of a conventionally known differential gain package. l... Differential gain package, 2... Hole-shaped support part, 3... Plastic board, 4... Conductor pattern,
7...Input/output pin
Claims (2)
チック基板と、該基板上に設けられ該ホール状固定部と
電気的に接続された導体パターンと、該ホール状固定部
に嵌入され、該導体パターンと電気的に接続された入出
力ピンとを具備したプラグインパッケージにおいて、 前記入出力ピンが２００℃以下で硬化可能な熱硬化型導
電性接着剤によつて前記ホール状固定部に接着固定され
たことを特徴とするプラグインパツケージ。(1) A plastic substrate having a plurality of conductive hole-shaped fixing parts, a conductor pattern provided on the substrate and electrically connected to the hole-shaped fixing parts, and a conductive pattern fitted into the hole-shaped fixing parts. , in a plug-in package equipped with an input/output pin electrically connected to the conductor pattern, the input/output pin is attached to the hole-shaped fixing part with a thermosetting conductive adhesive that can be cured at 200° C. or less. A plug-in package characterized by being fixed with adhesive.
支持部と電気的に接続された導体パターンを少なくとも
具備したプラスチック製基板に対し、入出力ピンを２０
０℃以下で硬化可能な熱硬化型導電性接着剤によつて前
記ホール状支持部に装着する工程と、 該基板を２００℃以下の範囲で加熱して前記接着剤を硬
化させ、前記入出力ピンを前記ホール状支持部に固定す
る工程と、 を具備したプラグインパッケージの製造方法。(2) Connect 20 input/output pins to a plastic substrate that includes at least a plurality of conductive hole-shaped supports and a conductor pattern electrically connected to the hole-shaped supports.
Attaching the board to the hole-shaped support using a thermosetting conductive adhesive that can be cured at temperatures below 0°C; heating the substrate at a temperature below 200°C to cure the adhesive; A method of manufacturing a plug-in package, comprising: fixing a pin to the hole-shaped support.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60192723A JPS6252953A (en) | 1985-08-31 | 1985-08-31 | Plug-in package and manufacture of the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60192723A JPS6252953A (en) | 1985-08-31 | 1985-08-31 | Plug-in package and manufacture of the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6252953A true JPS6252953A (en) | 1987-03-07 |
Family
ID=16295990
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60192723A Pending JPS6252953A (en) | 1985-08-31 | 1985-08-31 | Plug-in package and manufacture of the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6252953A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5006922A (en) * | 1990-02-14 | 1991-04-09 | Motorola, Inc. | Packaged semiconductor device having a low cost ceramic PGA package |
| JPH03184880A (en) * | 1989-12-14 | 1991-08-12 | Matsushita Electric Ind Co Ltd | Electrostatic recording head and production thereof |
| US6340606B1 (en) | 1998-03-27 | 2002-01-22 | Seiko Epson Corporation | Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument |
| US7217999B1 (en) | 1999-10-05 | 2007-05-15 | Nec Electronics Corporation | Multilayer interconnection board, semiconductor device having the same, and method of forming the same as well as method of mounting the semiconductor chip on the interconnection board |
-
1985
- 1985-08-31 JP JP60192723A patent/JPS6252953A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03184880A (en) * | 1989-12-14 | 1991-08-12 | Matsushita Electric Ind Co Ltd | Electrostatic recording head and production thereof |
| US5006922A (en) * | 1990-02-14 | 1991-04-09 | Motorola, Inc. | Packaged semiconductor device having a low cost ceramic PGA package |
| US6340606B1 (en) | 1998-03-27 | 2002-01-22 | Seiko Epson Corporation | Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument |
| US6815815B2 (en) | 1998-03-27 | 2004-11-09 | Seiko Epson Corporation | Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument |
| US7094629B2 (en) | 1998-03-27 | 2006-08-22 | Seiko Epson Corporation | Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument |
| US7518239B2 (en) | 1998-03-27 | 2009-04-14 | Seiko Epson Corporation | Semiconductor device with substrate having penetrating hole having a protrusion |
| US7871858B2 (en) | 1998-03-27 | 2011-01-18 | Seiko Epson Corporation | Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument |
| US8310057B2 (en) | 1998-03-27 | 2012-11-13 | Seiko Epson Corporation | Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument |
| US7217999B1 (en) | 1999-10-05 | 2007-05-15 | Nec Electronics Corporation | Multilayer interconnection board, semiconductor device having the same, and method of forming the same as well as method of mounting the semiconductor chip on the interconnection board |
| US8008130B2 (en) | 1999-10-05 | 2011-08-30 | Renesas Electronics Corporation | Multilayer interconnection board, semiconductor device having the same, and method of forming the same as well as method of mounting the semicondutor chip on the interconnection board |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6297564B1 (en) | Electronic devices employing adhesive interconnections including plated particles | |
| JP2004363434A (en) | Electronic circuit device and its manufacturing method | |
| JPH0418787A (en) | Printed wiring board connection device | |
| Rorgren et al. | Reliability assessment of isotropically conductive adhesive joints in surface mount applications | |
| JPS6252953A (en) | Plug-in package and manufacture of the same | |
| JP4677968B2 (en) | Solder paste and joined parts | |
| US5814879A (en) | Tape carrier device having an adhesive resin overcoat and a polyimide resin-based overcoat | |
| JPS617692A (en) | Method of securing conductor pin and printed circuit board secured with conductor pin | |
| JP3346216B2 (en) | Printed wiring board | |
| JP3842981B2 (en) | Substrate manufacturing method, electronic component manufacturing method, and electronic component mounting method | |
| JPH07252460A (en) | adhesive | |
| JPH08191128A (en) | Electronic equipment | |
| JPH06112640A (en) | Circuit board | |
| JPH03798B2 (en) | ||
| WO2022220030A1 (en) | Electronic component mounting method and circuit mounting board | |
| JP2676107B2 (en) | Substrate for mounting electronic components | |
| JPS62130595A (en) | Manufacture of electric circuit device | |
| JPH02260592A (en) | Circuit board | |
| JP2000114424A (en) | Semiconductor element mounting board | |
| JPS60120588A (en) | Printed circuit board | |
| JPH0751807Y2 (en) | Flexible circuit board | |
| JPH0563343A (en) | Electronic parts packaging method | |
| JPH02105595A (en) | Hybrid integrated circuit | |
| JPH0344945A (en) | Mounting of semiconductor device | |
| JPS6276542A (en) | Plug-in package and its manufacturing method |