JPS6250841B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a processing device for detecting abnormal conditions such as battery voltage drop and parity occurrence in a sequence program memory due to battery backup of a sequence controller, and outputting the detection results to the outside. Generally, in a processing device having memory,
Memory defects are similar to serious failures, and it is necessary to actively detect them and output them to the outside.

Conventionally, in sequence controllers,
Detection of abnormal conditions such as battery voltage drop and parity occurrence in battery backup semiconductor read/write memory (IC-RAM) is carried out by self-diagnosis, which is equipped with hardware that performs processing for each and outputs faults in the sequence controller to the outside. It was used as output.

This conventional device requires hardware to handle memory defects and output them to the outside, resulting in an increase in hardware, and especially since these processes are performed by a central processing unit (CPU). However, it has the disadvantage that special measures must be taken against external noise from the self-diagnosis output.

The present invention aims to eliminate this drawback by minimizing the hardware required to output self-diagnosis results to the outside.
It also has high resistance to noise and facilitates interface with external equipment connected to the self-diagnosis output.

Hereinafter, details of the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a sequence controller showing one embodiment of the present invention.

In the figure, 1 is a microprocessor that performs processing such as sequence calculations and external input/output control, and 2 is a memory that stores the processing program of the microprocessor 1, such as semiconductor read-on memory (ROM),
3 is a working memory used for processing by the microprocessor 1, such as a semiconductor read/write memory (RAM); 4 is a sequence program memory that stores processing programs for sequence calculations; Memory, 6, a battery voltage drop detection circuit that detects a voltage drop in the battery 5 and outputs the detection result to a data bus 7, which will be described later; 8, a battery voltage drop detection circuit that detects the occurrence of parity in the sequence program memory 4, and outputs the detection result to the data bus 7; 9 is an auxiliary relay memory used only for calculations without directly outputting calculation results to the outside in sequence calculations; 10 is an external input input via input interface 11; Turn on the device
12 is an input memory that stores the off state; 12 is an output memory that stores the state when outputting the results of sequence operations to the outside; 13 is the output memory 12
This is an output interface that interfaces with the external output device. Note that the data bus 7
has the function of being an information path for each block.

Next, the gist of the present invention will be explained with reference to FIG. In FIG. 1, a voltage drop in a battery 5 is detected by a battery voltage drop detection circuit 6. In FIG. Moreover, the occurrence of parity, which is an erroneous reading of the sequence program memory 4, is detected by the memory parity detection circuit 8. These detection results are output to the data bus 7 in response to a command G from the microprocessor 1 at a break in a series of sequence operations, for example, during processing of an instruction to declare the end of a program. The detection results outputted to the data bus 7, that is, the presence or absence of battery voltage drop and parity occurrence are taken into the microprocessor 1, processed, and stored in the auxiliary relay memory 9. At this time, for example, if the symbol of the auxiliary relay is M, battery voltage drop is numbered M62, parity occurrence is numbered M63, and so on, and stored in a specific auxiliary relay number for each cause of occurrence.

Here, the auxiliary relay does not directly output its contents to the outside as described above, but is used for sequence calculations by the sequence program, and the calculation results are sent to the output memory 12 and the output interface 1.
3 to an external output device. In addition, the auxiliary relay is a temporary memory, an intermediate relay,
They are also called dummy, internal register, etc., and they are all the same thing.

Next, the detection results stored in the auxiliary relay memory 9 are outputted to the outside as the self-diagnosis results of the memory through sequence calculation processing as shown in FIG. In FIG. 2, 20 shows the contents of the sequence program in a relay circuit format, 21 the contents M62 of the auxiliary relay memory 8 in which the detection result of the battery voltage drop is stored, and 22 the above contents M62 21
External output Am that outputs the contents of (here,
The external output is denoted by A), 23 is the content M63 of the auxiliary relay memory 8 in which the detection result of the parity occurrence is stored, and 24 is the external output An. Here, Am22 and An24 are output memory 1 in Figure 1.
2 and is output via the output interface 13. 30 shows this output circuit to the outside, 31 is a contact Am of the external output Am22 of the output interface 13, and this contact Am31
For example, an indicator light 32 is connected to indicate a drop in battery voltage, and output is made in the form of a lamp display. In addition, parity generation is the external output of output interface 13.
The signal is output by, for example, a buzzer 34 connected to a contact An33 of An24.

As described above, by storing the memory self-diagnosis result in a specific number of the auxiliary relay, the user of the sequence controller can output it to any external output A using the sequence program and further drive the external output device. be able to.

It is important to output via this external output A. Firstly, the external output A is one point of the output interface 13, and the output interface 13 has sufficient noise countermeasures for external output equipment. This improves the noise resistance of the self-diagnosis output. When outputting via dedicated hardware as in the past, the noise resistance was poor due to processing by the CPU, which is sensitive to noise. However, output interfaces provided for external output devices 13 is used, which is advantageous in terms of noise resistance.

Second, in a sequence controller, the output interface 13 is usually provided with interfaces for various voltage and current ratings. It has the advantage of being selectable and easy to interface. In the conventional method, the output format was built into the sequence controller, and there was a drawback that there was little room for selection, but this can be overcome by the present invention.

Thirdly, there is no need for a dedicated output interface for self-diagnosis results as in the conventional method, which has the advantage of saving hardware and making it economical in terms of cost.

As described above, according to the present invention, the drawbacks of the conventional technology can be reliably overcome, and its advantages are great.

Next, another embodiment for realizing the gist of the present invention will be described with reference to FIG.

In FIG. 3, the same reference numerals as in FIG. 1 indicate the same or corresponding parts, and only related parts are shown.

In the embodiment shown in FIG.
and is processed by the microprocessor 1 via the data bus 7. However, in the embodiment shown in FIG. 3, when the self-diagnosis result is significant, an interrupt is made to the microprocessor 1 for processing, and the interrupt signals are indicated by X and Y. When the interrupt signals X and Y become significant, an interrupt is generated in the microprocessor, which is accepted and processed with priority, and the result is stored in the auxiliary relay memory 8 as in the first example, resulting in the format shown in Figure 2. is output to the outside.

According to this device, especially when parity occurs, an interrupt is immediately processed, sequence calculations can be stopped immediately, and the time delay before outputting to the outside can be minimized. In the embodiment shown in FIG. 1, even if parity occurs, the microprocessor 1
It cannot be detected until the command G is issued from , and there is a possibility that an incorrect calculation will be performed, but this has been improved in the example shown in FIG.

As can be understood from the above explanation, the gist of the present invention is to output the memory self-diagnosis results to the outside via an auxiliary relay, and as mentioned above, it has great advantages over conventional devices, and has been improved and improved. has been done.

According to the gist of the present invention, not only the self-diagnosis results for the memory but also the operating status of the sequence controller, abnormalities in the internal power supply voltage, abnormalities in various connected peripheral devices, poor connection of connection cables between units, etc. It can be seen that the self-diagnosis results of the memory can also be outputted to the outside via the auxiliary relay, and the same advantages as the output of the self-diagnosis results of the memory can be obtained, and the application development is extremely wide, and the implementation effect of the present invention is great.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a sequence controller showing one embodiment of the present invention, Fig. 2 is a circuit diagram showing an external output method of self-diagnosis results, and Fig. 3 is a block diagram showing another embodiment of the present invention. be. In the figure, 1 is a microprocessor, 4 is a sequence program memory, 5 is a battery, 6 is a battery voltage drop detection circuit, 7 is a memory parity detection circuit, and 8
20 is a sequence program portion, and 30 is an external connection portion.

Claims (1)

[Scope of Claims] 1. A microprocessor, a microprocessor processing memory that stores a processing program for the microprocessor, a sequence program memory based on battery backup, and a battery voltage drop detection circuit that detects a voltage drop in the battery. and a sequence controller comprising a memory parity occurrence detection circuit for detecting occurrence of parity in the sequence program memory, and an auxiliary relay memory,
Detecting a voltage drop in the battery and detecting an abnormality such as occurrence of parity in the sequence program memory, and processing these detection signals by the microprocessor and a processing program stored in the microprocessor processing memory. The state processing of the sequence controller is characterized in that the detection result is stored in a specific number of the auxiliary relay memory, and the detection result stored in the auxiliary relay memory is outputted to the outside by the sequence program. Device. 2. When an abnormality such as battery voltage drop or memory parity is detected, this detection signal interrupts the microprocessor, and the microprocessor interrupts the detection to a specific number in the auxiliary relay memory. 2. A state processing device for a sequence controller according to claim 1, wherein a result is stored. 3. A state processing device for a sequence controller according to claim 1 or 2, wherein the self-diagnosis result of the sequence controller is stored in a specific number of an auxiliary relay memory.