JPS6051136B2 - Data error detection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data error detection method for detecting data errors occurring within a data processing device.

Generally, it is desirable that the validity of data to be processed by a data processing device be checked before the data is actually processed.

This is because such a check eliminates errors such as data processing based on erroneous data and improves the reliability of the apparatus. In conventional data processing devices, when detecting data errors as described above, the data is read once, and then a program for detecting errors in the data is activated to perform a check.

However, since the data error detection method described above uses a program check, there is a problem in that the error detection process takes time, and it cannot be put to practical use in data processing equipment for process control. Ta.

Therefore, the present invention is intended to improve the above-mentioned problems of the prior art, and its purpose is to shorten the time required to detect errors in input data, thereby increasing the scope of use, such as for process control. The object of the present invention is to provide a data error detection method that can be expanded to In order to achieve the above object, the present invention is characterized in that the same data processing device that reads input data, performs predetermined data processing on it, and then outputs it is connected to at least two or more of the same external data sending devices. The data processing devices are connected in parallel, and the data output from the data processing devices are compared with reference data set in advance to determine abnormality in these data to determine whether or not there is an abnormality. This data error detection method includes an abnormality detection circuit that outputs an abnormality detection signal to the data processing device that outputs the data. Embodiments of the invention will be described below with reference to the drawings.

The figure shows the internal configuration of a data error detection system according to an embodiment of the present invention. In the figure, reference numbers 1,
2 is a data processing device, these data processing devices 1 and 2 are respectively central processing unit 4, bus 4a1 process input section 5-1
...5-n1 process output section 6, process input section 7,
It is composed of a parallel-to-serial conversion circuit 8, a memory 9, and a modulator 10.

The process input sections 5-1...5-n are connected to a process output section 6, a process input section 7, a parallel-to-serial conversion circuit 8, a memory 9, They are respectively connected to the central processing unit 4. The process input section 5-1...5-n receives n pieces of data D output from the process processing device 3.・・・・・・
- Dn is taken in separately and outputted to the various devices mentioned above via the bus 4a. The central processing unit 4 is connected to the bus 4a.
It takes in information given from various devices including process input parts 5-1...5-n through
After performing predetermined arithmetic processing based on the information, the information is output to the various devices via the bus 4a. The central processing unit 4
When the abnormality detection circuit 11 receives judgment information indicating that there is a data abnormality as described later through the bus 4a, the data applied to the memory 9 through the process input sections 5-1...5-n D. ... Read out the corresponding data from Dn and discard it. The memory 9 contains control programs and the like, and also stores necessary data. As the data stored in the memory 9, for example, n pieces of data D respectively provided from the process processing device 3 via the process input units 5-1, . . . , 5-n.・・・・・・
Dn and each process input section 5-1...5-n to determine whether there is an abnormality in the process input section 5-1...5-n itself. There is standard data for abnormality determination that is set as follows. The input side of the process output section 6 is connected to the process input section 5- via the bus 4a.
1... 5-n, and the output side thereof is connected to the input side of the abnormality detection circuit 11. The process output section 6 includes a process input section 5-1.
...Data D sequentially output from 5-n.・・・
....Dn is taken in successively and this is sent to the abnormality detection circuit 1.
Output to 1. The process input section 7 has its input side connected to the output side of the abnormality detection circuit 11, and its output side connected to the aforementioned bus 4a. The process input section 7
is configured to receive a signal output from the abnormality detection circuit 11 and output it to the central processing unit 4 via the bus 4a. The parallel-to-serial conversion circuit 8 has its input side connected to the bus 4a and its output side connected to the input side of the modulator 10, and converts the signal data given via the bus 4a into parallel/serial data and outputs the result. It is a circuit. Modulator 1
0 receives the serially converted signal data, modulates it, and outputs it.

As shown in the figure, the switch 12 is disposed between the data processing devices 1, 2 and the line connection device 13, and is configured to connect each of the data processing devices 1, 2 and the line connection device 13 separately. It's summery. The switch 12 normally connects the data processing device 1 and the line connection device 13 as shown, and is configured to send only the data output from the data processing device 1 to the line connection device 13. . The line connection device 13 is connected via a line 13a to a line connection device (not shown) of a data processing device (not shown) that is different from the one described above. The line connection device 13 switches the switch 12 based on a predetermined signal output from the data processing device 1. As described above, the abnormality detection circuit 11 has its input side connected to the process output section 6 provided individually in the data processing apparatuses 1 and 2, and its output side connected to the process output section 6 provided individually in the data processing apparatuses 1 and 2. It is connected to the process input section provided in the

The abnormality detection circuit 11 includes, for example, a memory circuit (not shown) and a determination circuit (not shown). The storage circuit stores n pieces of data D output from the process processing device 3. . . . Standard data for checking whether or not Dn is normal is set and stored for each of the above-mentioned individual data. The determination circuit receives the data D sequentially inputted from each process output section 6 at predetermined timings.・・・・・・Compare Dn and the reference data individually to determine whether there is an abnormality in the input data. Then, the judgment result is sent to the process input section 7 and the bus 4.
It is configured to sequentially output the data to the central processing unit 4 via a. The operation of the data error detection system configured as described above will be explained below.

Normally, each central processing unit J4 has a process input section 5-1...
...Data D input via the 5-n1 bus 4a
. After reading -Dn and performing necessary data processing, it is sent to the line 13a via the parallel-to-serial conversion circuit 8, modulator 10, switch 12, and line connection device 13. As described above, the switch 12 normally closes the data processing device 1 side as shown in the figure, so that only the data output from the processing device 1 is sent out. In parallel with such an operation, the abnormality detection circuit 11 detects the process input units 5-1, . . . , 5-n of each data processing device 1, 2.
1 bus 4a1 data D given via process output unit 6.・・・・・・Dn is sequentially fetched according to a predetermined timing, the fetched input data and reference data are individually compared to determine whether or not there is an abnormality in the input data, and the determination result is sent to the central processing unit. Output to 4. As a result of the above judgment,
For example, data DO input from the data processing device 1...
...When a signal indicating that there is an abnormality in one of Dn is output from the abnormality detection circuit 11, the central processing unit 4 on the data processing device 1 side retrieves the corresponding data from the memory 9 and the individual processes. Input section 5-1...5-n
The data is read out and compared with the reference data for abnormality determination set for each case, and the input data in which the abnormality is found is discarded. Further, when it is recognized that the cause of the abnormality in the input data is due to an abnormality in the process input section corresponding to the data as a result of the comparison, the circuit is A switching command signal is output to the connection device 13, and the switch 12 is switched from the data processing device 1 side to the data processing device 2 side. Thereafter, data will be sent from the data processing device 2 to the line 13a. In the embodiment according to the present invention described above, for convenience of explanation, two data processing devices having the same structure are connected in parallel to the process processing device, but three or more data processing devices are connected to the process processing device in parallel. There is no problem even if they are connected in parallel to each other, and the same effect as in the above embodiment can be achieved. As explained above, according to the present invention, the same data processing device can be used for at least two
We decided to provide an abnormality detection circuit that is connected in parallel to the same external data sending device and outputs an abnormality detection signal to the data processing device that outputs the data determined to be abnormal. It is possible to provide a data error detection method that can shorten the time required for data error detection processing, and thereby expand the scope of use.

[Brief explanation of the drawing]

The figure is a block diagram showing the internal configuration of a data error detection system according to an embodiment of the present invention. 1...Data processing device, 2...Data processing device, 4...Central processing unit, 5-1...
... 5-n... Process input section, 6... Process output section, 7... Process input section, 11...
...Anomaly detection circuit.

Claims (1)

[Claims] 1 At least two or more identical data processing devices that read input data, perform predetermined data processing on it, and then output the data are connected in parallel to the same external data transmission device, and each of the data processing devices The output data is compared with standard data set in advance to determine abnormalities in these data, the presence or absence of an abnormality is determined, and an abnormality is detected in the data processing device that outputs the data determined to be abnormal. A data error detection method characterized by providing an abnormality detection circuit that outputs a signal.