JPS6248062A - Memory cell - Google Patents
Memory cellInfo
- Publication number
- JPS6248062A JPS6248062A JP60188818A JP18881885A JPS6248062A JP S6248062 A JPS6248062 A JP S6248062A JP 60188818 A JP60188818 A JP 60188818A JP 18881885 A JP18881885 A JP 18881885A JP S6248062 A JPS6248062 A JP S6248062A
- Authority
- JP
- Japan
- Prior art keywords
- film
- capacitor
- memory cell
- electrode
- electrode film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 53
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 19
- 230000002093 peripheral effect Effects 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 15
- 229910052814 silicon oxide Inorganic materials 0.000 description 10
- 239000011229 interlayer Substances 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910052681 coesite Inorganic materials 0.000 description 4
- 229910052906 cristobalite Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000001590 oxidative effect Effects 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
Landscapes
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】 本発明メモリセルを以下の項目に従って説明する。[Detailed description of the invention] The memory cell of the present invention will be explained according to the following items.
Ａ、産業上の利用分野
Ｂ１発明の概要
Ｃ２従来技術［第３図］
Ｂ１発明が解決しようとする問題点
Ｅ８問題点を解決するための手段
Ｆ、実施例［第１図、第２図］
ａ、製造方法［第１図］
ｂ、構成［第１図、第２図］
Ｃ６作用
Ｇ１発明の効果
（Ａ、産業上の利用分野）
本発明は新規なメモリセル、特に、１つのコンデンサと
１つのトランジスタとからなるメモリセルに関するもの
である。A. Industrial field of application B1 Overview of the invention C2 Prior art [Figure 3] B1 Problems to be solved by the invention E8 Means for solving the problems F. Examples [Figures 1 and 2] a. Manufacturing method [Fig. 1] b. Structure [Fig. 1, Fig. 2] C6 Effect G1 Effect of the invention (A. Field of industrial application) The present invention provides a novel memory cell, particularly a single capacitor and The present invention relates to a memory cell consisting of one transistor.
（Ｂ、発明の概要）
本発明は、１つのコンデンサと１つのトランジスタとか
らなるメモリセルにおいて、占有面積を大きくすること
なくコンデンサの静電容量を大きくするため、コンデン
サを略平面上に延在する部分と、その部分の周縁から垂
直に延びるように形成した部分とにより構成するように
したものであり、略平面」二に延在するコンデンサ部分
の周縁に垂直に延びるコンデンサ部分を付加したのでセ
ルの占有面積を増やすことなくコンデンサの静電容量を
大きくすることができる。(B. Summary of the Invention) In a memory cell consisting of one capacitor and one transistor, the present invention extends the capacitor substantially on a plane in order to increase the capacitance of the capacitor without increasing the occupied area. The capacitor part is formed by adding a capacitor part that extends perpendicularly to the periphery of the capacitor part that extends substantially in a plane. The capacitance of the capacitor can be increased without increasing the area occupied by the cell.
（Ｃ，従来技術）［第３図〕
ダイナミックＲＡＭにおいてメモリセルの占有面積を小
さくし、記憶容量を大きくすることが要請されている。(C, Prior Art) [Figure 3] In a dynamic RAM, it is required to reduce the area occupied by the memory cell and increase the storage capacity.
そして、メモリセルの占有面積を小さくするためにはコ
ンデンサを小さくする必要があるが、その場合静電容量
が情報の蓄積、即ち電荷の蓄積に必要な大きさを有して
いなければならない、即ち、メモリセルのコンデンサは
占有面積を小さくしつつ静電容量を大きくする必要性が
ある。In order to reduce the area occupied by a memory cell, it is necessary to make the capacitor smaller, but in this case, the capacitance must have a size necessary for storing information, that is, storing charge. , it is necessary to increase the capacitance of a memory cell capacitor while reducing its occupied area.
ところで、占有面積が小さくても比較的大きな静電容量
が得られるコンデンサとして半導体基板に形成すること
ができるものにはトレンチキャパシターとスタックドキ
ャパシターがある。トレンチキャパシターは半導体基板
表面にトレンチを形成し、該トレンチ表面に誘電体を成
す酸化膜を形成し、更にトレンチ内に一方の電極を成す
導電体を形成してなるものであり、半導体基板自身がコ
ンデンサの他方の電極を成す、しかしながら、コンデン
サの形成に良好なトレンチはＲＩＥ技術との関係を形成
が難しい。By the way, trench capacitors and stacked capacitors are capacitors that can be formed on semiconductor substrates and can provide a relatively large capacitance even if they occupy a small area. Trench capacitors are made by forming a trench on the surface of a semiconductor substrate, forming an oxide film as a dielectric on the surface of the trench, and further forming a conductor as one electrode within the trench. However, the trench forming the other electrode of the capacitor, which is good for forming the capacitor, is difficult to form in relation to the RIE technique.
従って、スタックドキャパシターがＤ−ＲＡＭの情報蓄
積用のコンデンサとして用いられている。第３図はスタ
ックドキャパシターをコンデンサとして用いたメモリセ
ルの従来例の−を示すものである。Therefore, stacked capacitors are used as capacitors for storing information in D-RAMs. FIG. 3 shows a conventional example of a memory cell using a stacked capacitor as a capacitor.
同図において、＆はシリコン単結晶からなる半導体基板
、ｂは選択酸化により形成されたフィールド酸化膜、Ｃ
はゲート酸化膜、ｄはゲート電極、ｄ′は別のメモリセ
ルのゲート電極、ｅはドレイン、ｆはソース、ｇは層間
絶縁用酸化膜、ｈは多結晶シリコンからなる電極膜で、
層間絶縁用酸化膜ｇのコンタクトホールｉを通してソー
スｆに接続されている。ｊは電極膜りの表面に形成され
た誘電膜で、多結晶シリコンからなる電極膜りの表面部
を加熱酸化することにより形成される。In the figure, & is a semiconductor substrate made of silicon single crystal, b is a field oxide film formed by selective oxidation, and C is a semiconductor substrate made of silicon single crystal.
is a gate oxide film, d is a gate electrode, d' is a gate electrode of another memory cell, e is a drain, f is a source, g is an oxide film for interlayer insulation, h is an electrode film made of polycrystalline silicon,
It is connected to the source f through a contact hole i in an oxide film g for interlayer insulation. j is a dielectric film formed on the surface of the electrode film, and is formed by heating and oxidizing the surface portion of the electrode film made of polycrystalline silicon.
ｋは多結晶シリコンからなる電極膜にで、それの誘電膜
ｊを介して電極膜りと対向する部分が情報蓄積用のコン
デンサとなる。ｔは層間絶縁用の酸化膜、ｍは該酸化膜
ｔに形成されたコンタクトホールｎを通してドレインｅ
に接続されたアルミニウム電極であり、該電極ｍがＲＡ
Ｍのビットラインを成す。K is an electrode film made of polycrystalline silicon, and the portion thereof facing the electrode film with a dielectric film j in between serves as a capacitor for storing information. t is an oxide film for interlayer insulation, m is a drain e through a contact hole n formed in the oxide film t.
is an aluminum electrode connected to RA, and the electrode m is connected to RA
M bit lines are formed.
尚、ゲート電極ｄ（ｄ′）がＲＡＭのワードラインを成
し、そして、電極膜にのコンデンサを成す部分と反対側
の部分がアースラインを成す。Note that the gate electrode d (d') forms a word line of the RAM, and the part of the electrode film on the opposite side to the part forming the capacitor forms an earth line.
（Ｄ、発明が解決しようとする問題点）第３図に示すよ
うなメモリセルにおいては、コンデンサが多少の凹凸は
あるも略平面上に通商するように形成された電極膜り、
誘電膜ｊ及び電極ｌりｋからなる。(D. Problem to be Solved by the Invention) In a memory cell as shown in FIG.
It consists of a dielectric film j and an electrode lk.
そして、多結晶シリコンからなる電極膜りの表面を加熱
酸化することにより形成された誘電膜ｊを成すシリコン
酸化膜は単結晶シリコンを加熱酸化することにより形成
されたシリコン酸化膜に比較して電界強度が弱く３分の
１程度である。従って、充分な電界強度を得るにはその
誘電膜ｊを成すシリコン酸化膜の膜厚を相当に厚くすな
ければならない、そして、その膜厚を厚くすると当然の
ことながらコンデンサの単位占有面積当りの静電容量が
小さくなり、十分な大きさの静電容量を得るにはコンデ
ンサの占有面積を大きくせざるを得ない。The silicon oxide film forming the dielectric film j, which is formed by heating and oxidizing the surface of the electrode film made of polycrystalline silicon, has a higher electric field resistance than the silicon oxide film formed by heating and oxidizing single crystal silicon. The strength is weak, about one third. Therefore, in order to obtain sufficient electric field strength, the thickness of the silicon oxide film that forms the dielectric film j must be made considerably thicker, and as the film thickness becomes thicker, the amount per unit area occupied by the capacitor naturally increases. The capacitance becomes smaller, and in order to obtain a sufficiently large capacitance, the area occupied by the capacitor must be increased.
そこで、誘電膜として多結晶シリコンを加熱酸化するこ
とにより形成したシリコン酸化膜に代えて別の絶縁膜、
例えば５００人のタンタルオキサイド膜（熱酸化膜１０
０人の絶縁膜）を設けたりする必要がある。Therefore, instead of the silicon oxide film formed by heating and oxidizing polycrystalline silicon as a dielectric film, another insulating film,
For example, 500 tantalum oxide films (thermal oxide films 10
It is necessary to provide an insulating film for 0 people.
本発明は上記問題点を解決すべく為されたもので、メモ
リセルの占有面積を小さくしつつコンデンサの静電容量
を大きくすることを目的とするものである。The present invention has been made to solve the above-mentioned problems, and its object is to increase the capacitance of a capacitor while reducing the area occupied by a memory cell.
（Ｅ、問題点を解決するための手段）
本発明メモリセルは、上記問題点を解決するため、平面
上に延在するコンデンサ部分の周縁に垂直に延びるコン
デンサを付加してなることを特徴とするものである。(E. Means for Solving Problems) In order to solve the above problems, the memory cell of the present invention is characterized in that a capacitor extending perpendicularly to the periphery of a capacitor portion extending on a plane is added. It is something to do.
従って、本発明メモリセルによれば、平面方向における
占有面積を大きくすることなく静電容量を大きくするこ
とができる。Therefore, according to the memory cell of the present invention, the capacitance can be increased without increasing the occupied area in the planar direction.
（Ｆ、実施例）［第１図、第２図］
以下に、本発明メモリセルを添附図面に示した実施例に
従って詳細に説明する。(F. Embodiment) [FIGS. 1 and 2] The memory cell of the present invention will be described in detail below according to the embodiment shown in the accompanying drawings.
（ａ、製造方法）［第１図］
第１図（Ａ）乃至（Ｅ）は本発明メモリセルの実施の一
例の製造方法を工程順に示す断面図である。(a. Manufacturing method) [FIG. 1] FIGS. 1(A) to (E) are cross-sectional views showing, in order of steps, a manufacturing method of an embodiment of the memory cell of the present invention.
（Ａ）シリコン半導体基板１表面部に選択酸化法により
フィールド絶縁膜２を形成し、半導体基板１のセル形成
領域にＭＯＳＦＥＴ３を形成する。４はそのゲート絶縁
膜、５は多結晶シリコンからなるゲート電極、５′は上
記ＭＯＳＦＥＴ３の隣りのＭＯＳＦＥＴのゲート電極、
６はドレイン、７はソース、８は層間絶縁膜、９は該層
間絶縁膜８に形成されたコンタクトホールで、ソース７
上に形成されている。(A) A field insulating film 2 is formed on the surface of a silicon semiconductor substrate 1 by selective oxidation, and a MOSFET 3 is formed in a cell formation region of the semiconductor substrate 1. 4 is its gate insulating film, 5 is a gate electrode made of polycrystalline silicon, 5' is the gate electrode of the MOSFET next to the MOSFET 3,
6 is a drain, 7 is a source, 8 is an interlayer insulating film, 9 is a contact hole formed in the interlayer insulating film 8, and the source 7
formed on top.
上記ＭＯＳＦＥＴ３を通常のシリコンゲートＭＯＳＦＥ
Ｔ形成技術により形成し、更に、層間絶縁膜８を形成し
、該絶縁膜８にコンタクトホール９を形成した後は、ソ
ース７に接続される多結晶シリコンからなる電極膜１０
を形成する。ところで１本実施例において電極膜（膜厚
３０００人）１０め表面にはシリコン酸化物（ＳｉＯ２
）からなる絶縁膜（膜厚５０００人）１１が設けられて
いる。具体的には、電極膜１０を成す多結晶シリコンを
ＣＶＤ法により形成した後絶縁膜１１を為すシリコン酸
化物（Ｓｉ０２）を例えばスピンオングラス（ＳＯＧ）
法により形成し、その後、その絶縁膜１１及び電極膜１
０をフォトエツチングにより選択的に除去してソース７
及びその周辺部上にのみ絶縁膜１１及び電極膜ｌＯを残
存させる。第１図（Ａ）は絶縁膜１１及び電極膜１ｏに
対するフォトエツチングの終了後の状態を示す。The above MOSFET3 is a normal silicon gate MOSFET.
After forming an interlayer insulating film 8 using a T-forming technique and forming a contact hole 9 in the insulating film 8, an electrode film 10 made of polycrystalline silicon connected to the source 7 is formed.
form. By the way, in this example, silicon oxide (SiO2
) is provided with an insulating film 11 (film thickness: 5000 mm). Specifically, polycrystalline silicon forming the electrode film 10 is formed by a CVD method, and then silicon oxide (Si02) forming the insulating film 11 is formed using spin-on glass (SOG), for example.
After that, the insulating film 11 and electrode film 1 are formed by
0 is selectively removed by photoetching to form the source 7.
The insulating film 11 and the electrode film 1O are left only on the periphery thereof. FIG. 1(A) shows the state after the photoetching of the insulating film 11 and the electrode film 1o is completed.
（Ｂ）次に、同図（Ｂ）に示すようにサイドウオール形
成用の多結晶シリコン膜（３０００人）１２を形成する
。この多結晶シリコン膜１２のステップカバレージの良
い成長方法により形成する。(B) Next, as shown in Figure (B), a polycrystalline silicon film (3000 layers) 12 for forming sidewalls is formed. This polycrystalline silicon film 12 is formed by a growth method that provides good step coverage.
（Ｃ）次いで、多結晶シリコン膜１２に対してＲＩＥ等
の異方性エツチング処理を施すことにより前記絶縁膜１
１及び電極膜ｌＯの側面にのみ多結晶シリコン膜１２が
サイドウオールとして残存するようにする。１３はその
多結晶シリコン膜１２の残存部、即ち、サイドウオール
である。(C) Next, the polycrystalline silicon film 12 is subjected to an anisotropic etching process such as RIE, thereby etching the insulating film 1.
The polycrystalline silicon film 12 is made to remain as a sidewall only on the side surfaces of the electrode film 1 and the electrode film IO. Reference numeral 13 indicates a remaining portion of the polycrystalline silicon film 12, that is, a sidewall.
その後、電極膜ＩＯ上の絶縁膜１１をエッチオフする。After that, the insulating film 11 on the electrode film IO is etched off.
このようにして電極膜ｌＯの周縁にそこから上方へ垂直
方向に延びるサイドウオール１３が形成される。そして
、電極膜１０及びサイドウオール１３が情報蓄積用コン
デンサの一方の電極となる。第１図（Ｃ）は絶縁膜１１
除去後の状態を示す。In this way, a sidewall 13 is formed at the periphery of the electrode film 1O, extending vertically upward therefrom. Then, the electrode film 10 and the sidewall 13 become one electrode of the information storage capacitor. FIG. 1(C) shows the insulating film 11.
Shows the state after removal.
（Ｄ）次に、コンデンサの誘電膜１４を形成する− ８
ｊＥ誘電膜１４はＣＶＤによるシリコン酸化物（Ｓｉ０
２）あるいはシリコンの加熱酸化によるシリコン酸化物
（Ｓ ｉ Ｏ２）あるいはシリコン酸化物（Ｓｉ０２）
・ナイトライド（ＳｉＮ）・シリコン酸化物（Ｓｉ０２
）の三重層により形成される。(D) Next, form the dielectric film 14 of the capacitor - 8
The jE dielectric film 14 is made of silicon oxide (Si0
2) Or silicon oxide (S i O2) or silicon oxide (Si02) by thermal oxidation of silicon
・Nitride (SiN) ・Silicon oxide (Si02
) is formed by a triple layer of
次いで、誘電膜１４上にコンデンサのもう一方の電極を
成す電極膜１０を形成する。該電極膜１０は多結晶シリ
コンのＣＶＤにより形成する。これにより、電極膜１５
、誘電膜１４及び電極膜ｌＯ・サイドウオール１３から
なるコンデンサ１６が形成される。該コンデンサ１６は
略一平面上に延びる略平板状部１６ａと、該平板状部１
６ａの周縁から垂直に上方に延びる垂直部１６ｂとから
なる。そして、略平板状部１６ａは多結晶シリコンから
なる電極膜１０［第１図（Ａ）に示した工程で形成され
る］と、誘電膜１４のその電極膜１０と対応する部分と
、電極膜１５の電極膜１０と対応する部分と、からなる
。また、垂直部１６ｂは多結晶シリコンからなるサイド
ウオール１３と、ＡＡ電膜１４のそのサイドウオール１
３と対応する部分と、電極膜１５のサイドウオール１３
と対応する部分と、からなる。Next, an electrode film 10 forming the other electrode of the capacitor is formed on the dielectric film 14. The electrode film 10 is formed by CVD of polycrystalline silicon. As a result, the electrode film 15
, a capacitor 16 consisting of a dielectric film 14 and an electrode film lO/sidewall 13 is formed. The capacitor 16 includes a substantially flat portion 16a extending on approximately one plane, and the flat portion 1.
6a, and a vertical portion 16b extending perpendicularly upward from the peripheral edge of 6a. The approximately flat plate-shaped portion 16a includes an electrode film 10 made of polycrystalline silicon [formed in the process shown in FIG. 1(A)], a portion of the dielectric film 14 corresponding to the electrode film 10, and an electrode film 15 electrode films 10 and corresponding portions. Further, the vertical portion 16b includes the sidewall 13 made of polycrystalline silicon and the sidewall 1 of the AA electric film 14.
3 and the side wall 13 of the electrode film 15
and a corresponding part.
第１図ＣＩ））は電極膜１３形成後の状態を示す。FIG. 1 CI)) shows the state after the electrode film 13 is formed.
（Ｅ）次いで、電極膜１５に対して選択的にエツチング
することにより電極膜１５の不要部分を除去する。尚、
電極膜１５は接地される。(E) Next, unnecessary portions of the electrode film 15 are removed by selectively etching the electrode film 15. still,
The electrode film 15 is grounded.
次いで、電極膜１５の形成後層間絶縁膜１７を形成し、
該絶縁膜１７のドレイン６と対応する位置にコンタクト
ホール１８を形成し、その後、アルミニウムからなる配
線膜１９を形成する。該配線膜１９はコンタクトホール
１８を通してドレイン６と接続されたビットラインであ
る。該配線膜１９はＭＯＳＦＥＴ３を介してコンデンサ
１６に接続されている。Next, after forming the electrode film 15, an interlayer insulating film 17 is formed,
A contact hole 18 is formed in the insulating film 17 at a position corresponding to the drain 6, and then a wiring film 19 made of aluminum is formed. The wiring film 19 is a bit line connected to the drain 6 through the contact hole 18. The wiring film 19 is connected to the capacitor 16 via the MOSFET 3.
このようにしてＭＯＳＦＥＴ３とトランジスタ１６とか
らなるメモリセルが製造される。In this way, a memory cell consisting of MOSFET 3 and transistor 16 is manufactured.
第２図１主メモリセル形成後［第１図（Ｅ）の工程終了
後〕における平面図である。尚、同図において格子状部
分はコンタクト部分である。FIG. 2 is a plan view after forming the main memory cell [after the step shown in FIG. 1(E)]. Note that the grid-like portions in the figure are contact portions.
（ｂ、構成）［第１図、第２図］
図示したメモリセルは、ビットラインを成す配線膜１９
がコンタクトホール１８を介してＭＯＳＦＥＴ３のドレ
イン６に接続されている。そして、ソース７はコンデン
サ１６の略平板状の電極膜１０とコンタクトホール９を
介して電気的に接続されている。該電極膜１０の周縁に
はそれと略垂直方向に上方に延びるところの多結晶シリ
コンからなるサイドウオール１３が一体に形成されてお
り、電極膜ｌＯ及びサイドウオール１３の表面には誘電
膜１４を介して電極膜１５が形成されている。しかして
、電極膜ｌＯ及び絶縁膜１３と、電極膜１５の誘電膜１
４を介して電極膜１０及び誘電膜１３と対向する部分と
、によって情報蓄積用のコンデンサ１６が形成される。(b, Configuration) [Figures 1 and 2] The illustrated memory cell has a wiring film 19 forming a bit line.
is connected to the drain 6 of the MOSFET 3 via a contact hole 18. The source 7 is electrically connected to the substantially flat electrode film 10 of the capacitor 16 via the contact hole 9. A side wall 13 made of polycrystalline silicon is integrally formed on the periphery of the electrode film 10 and extends upward in a direction substantially perpendicular to the electrode film 10. A dielectric film 14 is interposed between the electrode film 10 and the surface of the side wall 13. An electrode film 15 is formed thereon. Therefore, the electrode film lO, the insulating film 13, and the dielectric film 1 of the electrode film 15
A capacitor 16 for storing information is formed by the electrode film 10 and the portion facing the dielectric film 13 via the capacitor 4 .
依って、１つのＭＯＳＦＥＴ３とそれに直列に接続され
たコンデンサ１６とからなるメモリセルが構成される６
ソシテ、ＭＯＳＦＥＴ３のゲート電極５．５′がメモリ
セルのワードラインをなす。Therefore, a memory cell consisting of one MOSFET 3 and a capacitor 16 connected in series with it is configured 6.
The gate electrode 5.5' of MOSFET 3 forms the word line of the memory cell.
（ｃ、作用）
上述したメモリセルによれば、第３図に示した従来例に
おける電極膜りに相当する電極膜１０の上にサイドウオ
ール１３の高さをかせぐための絶縁膜１１を設けること
とし、電極膜１０及び絶縁膜１１の形成後その周縁に多
結晶シリコンからなるサイドウオール１３を形成し、そ
の電極膜１０とサイドウオール１３とをもってコンデン
サ１６の一方の電極としたので、垂直に延びるサイドウ
オール１３によってコンデンサの占有面積を大きくする
ことなく静゛屯容量を大きくすることができる。従って
、メモリセルの占有面積を大きくすることなくコンデン
サの静電容量を大きくすることができる。これは、視点
を変えてみれば、必要な静電容量を確保するに要するコ
ンデンサあるいはメモリセルの占有面積を狭くすること
ができることを意味する。そして、サイドウオール１３
により静電容量を増す量を変えるにはサイドウオール１
３の高さを変えれば良い（これはとりもなおさず電極膜
１０上に形成する絶縁膜１１（第１図（Ａ）参照］の厚
さを変えれば良い）、そして、サイドウオール１３によ
り静電容量を項す量を背えてもコンデンサ１６の占有面
積は全く変わらない。(c. Effect) According to the above-described memory cell, an insulating film 11 for increasing the height of the sidewall 13 is provided on the electrode film 10 corresponding to the electrode film in the conventional example shown in FIG. After forming the electrode film 10 and the insulating film 11, a side wall 13 made of polycrystalline silicon was formed on the periphery of the electrode film 10 and the insulating film 11, and the electrode film 10 and the side wall 13 were used as one electrode of the capacitor 16, so that the capacitor 16 extends vertically. The sidewall 13 allows the static capacitance to be increased without increasing the area occupied by the capacitor. Therefore, the capacitance of the capacitor can be increased without increasing the area occupied by the memory cell. From a different perspective, this means that the area occupied by the capacitor or memory cell required to secure the necessary capacitance can be reduced. And sidewall 13
To change the amount of capacitance increased by sidewall 1
3 (this can be done by changing the thickness of the insulating film 11 (see FIG. 1 (A)) formed on the electrode film 10), and the side wall 13 can be The area occupied by the capacitor 16 does not change at all even if the capacitance is reduced.
（Ｇ、発明の効果）
以上に述べたところから明らかなように、本発明メモリ
セルは、コンデンサが、略二次元面上に延在する部分と
、該部分の周辺に上記二次元面に対して垂直に形成され
た部分とから成ることを特徴とするものである。(G. Effects of the Invention) As is clear from the above description, the memory cell of the present invention has a capacitor in a portion extending on a substantially two-dimensional surface, and a capacitor in the periphery of the portion with respect to the two-dimensional surface. It is characterized by consisting of vertically formed parts.
従って、本発明メモリセルによれば、情報蓄積用コンデ
ンサの平面方向における占有面積を大きくすることなく
静電容量を大きくすることができる。Therefore, according to the memory cell of the present invention, the capacitance can be increased without increasing the area occupied by the information storage capacitor in the planar direction.
第１図及び第２図は本発明メモリセルの実施の一例を説
明するためのもので、第１図（Ａ）乃至（Ｅ）はメモリ
セルの製造方法を工程順に示す断面図、特に同図（Ｅ）
は完成した状態を示し、第２図は完成したメモリセルの
平面図、第３図はメモリセルの従来例の−を示す断面図
である。
符号の説明
３１・トランジスタ、
１６壷・・コンデンサ、
１６ａ・・・略二次元面上に延在する部分、１６ｂ・・
・垂直に形成された部分
３（Ａ）
第１図
３−１−ランソ又り
３ （Ｄ）
第１図
３−・・Ｌランシ゛又り
１５−・コン千゛し寸
５！ｉ′
：Ｐ 命 Ｑ
第２図
イ課二Ｊミイη１１ を 含ミ 支
煎 狛 配
第３図1 and 2 are for explaining an example of implementation of the memory cell of the present invention, and FIGS. 1(A) to 1(E) are cross-sectional views showing the method of manufacturing the memory cell in the order of steps, especially the same figure. (E)
2 shows a completed state, FIG. 2 is a plan view of the completed memory cell, and FIG. 3 is a cross-sectional view of a conventional example of the memory cell. Explanation of symbols 31: Transistor, 16: Capacitor, 16a: Portion extending on a substantially two-dimensional surface, 16b:
・Vertically formed portion 3 (A) Fig. 1 3-1 - Ransho matari 3 (D) Fig. 1 3 - L lanshi matari 15 - Contour length 5! i' : P Life Q Figure 2 A Division 2 J Mii η11 Contains Mi Seikan Koma Arrangement Figure 3
Claims (1)
メモリセルにおいて、 上記コンデンサが、略二次元面上に延在する部分と、該
部分の周辺に上記二次元面に対して垂直に形成された部
分と、 から成ることを特徴とするメモリセル(1) In a memory cell consisting of one capacitor and one transistor, a portion in which the capacitor extends approximately on a two-dimensional surface, and a portion formed around the portion perpendicular to the two-dimensional surface A memory cell characterized by comprising: and
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60188818A JPS6248062A (en) | 1985-08-28 | 1985-08-28 | Memory cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60188818A JPS6248062A (en) | 1985-08-28 | 1985-08-28 | Memory cell |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6248062A true JPS6248062A (en) | 1987-03-02 |
Family
ID=16230352
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60188818A Pending JPS6248062A (en) | 1985-08-28 | 1985-08-28 | Memory cell |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6248062A (en) |
Cited By (28)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63318152A (en) * | 1987-06-19 | 1988-12-27 | Fujitsu Ltd | Dynamic random access memory |
| JPH01257365A (en) * | 1988-04-07 | 1989-10-13 | Fujitsu Ltd | Semiconductor integrated circuit device |
| JPH0258374A (en) * | 1988-08-24 | 1990-02-27 | Hitachi Ltd | Semiconductor integrated circuit device |
| US4974040A (en) * | 1987-06-17 | 1990-11-27 | Fujitsu Limited | Dynamic random access memory device and method of producing same |
| US4977102A (en) * | 1987-11-17 | 1990-12-11 | Fujitsu Limited | Method of producing layer structure of a memory cell for a dynamic random access memory device |
| JPH03135670A (en) * | 1989-10-20 | 1991-06-10 | Kubota Corp | Data base system containing intelligent retrieving method |
| JPH03180065A (en) * | 1989-12-08 | 1991-08-06 | Mitsubishi Electric Corp | Semiconductor device |
| JPH03180062A (en) * | 1989-12-08 | 1991-08-06 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH03214767A (en) * | 1990-01-19 | 1991-09-19 | Nec Corp | Manufacture of semiconductor device |
| JPH03232271A (en) * | 1989-11-30 | 1991-10-16 | Hyundai Electron Ind Co Ltd | Semiconductor element with cylindrical type laminated capacitor and manufacture |
| JPH03263370A (en) * | 1990-02-16 | 1991-11-22 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| US5071783A (en) * | 1987-06-17 | 1991-12-10 | Fujitsu Limited | Method of producing a dynamic random access memory device |
| JPH03296263A (en) * | 1990-04-16 | 1991-12-26 | Nec Corp | Semiconductor memory cell and its manufacture |
| JPH04320370A (en) * | 1991-03-23 | 1992-11-11 | Samsung Electron Co Ltd | Semiconductor device and manufacture thereof |
| US5314835A (en) * | 1989-06-20 | 1994-05-24 | Sharp Kabushiki Kaisha | Semiconductor memory device |
| JPH06236971A (en) * | 1993-02-12 | 1994-08-23 | Nec Corp | Semiconductor memory |
| US5436187A (en) * | 1994-02-22 | 1995-07-25 | Nec Corporation | Process for fabricating a semiconductor memory device including a capacitor having a cylindrical storage node electrode |
| JPH07326717A (en) * | 1993-12-31 | 1995-12-12 | Hyundai Electron Ind Co Ltd | Semiconductor memory device and manufacturing method |
| US5650647A (en) * | 1987-06-17 | 1997-07-22 | Fujitsu Limited | Dynamic random access memory device and method of producing same |
| KR100235983B1 (en) * | 1991-09-11 | 1999-12-15 | 김영환 | Multilayer Capacitor Manufacturing Method |
| US6028334A (en) * | 1995-12-18 | 2000-02-22 | Nec Corporation | Semiconductor device and method of manufacturing the same |
| US6057190A (en) * | 1996-06-24 | 2000-05-02 | Nec Corporation | Method of manufacturing semiconductor device |
| US6097053A (en) * | 1996-08-22 | 2000-08-01 | Nec Corporation | Semiconductor device having a multi-wall cylindrical capacitor |
| US6340619B1 (en) | 1996-12-26 | 2002-01-22 | Lg Semicon Co., Ltd. | Capacitor and method of fabricating the same |
| US6403455B1 (en) | 2000-08-31 | 2002-06-11 | Samsung Austin Semiconductor, L.P. | Methods of fabricating a memory device |
| US6407420B1 (en) | 1996-12-20 | 2002-06-18 | Hitachi, Ltd. | Integrated circuit device having line width determined by side wall spacer provided in openings formed in insulating film for connection conductors |
| US6576510B2 (en) | 1999-06-17 | 2003-06-10 | Hitachi Ltd | Method of producing a semiconductor memory device using a self-alignment process |
| US6689668B1 (en) | 2000-08-31 | 2004-02-10 | Samsung Austin Semiconductor, L.P. | Methods to improve density and uniformity of hemispherical grain silicon layers |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59112646A (en) * | 1982-12-20 | 1984-06-29 | Fujitsu Ltd | semiconductor storage device |
-
1985
- 1985-08-28 JP JP60188818A patent/JPS6248062A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59112646A (en) * | 1982-12-20 | 1984-06-29 | Fujitsu Ltd | semiconductor storage device |
Cited By (32)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5071783A (en) * | 1987-06-17 | 1991-12-10 | Fujitsu Limited | Method of producing a dynamic random access memory device |
| US4974040A (en) * | 1987-06-17 | 1990-11-27 | Fujitsu Limited | Dynamic random access memory device and method of producing same |
| US5021357A (en) * | 1987-06-17 | 1991-06-04 | Fujitsu Limited | Method of making a dram cell with stacked capacitor |
| US5650647A (en) * | 1987-06-17 | 1997-07-22 | Fujitsu Limited | Dynamic random access memory device and method of producing same |
| JPS63318152A (en) * | 1987-06-19 | 1988-12-27 | Fujitsu Ltd | Dynamic random access memory |
| US4977102A (en) * | 1987-11-17 | 1990-12-11 | Fujitsu Limited | Method of producing layer structure of a memory cell for a dynamic random access memory device |
| JPH01257365A (en) * | 1988-04-07 | 1989-10-13 | Fujitsu Ltd | Semiconductor integrated circuit device |
| JPH0258374A (en) * | 1988-08-24 | 1990-02-27 | Hitachi Ltd | Semiconductor integrated circuit device |
| US5334869A (en) * | 1989-06-20 | 1994-08-02 | Sharp Kabushiki Kaisha | Semiconductor memory device |
| US5314835A (en) * | 1989-06-20 | 1994-05-24 | Sharp Kabushiki Kaisha | Semiconductor memory device |
| JPH03135670A (en) * | 1989-10-20 | 1991-06-10 | Kubota Corp | Data base system containing intelligent retrieving method |
| JPH03232271A (en) * | 1989-11-30 | 1991-10-16 | Hyundai Electron Ind Co Ltd | Semiconductor element with cylindrical type laminated capacitor and manufacture |
| JPH03180062A (en) * | 1989-12-08 | 1991-08-06 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH03180065A (en) * | 1989-12-08 | 1991-08-06 | Mitsubishi Electric Corp | Semiconductor device |
| JPH03214767A (en) * | 1990-01-19 | 1991-09-19 | Nec Corp | Manufacture of semiconductor device |
| JPH03263370A (en) * | 1990-02-16 | 1991-11-22 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| JPH03296263A (en) * | 1990-04-16 | 1991-12-26 | Nec Corp | Semiconductor memory cell and its manufacture |
| JPH04320370A (en) * | 1991-03-23 | 1992-11-11 | Samsung Electron Co Ltd | Semiconductor device and manufacture thereof |
| KR100235983B1 (en) * | 1991-09-11 | 1999-12-15 | 김영환 | Multilayer Capacitor Manufacturing Method |
| JPH06236971A (en) * | 1993-02-12 | 1994-08-23 | Nec Corp | Semiconductor memory |
| JPH0831575B2 (en) * | 1993-02-12 | 1996-03-27 | 日本電気株式会社 | Semiconductor memory device |
| JPH07326717A (en) * | 1993-12-31 | 1995-12-12 | Hyundai Electron Ind Co Ltd | Semiconductor memory device and manufacturing method |
| US5436187A (en) * | 1994-02-22 | 1995-07-25 | Nec Corporation | Process for fabricating a semiconductor memory device including a capacitor having a cylindrical storage node electrode |
| US6028334A (en) * | 1995-12-18 | 2000-02-22 | Nec Corporation | Semiconductor device and method of manufacturing the same |
| US6057190A (en) * | 1996-06-24 | 2000-05-02 | Nec Corporation | Method of manufacturing semiconductor device |
| US6097053A (en) * | 1996-08-22 | 2000-08-01 | Nec Corporation | Semiconductor device having a multi-wall cylindrical capacitor |
| US6407420B1 (en) | 1996-12-20 | 2002-06-18 | Hitachi, Ltd. | Integrated circuit device having line width determined by side wall spacer provided in openings formed in insulating film for connection conductors |
| US6340619B1 (en) | 1996-12-26 | 2002-01-22 | Lg Semicon Co., Ltd. | Capacitor and method of fabricating the same |
| US6576510B2 (en) | 1999-06-17 | 2003-06-10 | Hitachi Ltd | Method of producing a semiconductor memory device using a self-alignment process |
| US6661048B2 (en) | 1999-06-17 | 2003-12-09 | Hitachi, Ltd. | Semiconductor memory device having self-aligned wiring conductor |
| US6403455B1 (en) | 2000-08-31 | 2002-06-11 | Samsung Austin Semiconductor, L.P. | Methods of fabricating a memory device |
| US6689668B1 (en) | 2000-08-31 | 2004-02-10 | Samsung Austin Semiconductor, L.P. | Methods to improve density and uniformity of hemispherical grain silicon layers |
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