JPS6247009B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a detection circuit for detecting an idle line (or idle signal line) of a communication line (or signal line), and particularly relates to an idle line detection circuit with a fast detection time.

As shown in FIG. 1, a conventional mobile radio communication system including an idle line detection circuit is composed of a mobile device 1, a radio base station 2, a communication path device 3, a switching equipment 4, a telephone set 5, and an idle line detection circuit 6. There is. Further, the communication path device 3 includes communication path boards 31 to 34. Further, the idle line detection circuit 6 includes a scanner 60 and an information output circuit 6.
5 and AND gates 61 to 64. In the figure, when making a call connection between the mobile device 1 and the fixed subscriber's telephone device 5, an arbitrary unused line (empty line) is selected from among the plurality of call paths _L1 to _L0 . need to be detected. Each call path
L ₁ to _{L o} are connected from the exchange 4 to communication path boards 31 to 34 in the communication path device 3, and on the radio side, each communication path board is connected to the radio base station 2. Each communication path is in charge of connection control between the mobile device 1 and the exchange 4 until a call can be made between the mobile device 1 and the telephone 5, and each communication path is managed by each communication path. When detecting an empty communication line, by connecting the status signal, that is, "empty" information from each of the communication bases 31 to 34 to one input of the AND gates 61 to 64, the detection of an empty line can be performed as shown below. .

“Empty” information is input to AND gates 61 to 64, and each
A logic level "1" is input to one of the AND gates 61 to 64 in order, and the state of "empty" information is sequentially detected and stored in the information output circuit 65, displayed, or converted into a signal. As is clear from the above explanation, when "empty" information is input only to the AND gate 64, the scanner 60
Since it scans sequentially from 1 to 64, AND gates 61 to 64 must be scanned before reaching AND gate 64.
If there are n numbers, extra searches will be performed n-1 times, so it will take time until the "empty" number is determined. Further, since the scanner 60 is composed of only one scanner, there are drawbacks such as low reliability.

SUMMARY OF THE INVENTION An object of the present invention is to provide an idle line detection circuit which eliminates the above-mentioned drawbacks.

The idle line detection circuit of the present invention is characterized in that the detection time is shortened and the reliability is improved by eliminating the scanner and using simple logic elements such as AND gates.

The idle line detection circuit of the present invention will be explained below with reference to FIG.

In FIG. 2, 7, 8, 9 are logic gate circuits, 10 is a priority designation circuit, 11 is an empty information reception number generation circuit, 71, 74, 81, 84, 91,
94 is an inverter, 72, 73, 75, 82, 8
3, 85, 92, 93, 95 are NAND gates, X _1
.about.X3 is an input terminal for "empty" information signals from the communication bases 31-34 in FIG. 1, and D is an output terminal for "vacant" numbers.

It is assumed that a logic level "0\" is input to the input terminals _X1 to _X3 when they are "empty", and a logic level "1" is input when they are "in use". In addition, the logic gate circuits 7 to 9 are, for example, a priority designation circuit 10.
The initial setting is made by setting any one of the outputs to logic level "1".

First, the logic gate circuit 7 will be explained. Assume that "empty" information is now input to input terminal _X1 . The signal input to the input terminal _X1 is input to one side of the NAND gate 73. Also, NAND gate 73
The output of the NAND gate 75 is input to the other input terminal of the . The two input terminals of the NAND gate 75 are externally operated terminals, and one input terminal receives the output signal of the NAND gate 93 of the logic gate circuit 9 in the previous stage. The other signal is input from the priority order designation circuit 10. This logic gate circuit 7
, _the output (first output) of the NAND gate 72 is the input terminal (input terminal from the signal line)
is "0" and the output signal (second control signal) of the NAND gate 93 in the previous stage is "0", or the output signal (first control signal) and the second control signal of the priority designation circuit 10 are "0". When both are “1”,
It becomes "0" and becomes "1" in other cases. Moreover, the output (second output) of the NAND gate 73 is
When the signal at _input terminal It becomes “1”. Therefore, for example,
When “0\” is input to the input terminal that is affected by the previous stage among the two input terminals of the NAND gate 75,
The output of the NAND gate 75 becomes "1" and the signal is input to the NAND gate 73 and the NAND gate 72. Since the “empty” information “1” inverted by the inverter 71 is input to the other input terminal of the NAND gate 72, the output of the NAND gate 72 is “0”.
As a result, "empty" information is output. On the other hand, since "0", which is "empty" information, is input to the other NAND gate 73, "1" is output from the NAND gate 73 to the logic gate circuit 8. Also NAND gate 7
5, when "0\" is input from the priority order designation circuit 10 via the inverter 74,
The output of the NAND gate 75 becomes "1", indicating that this logic gate circuit 7 is designated, and if there is "empty" information, the output of the NAND gate 73 becomes "1".

The above explanation has been about the logic gate circuit 7, but the circuits 8 and 9 also operate in the same way, and these logic gate circuits 8 and 9 are as shown in FIG.
Generally n through NAND gates 73, 83, 93
Individually connected in cascade.

In the case of such a connection, among the "empty" information input terminals X ₁ to _{X 3} of n logic gate circuits, "0" is input to input terminal X ₁ , and "1" is input to X ₂ and X ₃ . In this case, the NAND gate 75 of the logic gate circuit 7,
The output of the preceding stage logic gate circuit 9, 7 or 8 is input to one input terminal of 85 or 95, and the other input terminal for specifying priority level is set to "1" only in the case of logic gate circuit 7. If you input “0” to other logic gate circuits, the NAND gate 73
The output becomes "1", and the logic gate circuits in the next and subsequent stages become inoperable. On the other hand, the output of the NAND gate 72 becomes " ₀ ", and therefore the terminal As a result, the selected "empty" information is converted into a corresponding number, and the corresponding "empty" number is sent to the output terminal D of the circuit. The above explanation is based on the case where there is only one "sky", but when there are multiple "sky" at the same time, as is clear from the circuit diagram in Figure 2, the sky information input to _X1 is the most become a priority
Priority is specified in the order of X ₁ →X ₃ .

In addition, by providing a priority order designation circuit 10 using an n-stage shift register in order to forcibly change the priority order sequentially in addition to the priority order, any one of the n output signals output from the designation circuit 10 is provided. If only one of them sequentially inputs a priority designation signal of logic level "1" to the designated input terminal of each logic gate circuit, the priority designation signal of " It is clear that if there is "empty" information, the "empty" number is output, and if there is no "empty" information, the "empty" information after the specified logic gate circuit is searched preferentially.

Note that when the priority designation circuit 10 is not used, the input of any one of the inverters 74, 84, and 94 may be set to "1" and the remaining inputs may be set to "0". Further, although the detection circuit of the present invention has been described in a mobile radio system, it can also be used in other systems.

As explained above, the detection circuit of the present invention can easily detect an "empty" line in a short time by using a digital circuit in which a plurality of simple logic gate circuits are connected in cascade.

[Brief explanation of the drawing]

FIG. 1 shows an example of a mobile radio system using a conventional idle line detection circuit, and FIG. 2 shows an example of an idle line detection circuit according to the present invention. In the figure, 1 is a mobile device, 2 is a wireless base station, and 3 is a mobile device.
4 is a communication path device, 4 is an exchange, 5 is a telephone set, 6 is an idle line detection circuit, 7, 8, and 9 are logic gate circuits, 1
0 is a priority designation circuit, 11 is an empty information reception number generation circuit, 31 to 34 are communication bases, 60 is a scanner, 61 to 64 are AND gates, 65 is an information output circuit, 71, 74, 81, 84, 91, 94 is an inverter, 72, 73, 75, 82, 83, 8
5, 92, 93, and 95 are NAND gates.

Claims (1)

[Claims] 1. In a detection circuit that detects one empty signal line among a plurality of signal lines, a first control signal input terminal, a second control signal input terminal, and a signal input from the signal line. It has a terminal, a first output terminal, and a second output terminal, and the first output terminal has a signal from a signal line at a first level and a second control signal at a first level or a first control level. When both the signal and the second control signal are at the second level, the level is at the first level, and at other times, the level is at the second level, and the second output terminal outputs the signal from the signal line at the second level and the second control signal. a plurality of logic gate circuits that are at the first level when the first level or the first control signal and the second control signal are both at the second level, and are at the second level otherwise; and the plurality of logic gate circuits. a priority designation circuit that supplies the first control signal to each of the first output terminals, and a vacant information reception number generation circuit that receives the signal from the first output terminal, and the signal from the second output terminal is applied to the logic of the next stage. A plurality of control signals are connected cyclically and sequentially to become the second control signal of the gate circuit, and one of the first control signals is set to the second level and the other to the first level. Among the signal lines, the one with the highest priority from the empty signal line
An empty signal line detection circuit characterized by detecting only two empty signal lines. 2. In a detection circuit that detects one empty signal line among a plurality of signal lines, a first control signal input terminal, a second control signal input terminal, a signal input terminal from the signal line, and a first It has an output terminal and a second output terminal, and the first output terminal has a signal from the signal line at the first level and a second control signal at the first level, or the first control signal and the second control signal. When the signals are both at the second level, they are at the first level, and at other times they are at the second level, and the second output terminal has a signal from the signal line at the second level and a second control signal at the first level or a plurality of logic gate circuits which are at the first level when both the control signal and the second control signal are at the second level, and which are at the second level at other times; It includes a priority order designation circuit that supplies a control signal, and an empty information reception number generation circuit that receives a signal from the first output terminal, and the signal from the second output terminal is used to send a signal from the second output terminal to the second logic gate circuit at the next stage. By connecting one of the first control signals to the second level and the others to the first level, either randomly or in an order, 1. An empty signal line detection circuit that detects only one empty signal line with a high priority from among the empty signal lines randomly or in an orderly manner.