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JPS6246983B2 - - Google Patents

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Publication number
JPS6246983B2
JPS6246983B2 JP9241478A JP9241478A JPS6246983B2 JP S6246983 B2 JPS6246983 B2 JP S6246983B2 JP 9241478 A JP9241478 A JP 9241478A JP 9241478 A JP9241478 A JP 9241478A JP S6246983 B2 JPS6246983 B2 JP S6246983B2
Authority
JP
Japan
Prior art keywords
element fixing
fixing region
metallized layer
ceramic substrate
conductive layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP9241478A
Other languages
Japanese (ja)
Other versions
JPS5519837A (en
Inventor
Shuichi Oosaka
Toshinobu Banjo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP9241478A priority Critical patent/JPS5519837A/en
Publication of JPS5519837A publication Critical patent/JPS5519837A/en
Publication of JPS6246983B2 publication Critical patent/JPS6246983B2/ja
Granted legal-status Critical Current

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  • Led Device Packages (AREA)

Description

【発明の詳細な説明】 この発明は、複数のセラミツク基板と積層した
際、セラミツク基板に形成された素子固着領域
と、他のセラミツク基板に形成され、外部電極に
それぞれ接続されたインナーリード部となる金属
化層の特定端子とが電気的に接続されたことを容
易に判別できるようにした半導体容器に関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION When stacked with a plurality of ceramic substrates, the present invention provides an element fixing region formed on the ceramic substrate and inner lead portions formed on other ceramic substrates connected to external electrodes. This invention relates to a semiconductor container in which it is possible to easily determine whether a metallized layer is electrically connected to a specific terminal.

第1図は従来の半導体容器を構成する3枚のセ
ラミツク基板の平面図をそれぞれ示すもので、1
Aは第1のセラミツク基板であり、この表面には
金属化された素子固着領域2が形成されている。
この金属化された素子固着領域2は既知の金属粉
末の焼付け法により形成される。1Bは第2のセ
ラミツク基板で、インナーリード部を形成するた
めの微細化された所定の金属化層3が形成され、
その中央部には開口部4が形成されている。1C
は第3のセラミツク基板で、内蔵する素子および
内部金属細線等を保護するためのもので、金属化
された封止帯5が形成され、その中央部には開口
部6が形成されている。また、第1のセラミツク
基板1Aには、第2のセラミツク基板1Bに形成
され、外部電極(図示せず)にそれぞれ接続され
る金属化層3の特定端子と素子固着領域2とを接
続するための導電層7が素子固着領域2の一部分
より設けられている。この第1のセラミツク基板
1Aの導電層7と第2のセラミツク基板1Bの例
えば特定端子8との接続は第2図に示すように積
層した各セラミツク基板1A,1B,1Cの側面
に形成した導電層9で連結される。
Figure 1 shows a plan view of three ceramic substrates constituting a conventional semiconductor container.
A is a first ceramic substrate, on the surface of which a metalized element fixing region 2 is formed.
This metallized element fixing region 2 is formed by a known metal powder baking method. 1B is a second ceramic substrate on which a predetermined miniaturized metallization layer 3 for forming an inner lead portion is formed;
An opening 4 is formed in the center thereof. 1C
1 is a third ceramic substrate, which is used to protect built-in elements, internal thin metal wires, etc., and has a metalized sealing band 5 formed therein, and an opening 6 formed in the center thereof. The first ceramic substrate 1A also has a device for connecting the element fixing region 2 to specific terminals of the metallized layer 3 formed on the second ceramic substrate 1B and connected to external electrodes (not shown). A conductive layer 7 is provided from a portion of the element fixing region 2. The connection between the conductive layer 7 of the first ceramic substrate 1A and, for example, a specific terminal 8 of the second ceramic substrate 1B is made using a conductive layer formed on the side surface of each laminated ceramic substrate 1A, 1B, 1C as shown in FIG. They are connected by layer 9.

このような各セラミツク基板1A,1B,1C
を積層することにより構成される中空状の半導体
容器では、素子固着領域2と金属化層3の特定端
子との接続を明らかにするために次のような方法
をとつている。すなわち、例えば第3図aに示す
ように第3のセラミツク基板1Cの表面上に特定
目印10(例えばその端子番号)をつけたり、第
2のセラミツク基板1B上の特定端子またはその
近傍に第3図bに示すような目印11を形成し、
その接続個所を判別していた。なお、第3図aに
示す12は半導体素子、13は前記半導体素子1
2と金属化層3に設けられたインナーリード部を
接続する金属細線である。
Each of these ceramic substrates 1A, 1B, 1C
In a hollow semiconductor container constructed by laminating layers, the following method is used to clarify the connection between the element fixing region 2 and a specific terminal of the metallized layer 3. That is, for example, as shown in FIG. 3a, a specific mark 10 (for example, its terminal number) may be placed on the surface of the third ceramic substrate 1C, or a specific mark 10 (for example, its terminal number) may be placed on the second ceramic substrate 1B at or near the specific terminal as shown in FIG. Forming a mark 11 as shown in b,
The connection point was determined. Note that 12 shown in FIG. 3a is a semiconductor element, and 13 is the semiconductor element 1.
2 and the inner lead portion provided on the metallized layer 3.

しかしながら、このような方法では同一寸法、
同一外形、また同一寸法の開口部でかつ同一配置
のインナーリード部を持つ半導体容器で、素子固
着領域2とインナーリード部が形成される金属化
層3の特定端子とを接続する容器を複数種類作る
必要のあるときには次のような欠点がある。つま
り、それぞれのセラミツク基板1A,1B,1C
上に素子固着領域2、金属化層3、封止帯5をそ
れぞれ形成するのに必要な印刷マスクは、素子
固着領域用、金属化層形成用、封止帯形成
用、さらに素子固着領域2と金属化層3の特定端
子との接続を明示するための目印形成用の4種
類が必要である。また、とあるいはとを
同一マスクに形成した場合にも素子固着領域2と
金属化層3の接続に応じて印刷マスクを増やさな
くてはならない。また、の金属化層形成用ある
いはの封止帯形成用の印刷マスク上にの目印
形成用の印刷マスクを重ねたり、あるいはと
とは別の印刷マスクを形成し、素子固着領域2と
金属化層3の特定端子を接続する場合には、それ
ぞれの接続に応じての素子固着用の印刷マスク
の変更との目印形成用の印刷マスクの変更をし
なければならなかつた。
However, with this method, the same dimensions,
There are multiple types of semiconductor containers that have openings with the same external shape, the same dimensions, and inner lead parts arranged in the same way, and which connect the element fixing region 2 and the specific terminals of the metallized layer 3 where the inner lead parts are formed. When it is necessary to create one, there are the following drawbacks. In other words, each ceramic substrate 1A, 1B, 1C
The printing masks required to form the element fixing region 2, metallized layer 3, and sealing band 5 on the top are those for the element fixing region, the metallized layer formation, the sealing band formation, and the element fixing region 2. Four types of markings are required to clearly indicate the connection between the terminal and the specific terminal of the metallized layer 3. Further, even if the printing mask and the printing mask are formed on the same mask, the number of printing masks must be increased depending on the connection between the element fixing region 2 and the metallized layer 3. In addition, a printing mask for forming a mark may be overlaid on a printing mask for forming a metallized layer or a sealing band, or a separate printing mask may be formed to cover the element fixing region 2 and metallization. When connecting specific terminals on layer 3, it was necessary to change the printing mask for fixing the elements and the printing mask for forming marks according to each connection.

したがつて使用する印刷マスクの枚数が増える
ばかりでなく、その工程に多くの時間を要する等
の欠点があつた。
Therefore, not only the number of printing masks used increases, but also the process requires a lot of time.

この発明は、上記欠点を除去するためになされ
たもので、基板上に素子固着領域を形成するのと
同時に接続個所を表示する目印となる欠落部を形
成するようにし、印刷マスクを増やすことなしに
素子固着領域と金属化層の特定端子の接続個所を
明示できるようにしたものである。以下この発明
について説明する。
This invention was made in order to eliminate the above-mentioned drawbacks, and at the same time as forming an element fixing area on a substrate, a missing part that serves as a mark for indicating a connection point is formed, thereby eliminating the need for increasing the number of printing masks. This makes it possible to clearly indicate the connection point between the element fixing region and the specific terminal of the metallized layer. This invention will be explained below.

第4図はこの発明の一実施例を示す半導体容器
の平面図で、第1図〜第3図と同一符号は同一部
分を示し、14は前記第1のセラミツク基板1A
上の素子固着領域2と金属化層3との境界部に形
成された接続個所を表示するための目印となる欠
落部である。この欠落部14は第2のセラミツク
基板1Bの開口部4の領域内でかつ第2のセラミ
ツク基板1Bの素子固着領域2と接続の金属化層
3の特定端子の直下に位置させてその接続個所を
明示するようにしたものである。
FIG. 4 is a plan view of a semiconductor container showing an embodiment of the present invention, in which the same reference numerals as in FIGS. 1 to 3 indicate the same parts, and 14 indicates the first ceramic substrate 1A.
This is a missing portion that serves as a mark for indicating a connection point formed at the boundary between the upper element fixing region 2 and the metallized layer 3. This missing portion 14 is located within the area of the opening 4 of the second ceramic substrate 1B and directly below the specific terminal of the metallized layer 3 connected to the element fixing region 2 of the second ceramic substrate 1B, and is located at the connection point. It is designed to clearly indicate.

このような欠落部14を形成するには、第5図
に示すように素子固着領域用の印刷マスク15に
素子固着領域2と導電層7を作るときに、前記素
子固着領域2と導電層7との境界部に欠落部14
を作ればよい。
In order to form such a missing portion 14, when forming the element fixing area 2 and the conductive layer 7 on the printing mask 15 for the element fixing area, as shown in FIG. Missing part 14 at the boundary with
All you have to do is make it.

このような構造にすることにより各セラミツク
基板上に所定の金属化層を形成するための印刷マ
スクは、その接続状態に応じて素子固着領域用の
印刷マスクのみを変えればよく、金属化層形成用
の印刷マスクや、封止帯用の印刷マスクは共用す
ることが可能となる。
With this structure, the printing mask for forming a predetermined metallized layer on each ceramic substrate only needs to be changed depending on the connection state, and only the printing mask for the element fixing area can be changed. It becomes possible to share the printing mask for the sealing band and the printing mask for the sealing band.

以上説明したように、この発明は素子固着領域
とインナーリード部となる金属化層の特定端子と
の接続個所を明示するための目印となる欠落部
を、素子固着領域および導電層を形成するときに
同時に形成し、半導体容器を構成したので、素子
固着領域と金属化層の特定端子との接続個所が容
易に判別できる。また、所定の金属化層を形成す
るための印刷マスクが少なくてすみ、したがつて
工程も簡略化される等の利点がある。
As explained above, the present invention creates a missing part that serves as a mark to clearly indicate the connection point between the element fixing area and a specific terminal of the metallized layer that becomes the inner lead part when forming the element fixing area and the conductive layer. Since the semiconductor container is formed by simultaneously forming the semiconductor container, it is possible to easily identify the connection point between the element fixing region and the specific terminal of the metallized layer. Further, there are advantages such as fewer printing masks are needed to form a predetermined metallized layer, and the process is therefore simplified.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の半導体容器を構成する3枚のセ
ラミツク基板の平面図、第2図は第1図のセラミ
ツク基板を積層したときの素子固着領域と金属化
層の特定端子との接続方法を示す部分拡大斜視
図、第3図a,bは従来の素子固着領域と金属化
層の特定端子との接続個所を表示するための目印
の配置を説明するための図、第4図はこの発明の
一実施例を示す平面図、第5図はこの発明の欠落
部を形成する際に用いられる印刷マスクの平面図
である。 図中、1A,1B,1Cはセラミツク基板、2
は素子固着領域、3は金属化層、4,6は開口
部、5は封止帯、9は導電層、14は欠落部であ
る。なお、図中の同一符号は同一または相当部分
を示す。
Fig. 1 is a plan view of three ceramic substrates constituting a conventional semiconductor container, and Fig. 2 shows a method of connecting the device fixing region and specific terminals of the metallized layer when the ceramic substrates of Fig. 1 are stacked. FIGS. 3a and 3b are diagrams for explaining the arrangement of marks for indicating the connection points between the conventional element fixing region and a specific terminal of the metallized layer, and FIG. 4 is a partially enlarged perspective view of the present invention. FIG. 5 is a plan view of a printing mask used in forming the missing portion of the present invention. In the figure, 1A, 1B, 1C are ceramic substrates, 2
3 is an element fixing region, 3 is a metallized layer, 4 and 6 are openings, 5 is a sealing band, 9 is a conductive layer, and 14 is a missing portion. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] 1 絶縁板表面を金属化して形成された素子固着
領域およびこの素子固着領域から絶縁板表面端部
まで導出された導電層とを有し、この素子固着領
域と導電層との接合部近傍における素子固着領域
内に金属の欠落部を有した第1の基板、この第1
の基板表面に積層され、上記素子固着領域に対向
する部位に上記素子固着領域の少なくとも一部お
よび欠落部が露出される開口部を有し、絶縁板表
面における上記欠落部対向位置に一端が配設さ
れ、上記導電層と電気的に接続されるリード層が
金属化して形成された第2の基板を備えた半導体
容器。
1 An element fixing region formed by metallizing the surface of an insulating plate and a conductive layer led out from this element fixing region to an end of the surface of the insulating plate, and an element in the vicinity of the joint between the element fixing region and the conductive layer. a first substrate having a missing portion of metal in the bonded region;
is laminated on the surface of the substrate, has an opening through which at least a part of the element fixing area and the missing part are exposed at a portion facing the element fixing area, and has one end disposed at a position facing the missing part on the surface of the insulating plate. A semiconductor container comprising a second substrate formed by metallizing a lead layer provided thereon and electrically connected to the conductive layer.
JP9241478A 1978-07-27 1978-07-27 Semiconductor container Granted JPS5519837A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9241478A JPS5519837A (en) 1978-07-27 1978-07-27 Semiconductor container

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9241478A JPS5519837A (en) 1978-07-27 1978-07-27 Semiconductor container

Publications (2)

Publication Number Publication Date
JPS5519837A JPS5519837A (en) 1980-02-12
JPS6246983B2 true JPS6246983B2 (en) 1987-10-06

Family

ID=14053747

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9241478A Granted JPS5519837A (en) 1978-07-27 1978-07-27 Semiconductor container

Country Status (1)

Country Link
JP (1) JPS5519837A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6243154A (en) * 1985-08-20 1987-02-25 Sanyo Electric Co Ltd Semiconductor device
JPH0618227B2 (en) * 1987-05-25 1994-03-09 東京エレクトロン株式会社 Wafer prober

Also Published As

Publication number Publication date
JPS5519837A (en) 1980-02-12

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