JPS6245707B2 - - Google Patents
Info
- Publication number
- JPS6245707B2 JPS6245707B2 JP57202151A JP20215182A JPS6245707B2 JP S6245707 B2 JPS6245707 B2 JP S6245707B2 JP 57202151 A JP57202151 A JP 57202151A JP 20215182 A JP20215182 A JP 20215182A JP S6245707 B2 JPS6245707 B2 JP S6245707B2
- Authority
- JP
- Japan
- Prior art keywords
- potential
- electrode
- base region
- radiation
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000005855 radiation Effects 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 8
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims 1
- 238000005215 recombination Methods 0.000 description 5
- 230000006798 recombination Effects 0.000 description 5
- 239000000969 carrier Substances 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 230000005865 ionizing radiation Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 238000011109 contamination Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は集積注入型論理回路（IIL………
Integrated Injection Logic）を構成する半導体
集積回路装置に係わり、とくにγ線、電子線など
の電離性放射線照射に対して特性劣化を少なくす
るための手段を有するものに関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an integrated injection logic circuit (IIL).
The present invention relates to a semiconductor integrated circuit device constituting an integrated injection logic (Injection Logic), and particularly to one having means for reducing characteristic deterioration due to irradiation with ionizing radiation such as gamma rays and electron beams.
バイポーラ型半導体集積回路装置、とくに第１
図に示すようなIIL（Integrated Injection
Logic）素子において、電離性放射線１００が照
射された場合、酸化膜１中に正電荷５０、界面７
にアクセプタ型の表面準位が形成される。このた
め、表面再結合速度が増加して、ｎ型層２をコレ
クタ、ｐ型層３をベース、n+型層４をエミツタ
とするnpnトランジスタもしくはｎ型層２をベー
スとする横方向pnpトランジスタなどの各トラン
ジスタの電流利得βが低電流部で著しく低下す
る。第２図は横方向pnpトランジスタの電流利得
βの特性変化の例を示すもので、２００は照射
前、３００は照射後を示す。このような電流利得
βの低下のため、従来の構造では照射量が
103Rad以下でも回路動作不良を起こした。
Bipolar semiconductor integrated circuit devices, especially the first
IIL (Integrated Injection) as shown in the figure
Logic) element, when irradiated with ionizing radiation 100, positive charges 50 are generated in the oxide film 1, and an interface 7
Acceptor type surface states are formed in Therefore, the surface recombination speed increases, and an npn transistor with the n-type layer 2 as the collector, the p-type layer 3 as the base, and the n + type layer 4 as the emitter or a lateral pnp transistor with the n-type layer 2 as the base The current gain β of each transistor decreases significantly in the low current section. FIG. 2 shows an example of the characteristic change of the current gain β of a lateral pnp transistor, with 200 showing before irradiation and 300 after irradiation. Due to this reduction in current gain β, the irradiation amount is reduced in the conventional structure.
Even below 10 3 Rad, circuit malfunction occurred.
本発明の目的は、かかる従来の欠点を改良し、
放照線耐量の大きいバイポーラ型半導体集積回路
装置を提供することにある。
The purpose of the present invention is to improve such conventional drawbacks,
An object of the present invention is to provide a bipolar semiconductor integrated circuit device having a large radiation resistance.
低電流部での電流利得の低下は表面再結合速度
が大きく、注入された少数キヤリヤ成分が表面に
達したとき、再結合してベース電流成分を増大さ
せることに起因している。したがつて、本発明で
は半導体装置のシリコン層上部の酸化膜の上に電
極を形成し、前記シリコン層の表面に多数キヤリ
ヤ蓄積層ができるだけの電圧この電極に印加する
構成とした。これにより表面部に少数キヤリヤが
到達しにくい構造となり再結合電流成分を減少さ
せることができ、等価的にベース電流成分を小さ
くできる。これにより電流利得の低下を防止する
ことができる。
The decrease in current gain in the low current section is due to the high surface recombination rate, and when the injected minority carrier components reach the surface, they recombine and increase the base current component. Therefore, in the present invention, an electrode is formed on the oxide film on the silicon layer of the semiconductor device, and a voltage sufficient to form a multi-carrier accumulation layer on the surface of the silicon layer is applied to this electrode. This creates a structure in which minority carriers are less likely to reach the surface portion, making it possible to reduce the recombination current component and equivalently reduce the base current component. This can prevent a decrease in current gain.
第３図において、ｎ型エピタキシヤル層２の上
の酸化膜１の上にAI電極８が、ｐ型層３の上の
酸化膜１１の上にAl電極９が、それぞれ形成さ
れているのが本実施例の特徴である。形成方法
は、Al蒸着、エツチングなど通常の集積回路の
形成手段を用いて容易に構成される。ｎ型層２の
上の酸化膜１の上のAl電極８には電子蓄積層１
２が出来る程度にする。実際には＋５ボルト以上
が好ましい。また正の電圧を印加ｐ型層３の上の
酸化膜１１の上のAI電極９には正孔蓄積層１３
が出来る程度に負の電圧（−５〜−10V）を印加
しておく。実際には−５ボルト以下が好ましい。
In FIG. 3, an AI electrode 8 is formed on the oxide film 1 on the n-type epitaxial layer 2, and an Al electrode 9 is formed on the oxide film 11 on the p-type layer 3. This is a feature of this embodiment. The structure can be easily formed using ordinary integrated circuit forming methods such as Al vapor deposition and etching. An electron storage layer 1 is provided on the Al electrode 8 on the oxide film 1 on the n-type layer 2.
Make sure you can do 2. Actually, +5 volts or more is preferable. In addition, a positive voltage is applied to the hole accumulation layer 13 on the AI electrode 9 on the oxide film 11 on the p-type layer 3.
Apply a negative voltage (-5 to -10V) to the extent that this is possible. In reality, -5 volts or less is preferable.
ｐ型層３とｎ型層２が順方向にバイアスされた
場合の少数キヤリアとして正孔はｎ型層へ、電子
はｐ型層へ注入されるが、酸化膜１の直下のシリ
コン表面部へは電子蓄積層１２の存在のため逆電
界がかかり到達する少数キヤリヤは指数関数的に
抑制される。その結果、第４図に示したように、
電流利得βは照射前のコレクタ電流Ｉc依存性曲
線２００に比べて、照射後は３００の程度であ
り、低抵電流部でもほとんど低下しない。実施例
では酸化膜１と１１の厚さを50nｍ以上に選び、
105Rad以上の放射線耐量を得た。 When the p-type layer 3 and the n-type layer 2 are biased in the forward direction, holes are injected into the n-type layer and electrons are injected into the p-type layer as minority carriers, but they are injected into the silicon surface directly under the oxide film 1. Due to the presence of the electron storage layer 12, a reverse electric field is applied and the arriving minority carriers are suppressed exponentially. As a result, as shown in Figure 4,
The current gain β is about 300 after irradiation compared to the collector current I c dependence curve 200 before irradiation, and hardly decreases even in the low resistance current section. In the example, the thickness of oxide films 1 and 11 was selected to be 50 nm or more,
A radiation tolerance of 10 5 Rad or more was obtained.
本発明の第２の実施例を第５図に示す。表面再
結合電流の影響を特に受ける横型pnpトランジス
タのベース層となるｎ型層２の上方にのみAI電
極８を形成したものである。これにより、放射線
耐量を大幅に増加させることができる。 A second embodiment of the invention is shown in FIG. The AI electrode 8 is formed only above the n-type layer 2, which serves as the base layer of the lateral pnp transistor, which is particularly affected by surface recombination current. This allows the radiation tolerance to be significantly increased.
本発明の第３の実施例を第６図に示す。縦型
npnトランジスタのベース層となるｐ型層３の上
方にのみAl電極９を形成したものである。これ
によつても、放射線耐量を大幅に増加させること
ができる。 A third embodiment of the invention is shown in FIG. vertical
An Al electrode 9 is formed only above the p-type layer 3 which becomes the base layer of the npn transistor. This also allows the radiation tolerance to be increased significantly.
以上述べた如く、本発明によれば、電離放射線
照射によつて生じた表面準位に対し、少数キヤリ
ヤを表面部に到達させないようにして表面再結合
電流成分を抑制して、結果として耐放射線特性を
改善したものである。
As described above, according to the present invention, the surface recombination current component is suppressed by preventing minority carriers from reaching the surface of the surface states generated by ionizing radiation irradiation, and as a result, radiation resistance is achieved. It has improved characteristics.
このような構造にすることにより、表面部に生
じやすいプロセス上の汚染などに対しても強くな
り、耐放射線だけでなく製造歩留の向上にも役立
つ。従つて本発明は工業上有用な利益をもたらす
ものと考える。 By adopting such a structure, it becomes resistant to process-related contamination that tends to occur on the surface, and is useful not only for radiation resistance but also for improving manufacturing yield. Therefore, it is believed that the present invention provides useful industrial benefits.
第１図は従来のIIL素子の断面図、第２図は従
来のIIL素子のβ−Ｉc特性曲線、第３図は本発明
の第１の実施例IIL素子の断面図、第４図は本発
明の第１の実施例のβ−Ｉc特性曲線、第５図は
本発明の第２の実施例のIIL素子の断面図、第６
図は本発明の第３の実施例のIIL素子の断面図で
ある。
１……酸化膜、２……ｎ型エピタキシヤル層、
３……ｐ型層、４……n+型層、６……電極、７
……表面準位、８……Al電極、９……Al電極、
１１……酸化膜、５０……正電荷、１００……電
離性放射線、２００……照射前初期特性曲線、３
００……照射後特性曲線、β……電流利得、Ｉc
……コレクタ電流。
Figure 1 is a cross-sectional view of a conventional IIL element, Figure 2 is a β-I c characteristic curve of a conventional IIL element, Figure 3 is a cross-sectional view of an IIL element according to the first embodiment of the present invention, and Figure 4 is a cross-sectional view of a conventional IIL element. The β-I c characteristic curve of the first embodiment of the present invention, FIG. 5 is a cross-sectional view of the IIL element of the second embodiment of the present invention, and FIG.
The figure is a sectional view of an IIL element according to a third embodiment of the present invention. 1... Oxide film, 2... N-type epitaxial layer,
3...p type layer, 4...n + type layer, 6... electrode, 7
...Surface level, 8...Al electrode, 9...Al electrode,
11... Oxide film, 50... Positive charge, 100... Ionizing radiation, 200... Initial characteristic curve before irradiation, 3
00... Characteristic curve after irradiation, β... Current gain, I c
...Collector current.
Claims (1)
pnpトランジスタと、該横方向pnpトランジスタ
のベース領域と共通となり、接地電位とされるコ
レクタ領域、該横方向pnpトランジスタのコレク
タ領域と共通となるベース領域、及び該ベース領
域内に形成されるエミツタ領域から成るnpnトラ
ンジスタと、該pnpトランジスタのエミツタ領域
を電流注入部とするために該エミツタ領域に接続
され、正の第１の電位とされる第１の電極とを備
えた集積注入型論理回路において、該横方向pnp
トランジスタのベース領域上に絶縁膜を介して設
けられ、正の第２の電位とされる第２の電極、も
しくは該npnトランジスタのベース領域上に絶縁
膜を介して設けられ、負の第３の電位とされる第
３の電極のうち少なくとも一方を有することを特
徴とする耐放射線半導体集積回路装置。 ２ 前記第２の電位を＋５ボルト以上とする特許
請求の範囲第１項に記載の耐放射線半導体集積回
路装置。 ３ 前記第３の電位を−５ボルト以下とする特許
請求の範囲第１項に記載の耐放射線半導体集積回
路装置。[Claims] 1. Lateral direction provided in the surface area of the semiconductor substrate
A pnp transistor, a collector region that is common to the base region of the lateral pnp transistor and has a ground potential, a base region that is common to the collector region of the lateral pnp transistor, and an emitter region formed in the base region In an integrated injection logic circuit, the integrated injection logic circuit includes an npn transistor consisting of , the lateral pnp
A second electrode is provided on the base region of the transistor with an insulating film interposed therebetween and has a positive second potential, or a second electrode is provided on the base region of the npn transistor with an insulating film interposed therebetween and has a negative third potential. A radiation-resistant semiconductor integrated circuit device comprising at least one of the third electrodes set to a potential. 2. The radiation-resistant semiconductor integrated circuit device according to claim 1, wherein the second potential is +5 volts or more. 3. The radiation-resistant semiconductor integrated circuit device according to claim 1, wherein the third potential is -5 volts or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57202151A JPS5992560A (en) | 1982-11-19 | 1982-11-19 | Semiconductor integrated circuit device resistant to radiation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57202151A JPS5992560A (en) | 1982-11-19 | 1982-11-19 | Semiconductor integrated circuit device resistant to radiation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5992560A JPS5992560A (en) | 1984-05-28 |
| JPS6245707B2 true JPS6245707B2 (en) | 1987-09-28 |
Family
ID=16452804
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57202151A Granted JPS5992560A (en) | 1982-11-19 | 1982-11-19 | Semiconductor integrated circuit device resistant to radiation |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5992560A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102110692A (en) * | 2011-01-24 | 2011-06-29 | 中国电子科技集团公司第五十八研究所 | Isolation structure of anti-radiation EEPROM (electrically erasable programmable read-only memory) array |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61253479A (en) * | 1985-05-02 | 1986-11-11 | Nippon Telegr & Teleph Corp <Ntt> | Selection of semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS501677A (en) * | 1973-05-07 | 1975-01-09 |
-
1982
- 1982-11-19 JP JP57202151A patent/JPS5992560A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS501677A (en) * | 1973-05-07 | 1975-01-09 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102110692A (en) * | 2011-01-24 | 2011-06-29 | 中国电子科技集团公司第五十八研究所 | Isolation structure of anti-radiation EEPROM (electrically erasable programmable read-only memory) array |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5992560A (en) | 1984-05-28 |
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