JPS6244861B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a novel method for manufacturing CMIS (CMOS).

FIG. 1 shows a cross-sectional view of a monolithic complementary MIS integrated circuit.

In the figure, 1 is an n-type substrate, 8 is a p-well layer, and 11
is a p-channel MIS transistor, 12 is an n-channel MIS transistor, 13 is a substrate electrode, and 14 is a p-channel MIS transistor.
This is the well electrode.

In this structure, an equivalent vertical transistor Tv (an npn transistor consisting of a substrate 1, a well layer 8, and the source of an MIS transistor 12) and an equivalent lateral transistor T _L are parasitic.
(a pnp transistor consisting of the drain of the MIS transistor 11, the substrate 1, and the well layer 8), which constitutes a parasitic thyristor circuit as shown inside the dashed line in FIG. Of these, the area within the dotted line is an equivalent circuit of the junction between the p-well layer 8 and the n-type substrate 1.
R _S is the resistance between the substrate electrode 13 and the base of T _L , R
_W is the resistance between the p-well electrode 14 and the base of T _V ;
I _RS is the current flowing through R _S , I _RW is the current flowing through R _W , the dotted line is the equivalent circuit of the junction between substrate 1 and P well 8, C _PS is the junction capacitance between P well and substrate, I _PP
is the current.

Under normal conditions, only the leakage current from the junction between the p-well and the substrate flows between V DD and V _SS , which is in a blocked state, but under the following four conditions 1 _, even a momentary level between V _DD and V _SS When an excessive voltage exceeding .

2 When a high positive or negative voltage that causes dielectric breakdown of the gate oxide film is applied to the input terminal.

3. When a potential higher than V _DD by a certain level or lower than V _SS by a certain level is applied to the output terminal.

4 When electron-hole pairs are generated in a semiconductor due to light, radiation, etc.

Any one of these is added, and the following three conditions 5: The emitter-base junctions of T _L and T _V are forward biased and in an activated state.

6. The product of h _FF of two transistors is greater than the value.

7. The current that the power supply can supply is greater than the holding current of the latchup.

When all of the above are satisfied, the equivalent thyristor formed by the two transistors is turned on due to the positive feedback effect in which _IRS in Fig. 2 supplies each other's base current, and the voltage between V _DD and V _SS is turned on. A large current flows, and once this state is reached, the parasitic thyristor consisting of the two transistors T _L and T _V remains in the ON state and remains constant even if the noise voltage, light irradiation, radiation, etc. that caused it are removed. Current continues to flow. This phenomenon is called latch-up in complementary MIS transistors. When latchup occurs, V _DD ~
This cannot be prevented unless the voltage between V _SS is made below the holding voltage of the latch-up or the current flowing between V _DD and V _SS is limited below the holding current of the latch-up. When this phenomenon occurs, not only is it impossible to control the ON or OFF state of the MIS transistor, but also the element often burns out due to excessive current flowing. The likelihood of latch-up occurring increases as devices become more integrated.

There are various ways to prevent latch-up.

The first conventional method is to increase the depth of the p-well to increase the base width of the equivalent vertical transistor T _V , and at the same time increase the width of the base of the equivalent vertical transistor T
This is a method of increasing the base width of the equivalent lateral transistor T _L by separating the MIS transistors. Since the h _FE of the transistor is a decreasing function of the base width, condition 6 above is no longer satisfied and latch-up is prevented. For example, in a certain shape of monolithic complementary MIS circuit, the p-well depth is 11μ.
If the distance between the m- and p-well edge and the p-channel MOS transistor is 100 μm, latch-up will not occur. However, when considering integrated circuits, this method significantly reduces the degree of integration of elements and is not practical.

A second conventional method is to diffuse gold to shorten the lifetime of the fractional carriers in the p-well, lowering the h _FE of the equivalent vertical transistor and making it impossible to satisfy condition 6 above.

However, this method has drawbacks such as gold diffusing extremely quickly in silicon, making it difficult to control the amount and depth, and forming interface states, which adversely affects device performance. .

An object of the present invention is to realize a complementary MIS integrated circuit that does not cause latch-up and has a high degree of integration.

According to the present invention, the above object is a step of forming a first opening by partially removing a mask film formed on the surface of a semiconductor substrate of one conductivity type; etching a portion of the substrate surface to form a hole whose side surface is substantially perpendicular to the substrate surface, and forming the mask film into an eaves shape; forming an insulating film on the inner surface of the hole; and using the mask film as a mask. forming a second opening by removing the insulating film at the bottom of the hole while leaving the insulating film at the side faces of the hole by dry etching, and forming a reflective conductive well layer from above the substrate in the second opening. A method for manufacturing a complementary MIS transistor, comprising the steps of epitaxial growth, forming an MIS transistor of one conductivity type in the well layer, and forming an MIS transistor of the opposite conductivity type in the semiconductor substrate. This is achieved by

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is an element cross-sectional view of a complementary MIS transistor according to the present invention. In this embodiment, in addition to the barrier made of the insulator of the present invention, a buried layer doped with impurities at a high concentration is provided at the bottom of the well layer. 21
is an n-type silicon substrate, 22 is a p+ type buried layer, 28
is a p-well, 27 is an oxide film which is an insulating barrier, 31 is a p-channel MIS transistor, 32
is an n-channel MIS transistor. The buried layer 22 is a heavily doped p-type region, and is used as a base layer in a vertical npn transistor.
By increasing the Gummel number and generating a pullback electric field in the base, it serves to significantly reduce the h _FE of the vertical transistor. still,
Regarding the embedding layer, DBEstreich and A.Cchoa
Jr., “An Analysis of Lotch-Up Prevention
CMOS ICs Using an Epitasirl−Buriecl Layer
Process”, International Electron Devcie
Meeting, Washington DC1978. The oxide film No. 27 serves to increase the base length of the lateral PNP transistor, thereby reducing the h _FE of the lateral transistor and increasing the integration density. The buried layer 22 and the oxide film 27 prevent the above-mentioned condition 6 from being satisfied and prevent latch-up. Of course, in order to completely prevent latch-up, the depth of the p-well 28 and the
Conditions are also required for the depth and concentration distribution of the buried layer 22.

A method of manufacturing a complementary MIS integrated circuit according to an embodiment of the present invention will be explained with reference to FIG.

(1) After covering the surface of the n-type silicon substrate 21 with a thin base oxide film 25, a silicon nitride film 26 is selectively formed in the region where the complementary MIS transistor is to be formed, and the silicon nitride film 26 is made oxidation-resistant. Selective oxidation is performed as a mask to form a field oxide film 27. Next, a portion of the silicon nitride film 26 and base oxide film 25 are removed, and the remaining silicon nitride film 26 is removed.
Dry etching is performed using the base oxide film 25 as a mask to form a vertical hole 23. Next, etching is performed using isotropic hydrogen chloride gas to remove the silicon at the bottom of the hole damaged by the first dry etching. Next, boron ions are implanted to create an implant area for the buried layer.

(2) The entire surface is thermally oxidized, and the bottom and sides of the hole are coated with a thickness of 2000Å.
An oxide film 28 having a certain thickness is formed, and the oxide film at the bottom of the hole is removed by reactive ion etching, and then the silicon nitride film 26 is removed.

(3) Epitaxially grow P-type silicon over the entire surface until the holes 23 are completely filled. Silicon 29 is epitaxially grown in the hole 29 starting from the buried layer, and polycrystalline silicon 30 is grown on the base oxide film and the field oxide film.

(4) Low viscosity photoresist on the entire surface (not shown)
When this is applied, a photoresist layer that is thicker in the hole 31 area than in other areas is formed.

Next, the whole is incinerated so that only the photoresistor remains at the hole 31. Next, using the photoresist remaining in the hole 31 as a mask, the silicon is etched to remove the polycrystalline silicon 30 on the base oxide film 25. Finally, the base oxide film 25 is removed. In addition, since polycrystalline silicon grown from the sidewall may exist near the sidewall of the hole 29, it may be necessary to make it into a single crystal by laser annealing.

Next, N-channel and P-channel gate electrodes, source, and drain regions and electrodes are formed by a normal complementary MIS transistor manufacturing method,
form integrated circuits;

According to the present invention, a complementary MIS integrated circuit with a high degree of integration and less latch-up is realized.

[Brief explanation of the drawing]

1 is a cross-sectional view of a conventional monolithic complementary MIS circuit, FIG. 2 is an equivalent circuit diagram thereof, FIG. 3 is a cross-sectional view of a complementary MIS circuit according to the present invention, and FIG. 4 is a cross-sectional view of a complementary MIS circuit according to the present invention. FIG. 3 is a cross-sectional view of an element showing a manufacturing procedure of a manufacturing method. In these figures, 21 is an n-type silicon substrate,
22 is a buried layer, 27 is an insulating film, 28 is a p-well, 31 is a p-channel MIS transistor, and 32 is an n-channel MIS transistor.

Claims (1)

[Claims] 1. A step of partially removing a mask film formed on the surface of a semiconductor substrate of one conductivity type to form a first opening, using the mask film as a mask to form a first opening portion. Etching the surface of the substrate to form a hole whose side surfaces are substantially perpendicular to the surface of the substrate, and forming the mask film into an eaves shape; forming an insulating film on the inner surface of the hole, and etching using the mask film as a mask. forming a second opening by removing the insulating film at the bottom while leaving the insulating film at the side faces of the hole; epitaxially growing a reflective conductivity type well layer on the substrate in the second opening; step, a MIS transistor of one conductivity type is placed in the well layer,
A method for manufacturing a complementary MIS transistor, comprising the step of forming MIS transistors of opposite conductivity types on the semiconductor substrate.