JPS6243341B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and in particular, in a MOS type semiconductor device, high density,
By increasing the speed and making the surface flat,
The purpose is to reduce power consumption and improve yield.

Recently, semiconductor devices, especially those shown in Fig.
MOS type semiconductor devices have become finer, faster, and more dense.

In the MOS type FET shown in FIG. 1, 1 is a silicon substrate, 2 is polycrystalline silicon for gate, 3 is a wiring layer, 4 is a source region, 5 is a drain region, 6 is a silicon oxide film, and 7 is an Al It is an electrode.

In such conventional MOS FETs, when the size standard becomes about 2 μm, the wiring resistance becomes large, and the wiring resistance has a large effect on the speed of the element.
It is necessary to lower the wiring resistance, and possible methods include (1) increasing the thickness of the polycrystalline silicon film, (2) increasing the amount of impurities, and (3) using metal for the wiring layer. When forming the wiring layer 3 of the polycrystalline silicon film shown in FIG. 1 in the method (1) above, a dry etching method (for example, reactive sputter etching) is used as a method for etching a fine pattern. There is. A feature of the dry etching method is that the amount of intrusion in the lateral direction, so-called side etching, is extremely small, but the drawback is that the side surfaces of the pattern become sharp, so the thicker the film, the more difficult it will be to process later. When a film is formed, step breakage tends to occur at abrupt step portions of the film. Next, in method (2), there is a solid solubility limit for impurities in the polycrystalline silicon film.
And when implanting impurities by ion implantation method,
The larger the amount of injection, the longer the time. Furthermore, the temperature of the substrate during ion implantation becomes high, which may cause cracks or pattern deformation in the photosensitive resin commonly used as an ion implantation mask, leading to process defects. Next, in method (3), the number of wiring masks increases by one at the bottom, which causes problems such as an increase in the number of steps and poor workability.

Furthermore, when forming an opening in the silicon oxide film 6 on the polycrystalline silicon 2 for the gate shown in FIG. 1, if the opening becomes large or the position of the opening is shifted, and silicon substrate 1
A part of the source region 4 or the drain region 5 on the surface is exposed, and when the Al electrode 7 is formed later, a short will be formed between the gate portion and the source or drain. Therefore, method (1) is often used, but in this case, as mentioned earlier,
There is a risk of breakage in the Al wiring, and countermeasures must be taken to prevent this. The present invention provides a method for dealing with this problem.

In order to eliminate the above-mentioned drawbacks of the conventional technology, the present invention is a self-contained device that can be manufactured easily even when semiconductor devices are miniaturized.
It uses an aligned embedding method,
An embodiment of the present invention will be described below as an N-channel MOS FET.
The manufacturing method will be explained in detail based on FIGS. 2a to 2h showing the manufacturing method.

In FIG. 2a, the P-type silicon substrate 11 is selectively oxidized so that the field oxide film 12 has a substantially flat surface, for example, the P-type silicon substrate 11 is slightly etched before oxidation. , and then oxidizes to raise the surface and flatten the substrate surface (this step is not shown). After that, the n-type impurity layer 13 is ion-implanted at, for example, 10 ¹¹ to 10 ¹² cm ^-2 and several tens of KV.
It is selectively formed near the surface layer of the active region. Next, as shown in FIG. 2b, a silicon oxide film 14 is formed to a thickness of 3,000 to 8,000 Å by vapor phase growth or the like.
In this case, the thicker the silicon oxide film 14 is, the more
The next step, embedding with photosensitive resin, becomes easier. Next, in FIG. 2c, an opening 15 which will become a gate region is formed to a thickness of about 2 μm. Next, it is oxidized in water vapor at 900° C. for about 15 minutes to form a gate oxide film 16 on the surface of the silicon substrate in the opening 15 to a thickness of about 500 Å. Next, since the surface of the silicon substrate directly under the gate oxide film 16 is n-type and is a depletion type, when making a part of the enhancement type, P-type impurities are added to the gate oxide film at several tens of kilovolts to 10 ¹¹ to 10 ¹³ cm ^-2. Ions are implanted directly under 16 and inverted to P type. The drawing shows a region into which P-type ions have been implanted (the n-type region is shown separated).

Next, in FIG. 2d, the silicon oxide film 14 is etched to form openings 17 and 18 that will become source and drain regions. At the same time, openings 19 in the wiring layer region are also formed.

Next, as shown in FIG. 2e, polycrystalline silicon 20 is formed by vapor phase growth or the like to have approximately the same thickness as silicon oxide film 14. In this case, an n-type impurity, for example, phosphorus, is simultaneously diffused or introduced by ion implantation, etc., and after heat treatment, the source region 17'
Then, a direct contact region with the P-type silicon substrate 11, which will become the drain region 18', is formed.

Next, in FIG. 2f, a negative type photoresist 21 having a low viscosity is coated on the polycrystalline silicon film 20, and is formed thickly in the concave portions of the polycrystalline silicon 20 and thinly in the convex portions. In this case, for example, a step with a viscosity of 10cst
When the thickness is 5000 Å, the thickness is less than 100 Å on the convex portions having a width of about 2 μm, and the conditions are obtained such that the concave portions are completely filled. Next, apply a thin negative photoresist 2 on this convex part.
1 was removed by oxygen plasma etching,
The polycrystalline silicon film 20 in the convex portion is exposed. Next, by plasma etching using Freon gas,
The polycrystalline silicon film 20 is etched using the negative photoresist 21 in the recessed portion as a mask until the surface of the silicon oxide film 14 is exposed.
Next, when the negative photoresist 21 is removed, the polycrystalline silicon electrodes 17'', 15', and 18'' of the source, gate, and drain regions of polycrystalline silicon are filled in the openings of the silicon oxide film 14, which has a substantially flat surface. It has a built-in shape. Next, silicon oxide film 2 is applied to the entire surface.
2 is formed by a vapor phase growth method or the like. This is shown in Figure 2g.

Next, in FIG. 2h, the silicon oxide film 22 is selectively etched, openings are formed on each polycrystalline silicon electrode, Al 23 is formed by sputter deposition, etc., and wiring processing is performed. , MOS type
Complete FET.

By using the present invention described above, the following effects can be obtained.

(1) It is very easy to miniaturize, and it is easy to achieve high speed and high density.

(2) Since a resist embedding method is used, the finer the resist, the easier it is to embed, and the easier it is to flatten the surface. This contributes to prevention of stage breakage, improves yield, and is industrially useful.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view of a conventional MOS FET, and Fig. 2 a to h are diagrams for explaining an embodiment of the present invention.
FIG. 3 is a cross-sectional view of a process showing a method for manufacturing a MOS FET. 11...Semiconductor substrate (P-type silicon substrate), 1
2...first insulating film (field oxide film), 13
...Conductive impurity (n-type impurity layer), 14... Second insulating film (silicon oxide film), 15... Second opening (opening), 16... Third insulating film (gate oxide) film), 17, 18, 19... third opening (opening), 20... conductive material (polycrystalline silicon), 22... fourth insulating film (silicon oxide film),
23...Wiring pattern (Al).

Claims (1)

[Claims] 1. A step of forming a first opening to become an active region in a first insulating film provided on a surface of a semiconductor substrate, and selectively introducing a first conductive impurity into the first opening; forming a second insulating film on the surface of the semiconductor substrate and forming a second opening to serve as a gate region in the insulating film; forming a third gate insulating film in the second opening; introducing a second conductive impurity opposite to the first conductive impurity;
forming third openings to serve as source and drain regions in the second insulating film, and forming a conductive material on the surface of the semiconductor substrate to have approximately the same thickness as the second insulating film; a step of selectively leaving the conductive material to serve as source, gate and drain electrodes in the recesses of the openings formed in the second insulating film; forming a fourth insulating film on the surface of the semiconductor substrate; and forming a fourth insulating film on the surface of the semiconductor substrate; Manufacturing a semiconductor device comprising the steps of forming a fourth opening on the source, gate, and drain electrodes, and forming a metal thin film in the fourth opening to form a wiring pattern. Method.