JPS6236848A - Internal power source voltage generating circuit of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a circuit having a low power consumption and a low output impedance by composing of the first and second reference voltage generating circuits, and output stages of N-channel and P-channel MOS transistors controlled by the outputs of the generators. CONSTITUTION:When an external power source is Vcc and the threshold value of a P-channel MOS transistor Q6 is V THP, a voltage of 1/2Vcc-¦V THP¦ is applied to the gate of the transistor Q6 which forms an internal power source output stage 7, and the transistor Q6 generates a voltage higher by ¦V THP¦ from the gate applying voltage. In other words, Vo=1/2Vcc-¦V THP¦+¦V THP¦=1/2Vcc is satisfied, and a current flowing to a ground terminal from the Vcc becomes zero in the stage 7. In the reference voltage generating circuits 3 and 6, a current flowing to the ground terminal from the Vcc can be extremely reduced by increasing the values of R1, R2, R4 and R5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit for generating an internal power supply voltage on a chip based on an external power supply in a semiconductor integrated circuit.

(Prior Art) Fig. 3 shows a conventional circuit for generating an internal power supply voltage using resistance division. The end is connected to node N8. 9 is a resistor having a resistance value R9, one end is connected to node N8, and the other end is connected to the ground terminal. Vl which is the output of node N8
, and use this as the internal supply voltage. For simplicity, if we assume R8-R9, then in ■1, V l =
A voltage of -Vcc is generated.

[Problem that the invention seeks to solve]

In the conventional internal power supply voltage generating circuit, a current always flows from the external power supply Vcc to the ground terminal via the resistors 8 and 9, which has the drawback of increasing power consumption. Furthermore, if the resistance values R8 and R9 of the resistors 8 and 9 are increased in an attempt to reduce this power consumption, the output impedance of the node N8 increases and there is a drawback that a large current cannot be extracted from the node N8.

The present invention was made in order to solve the above-mentioned problems, and an object of the present invention is to obtain a circuit that can generate an internal power supply voltage with low power consumption and low output impedance.

[Means for solving problems]

The internal power supply voltage generation circuit according to the present invention has a first reference voltage that generates a voltage that is level-shifted with respect to a first reference voltage. It is composed of a second reference voltage generation circuit and an output stage consisting of an N-channel MOS transistor and a P-channel MOS transistor controlled by their respective outputs.

[Effect]

In the internal power supply voltage generating circuit according to the present invention, the first. The second reference voltage generation circuit suppresses the steady current to a low level, and when the output from the output stage deviates from the predetermined internal power supply voltage, one of the N and P channel MOS transistors in the output stage becomes conductive and the other becomes non-conductive. Since it becomes conductive and works to return the output to a predetermined value, the output impedance is low and the extracted power can be increased.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

This invention is a C-MO3 using both an N-channel MOS transistor and a P-channel MOS transistor.
Since this is often applied to circuits, this will be used in the following explanation. FIG. 1 shows an internal power supply voltage generation circuit for a semiconductor integrated circuit according to an embodiment of the present invention. In the figure, 3 is a first reference voltage generation circuit, resistors 1 and 2, and N
It is composed of channel MOS transistors Q1 and Q2.

1 is a resistor having a resistance value R1, one end of which is connected to CC, and the other end of which is connected to node N1.

Ql is an N-channel MOS transistor, its gate and drain are connected to node Nl, and its source is connected to node Nl.
Connected to 2. Q2 is an N-channel MOS transistor whose gate and drain are connected to node N2, and whose source is NO1! Connected to N3. 2 is a resistor having a resistance value R2, one end is connected to the node N3,
The other end is connected to the ground terminal.

Reference numeral 6 denotes a second reference voltage generation circuit, which is composed of resistors 4 and 5 and P-channel MOS transistors Q3 and 04.

4 is a resistor having a resistance value R4, one end of which is connected to Vcc, and the other end connected to node N4.

Q3 is a P-channel MOS transistor, its drain is connected to node N4, and its gate and source are connected to node N4.
5. Q4 is a P-channel MOS transistor, and its drain is connected to node N5, and its gate and source are connected to node N6. 5 is a resistor having a resistance value R5, one end of which is connected to the node N6, and the other end of which is connected to the ground terminal.

Reference numeral 7 denotes an internal power supply voltage output stage, which is composed of an N-channel MOS transistor Q5 and a P-channel Mo5t transistor Q6. Q5 is an N-channel MOS transistor whose gate is connected to node N1, drain is connected to Vcc, and source is connected to node N7.Q6 is a P-channel MOS transistor whose gate is connected to node N1. N6, its drain is connected to node N7, and its source is connected to the ground terminal.

The circuit that generates the internal power supply voltage configured as described above operates as follows.

In the first reference voltage generation circuit 3, if R1=R2 and L-transistors having the same characteristics are used as the N-channel MOS transistors Q1 and 02, the potential of the node N2 becomes 1/2 Vcc. If the values of R1 and R2 are increased so that a small amount of current flows between Vcc and the ground terminal, node N1 will have the dark value voltage V of the N-channel MO31 transistor with respect to node N2.
A voltage higher by THN is generated. That is, node N
1, a potential of 1/2 V c c +VTHN is generated.

In the second reference voltage generation circuit 6, if R4=R5 and transistors having the same characteristics are used for the P-channel Mo3t transistors Q3 and Q4, the potential of the node N5 becomes 1/2vCC. If the values of R4 and R5 are increased so that a small amount of current flows between Vcc and the ground terminal, a voltage lower than node N5 by the dark value voltage IVTHPI of the P-channel MOS transistor is generated at node N6. . That is, node N6 has 1
A voltage of /2Vcc-IVTHPl is generated.

A voltage of 1/2Vcc+VTtlN is applied to the gate of the N-channel MOS transistor Q5 constituting the internal power supply voltage output stage 7 connected to the node N1. Since transistor Q5 operates in the pentode region, its source, node N7, is connected to V from the gate voltage.
T) A voltage lower by IN is generated. In other words, it becomes.

On the other hand, the P channel M constituting the internal power supply voltage output stage 7
Since the node N6 is connected to the gate of the OS transistor Q6, 1/2 V cc -1vTI
■PI voltage is applied. Since the transistor Q6 also operates in the pentode region, a voltage higher than the gate applied voltage by IVTIIPl is generated at its drain, the node N7. That is, vo =1. /2Vc
C= l VTHP l +l VTHP l-1/
2Vcc, which is exactly the same value as the VQO value obtained from the N-channel Mo3t transistor 5, and it can be seen that there is no contradiction.

In the state of VO=1/2Vcc, transistor Q5 also has Q
6 is also in the last possible state between the conductive state and the non-conductive state, and in the internal power supply voltage output stage 7, the current flowing from VCC to the ground terminal is zero. Reference voltage generation circuit 3
In and 6, the current flowing from cc to the ground terminal can be made extremely small by increasing the values of R1, R2, R4, and R5, and a circuit that generates an internal power supply voltage with low power consumption can be realized.

-Here, assume that vO is deviated from 1/2Vcc. When the value of vO becomes higher than 1/2 Vcc, the drain of P-channel MOS transistor Q6
The voltage between the sources increases, Q6 becomes conductive, and
It works to return vo to 1/2 Vcc. During this time, the voltage between the drain and source of N-channel MOS transistor Q'-5 becomes small, so Q5 remains non-conductive, and the current flowing from Vcc to the ground terminal via Q5 and Q6 is zero. Conversely, the VQO value is l/2
When the voltage becomes lower than Vc, c, the voltage between the drain and source of Q5 increases, so N-channel MOS transistor Q5 becomes conductive and VO is reduced to 1/2 Vc.
It works to return to c. During this time, the drain-source voltage of P-channel MOS transistor Q6 becomes small, so Q6 remains non-conductive, and the current flowing from Vcc to the ground terminal via Q5O and Q6 is zero. In this way, when ■0 deviates from 1/2 Vcc, Q5 or Q6 immediately becomes conductive and works to return ■0 to 1/2 Vcc, so the output impedance is sufficiently low. Obtainable.

Furthermore, according to this embodiment, as explained above, a desired internal power supply voltage can be obtained that is independent of the dark value voltage of the N-channel MOS transistor and the P-channel MOS transistor that constitute the circuit.

FIG. 2 shows another embodiment of the present invention, in which 01 to Q6 are the same as in FIG. The four transistors 07 to QIO serve as resistors, Ql and Q8 are N-channel MOS transistors corresponding to resistors 1 and 2 shown in Figure 1, and their drains and gates are connected to each other. has been done. Q9 and QIO are P-channel MOS transistors corresponding to resistors 4 and 5 shown in FIG. 1, and their gates and sources are connected to each other, and the operation of the circuit shown in FIG. 2 is completely the same as that of the circuit shown in FIG. Same, N
If the channel MOS transistors Ql and 08 are configured with transistors with the same characteristics, and the P-channel MOS transistors Q9 and Q]O are configured with transistors with the same characteristics, the potentials of nodes N2 and N5 are respectively 1/2Vc c Therefore, the same effect as the circuit shown in FIG. 1 above can be expected.

Note that by combining several stages of the circuits shown in Figures 1 and 2 above, 1/4 Vcc, 3/4
The output of Vcc is further increased by 1/8 Vcc
, 3/8 Vcc.

It is also possible to obtain an output further divided into 7/8 Vcc.

Further, in the above embodiment, R1-R2, R4-'R5,
Furthermore, we have described the case where Ql and Q2 and Q3 and Q4 are respectively constructed of transistors with the same characteristics.
By changing the resistance distribution, it is also possible to arbitrarily control the output potential.

〔Effect of the invention〕

As described above, according to the present invention, the first. A circuit that generates a 1st and 2nd reference voltage whose level is shifted by the dark value voltage of the N and P channel MOS transistors with respect to the second reference voltage, and an N channel MOS transistor and a P channel that are controlled by these outputs. By combining this with an internal power supply voltage output stage consisting of MOS transistors, an internal power supply voltage generation circuit with low power consumption and low output impedance can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of one embodiment of the present invention, FIG. 2 is a circuit diagram of another embodiment of the invention, and FIG. 3 is a circuit diagram of a conventional device. In the figure, 1, 2, 4, 5, 8.9 are resistances, 3.6 is the first . 7 is an internal power supply voltage output stage, Ql, Q2 . Q5. Ql, Q8 are N channel MO
3I-transistor, Q3. Q4, Q6. Q9. QIO is a P-channel MOS transistor. Note that the same reference numerals in the figures indicate the same or equivalent parts. Figure 1

Claims (1)

[Claims] 1) In an internal power supply voltage generation circuit that generates an internal power supply voltage having a voltage value smaller than the absolute value of the external power supply based on an external power supply on a semiconductor integrated circuit, between the external power supply and ground. and first and second N-channel MOS transistors connected in series to the first reference voltage.
A first reference voltage generation circuit that outputs a voltage whose level is shifted by the threshold voltage of the transistor, and third and fourth resistance elements and third and fourth P channels connected in series between an external power supply and the ground. A P-channel MOS transistor is connected to the second reference voltage.
a second reference voltage generation circuit that outputs a voltage level-shifted by the threshold voltage of the transistor;
1. An internal power supply voltage generation circuit for a semiconductor integrated circuit, comprising an internal power supply voltage output stage consisting of N-channel and P-channel MOS transistors each controlled by the output of a reference voltage generation circuit. (2) The internal power supply voltage generation circuit for a semiconductor integrated circuit according to claim 1, wherein the first, second, third, and fourth resistance elements are made of resistors. (3) The first and second resistance elements are N-channel MOS transistors whose gates and drains are interconnected, and the third and fourth resistance elements are P-channel MOS transistors whose gates and sources are interconnected. An internal power supply voltage generation circuit for a semiconductor integrated circuit according to claim 1, characterized in that the circuit comprises: