JPH04301921A - Inverter circuit - Google Patents

Abstract

PURPOSE:To obtain an inverter circuit which can reduce energy consumption. CONSTITUTION:A Pch transistor 7 is connected between the source of a Pch transistor 5 and a power supply terminal 3. An Nch transistor 8 is connected between the source of a Pch transistor 6 and a GND terminal 4. A delay circuit 9 composed of a resistor 10 and a capacitor 11 is connected between the gate of the Pch transistor 7 and an input terminal 1 and between the gate of the Nch transistor 8 and the input terminal 1.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter circuit composed of MOS transistors and the like.

0002

2. Description of the Related Art FIG. 5 is a circuit diagram showing a conventional inverter circuit of this type. A P-channel MOS transistor (hereinafter referred to as Pch transistor) 5 has its source connected to the power supply terminal 3. An N-channel MOS transistor (hereinafter referred to as Nch transistor) 6 has its source connected to the GND terminal 4. The gates of the Pch transistor 5 and the Nch transistor 6 are commonly connected to the input terminal 1. Furthermore, the drains of the Pch transistor 5 and the Nch transistor 6 are commonly connected to the output terminal 2.

Next, the operation of the above-mentioned inverter circuit will be explained. First, when the input voltage of the input terminal 1 is at a low level, the Pch transistor 5 is in the ON state, and the N
ch transistor 6 is in an OFF state. Next, when the input voltage rises, the Nch transistor 6 turns on at the threshold voltage VTN, and the Pch transistor 5
is turned off at (VDD-|VTP|). however,
VDD is a power supply voltage, and VTP is a threshold voltage of the Pch transistor 5.

0004

However, the conventional inverter circuit described above is composed of a pair of Pch transistor 5 and Nch transistor 6, and when the input voltage is VTN~(VDD-|VTP|), Since the Pch transistor 5 and the Nch transistor 6 are turned on at the same time, there is a problem that the current consumption flowing between the power supply terminal 3 and the GND terminal 4 is large.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an inverter circuit that can reduce current consumption.

[0006]

[Means for Solving the Problems] An inverter circuit according to the present invention includes a first P-channel MOS transistor and a first N-channel MOS transistor, each having its gate connected to an input terminal and its drain connected to an output terminal. , a second P-channel MOS transistor connected between the source of the first P-channel MOS transistor and the power supply terminal, and a second P-channel MOS transistor connected between the source of the first N-channel MOS transistor and the ground terminal. between the second N-channel MOS transistor and the gate of the second P-channel MOS transistor and the input terminal;
It is characterized by comprising delay circuits connected between the gates of the N-channel MOS transistors and the input terminals, respectively.

[0007]

[Operation] In the present invention, the second P-channel MOS transistor is connected between the source of the first P-channel MOS transistor and the power supply terminal, and the first N-channel MOS transistor is connected between the source of the first P-channel MOS transistor and the power supply terminal.
A second N is connected between the source of the OS transistor and the ground terminal.
A channel MOS transistor is connected, and a delay circuit is connected between the gate of the second P-channel MOS transistor and the input terminal and between the source and the input terminal of the second N-channel MOS transistor. There is. Therefore, the second P-channel MOS transistor and the second N-channel MOS transistor are connected to the first P-channel MOS transistor, respectively.
Channel MOS transistor and first N-channel MO
It operates later than the S transistor. Therefore, the time during which all the transistors connected in series between the power supply terminal and the ground terminal are in the ON state can be shortened compared to the conventional method, thereby reducing the current consumption flowing between the power supply terminal and the ground terminal. be able to.

Each delay circuit can be configured as shown below. That is, a resistor is connected between the gate of the second P-channel MOS transistor or the gate of the second N-channel MOS transistor and the input terminal, respectively, and the gate of the second P-channel MOS transistor or the gate of the second N-channel MOS transistor is connected to the input terminal. A capacitor is connected between the gate of each of the second N-channel MOS transistors and the ground terminal. Thereby, the input voltage of the input terminal can be delayed based on the resistance value of the resistor and the capacitance of the capacitor. Further, instead of the resistor, a third P-channel MOS transistor and a third N-channel MOS transistor are connected between the gate of the second P-channel MOS transistor or the gate of the second N-channel MOS transistor and the input terminal, respectively. Channel MOS transistors are connected in parallel, and this third P
Channel MOS transistor and third N-channel MO
It is also possible to use the ON resistance of the S transistor. In this case, the formation area of the delay circuit can be reduced.

[0009]

Embodiments Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing an inverter circuit according to a first embodiment of the present invention. The Pch transistor 5 has its gate connected to the input terminal 1 and its drain connected to the output terminal 2, as in the conventional example. Pch transistor 7 is connected between the source of Pch transistor 5 and power supply terminal 3. Resistor 10 is Pc
h is connected between the gate of transistor 7 and input terminal 1. The capacitor 11 is connected between the gate of the Pch transistor 7 and the GND terminal 4. The resistor 10 and capacitor 11 constitute a delay circuit 9.

On the other hand, the Nch transistor 6 has its gate connected to the input terminal 1 and its drain connected to the output terminal 2, as in the conventional example. Nch transistor 8 is connected between the source of Nch transistor 6 and GND terminal 4. A delay circuit 9 consisting of a resistor 10 and a capacitor 11 is also connected between the gate of the Nch transistor 8 and the input terminal 1.

Next, the operation of the above-mentioned inverter circuit will be explained. First, when the input voltage of the input terminal 1 is at a low level, the Pch transistors 5 and 7 are in an ON state, and the Nch transistors 6 and 8 are in an OFF state. Next, when the input voltage increases, the Nch transistor 6 turns on at the threshold voltage VTN, but the Nch transistor 8 turns on later than the Nch transistor 6 because the delay circuit 9 is provided. On the other hand, Pc
The h transistor 5 turns off at (VDD-|VTP|), but the Pch transistor 7 turns off later than the Pch transistor 5 because it is provided with a delay circuit 9.
Becomes F state.

As described above, according to the present embodiment, the time during which all of the two pairs of transistors 5 to 8 connected in series between the power supply terminal 3 and the GND terminal 4 are in the ON state is different from that in the conventional example. Since the length can be shortened compared to the case of a pair of transistors 5 and 6, the current consumption flowing between the power supply terminal 3 and the GND terminal 4 can be reduced.

FIG. 2 is a circuit diagram showing an inverter circuit according to a second embodiment of the present invention. Note that this embodiment differs from the first embodiment in the configuration of the delay circuit.

The Pch transistor 5 has its gate connected to the input terminal 1 and its drain connected to the output terminal 2. Pch transistor 7 is connected between the source of Pch transistor 5 and power supply terminal 3. Pc
The h transistor 12 has its gate connected to the power supply terminal 3, its source connected to the input terminal 1, and its drain connected to the gate of the Pch transistor 7. N
The ch transistor 13 has its gate connected to the GND terminal 4, its source connected to the gate of the Pch transistor 7, and its drain connected to the input terminal 1. The capacitor 11 is connected to the gate of the Pch transistor 7 and the G
It is connected between the ND terminal 4 and the ND terminal 4. That is, the Pch transistor 12, the Nch transistor 13, and the capacitor 11 constitute a delay circuit 9a.

On the other hand, the Nch transistor 6 has its gate connected to the input terminal 1 and its drain connected to the output terminal 2. Nch transistor 8 is connected between the source of Nch transistor 6 and GND terminal 4. The Pch transistor 14 has its gate connected to the power supply terminal 3.
, its source is connected to the input terminal 1 , and its drain is connected to the gate of the Nch transistor 8 . The Nch transistor 15 has its gate connected to the GND terminal 4 , its source connected to the gate of the Nch transistor 8 , and its drain connected to the input terminal 1 . Capacitor 11 is connected between the gate of Nch transistor 8 and GND terminal 4. That is, P
The ch transistor 14, the Nch transistor 15, and the capacitor 11 constitute a delay circuit 9b.

In this embodiment, input terminal 1 and Pch
Delay circuit 9 connected between the gate of transistor 7
a delays the input voltage by the ON resistances of the transistors 12 and 13 and the capacitor 11. On the other hand, input terminal 1
A delay circuit 9b connected between the gate of the Nch transistor 8 and the gate of the Nch transistor 8 delays the input voltage by the ON resistances of the transistors 14 and 15 and the capacitor 11. Therefore, when the input voltage of the input terminal 1 rises from the Low level, the Nch transistor 8
Since the transistor turns on later than the Nch transistor 6, the current consumption flowing between the power supply terminal 3 and the GND terminal 4 can be reduced.

Furthermore, in this embodiment, the delay circuit 9a
, 9b uses the ON resistance of the transistor, so
The formation area of the delay circuit 9 can be made smaller than that of the delay circuit 9 in the first embodiment.

FIGS. 3 and 4 are graphs showing the results of simulations of the relationships among input voltage, output voltage, and current consumption in inverter circuits according to the second embodiment (see FIG. 2) and the conventional example (see FIG. 5), respectively. It is a diagram.

As is clear from FIGS. 3 and 4, according to the second embodiment, the current consumption at peak times can be reduced by about 25% compared to the conventional one.

[0021]

As explained above, according to the present invention, the first P-channel MOS constituting the conventional inverter circuit
A second P-channel MOS transistor and a second N-channel MOS transistor are connected in series to the transistor and the first N-channel MOS transistor, respectively, and a delay circuit connects the second P-channel MOS transistor and the second N-channel MOS transistor. Since the input voltage of the MOS transistor is delayed, the time required for all the transistors connected in series between the power supply terminal and the ground terminal to be in the ON state can be shortened compared to the conventional method. Therefore, the current consumption flowing between the power supply terminal and the ground terminal can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an inverter circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an inverter circuit according to a second embodiment of the present invention.

FIG. 3 is a graph diagram showing the results of simulating the relationship between input voltage, output voltage, and current consumption in an inverter circuit according to a second example.

FIG. 4 is a graph diagram showing the results of simulating the relationship between input voltage, output voltage, and current consumption in an inverter circuit according to a conventional example.

FIG. 5 is a circuit diagram showing a conventional inverter circuit.

[Explanation of symbols]

1; Input terminal 2; Output terminal 3; Power supply terminal 4; GND terminal 5, 7, 12, 14; Pch transistor 6, 8, 13
, 15; Nch transistors 9, 9a, 9b; delay circuit 10; resistor 11; capacitor

Claims (3)

[Claims] 1. A first P-channel MO whose gate is connected to an input terminal and whose drain is connected to an output terminal.
a second P-channel MOS transistor connected between an S transistor and a first N-channel MOS transistor, and a source of the first P-channel MOS transistor and a power supply terminal;
a second N-channel MOS transistor connected between the source of the first N-channel MOS transistor and the ground terminal;
a channel MOS transistor, and a delay circuit connected between the gate of the second P-channel MOS transistor and the input terminal and between the gate of the second N-channel MOS transistor and the input terminal, respectively. An inverter circuit characterized by: 2. Each of the delay circuits includes a resistor connected between the gate of the second P channel MOS transistor or the gate of the second N channel MOS transistor and the input terminal, and a resistor connected between the gate of the second P channel MOS transistor or the gate of the second N channel MOS transistor and the input terminal, and 2. The inverter circuit according to claim 1, further comprising a capacitor connected between the gate of the P-channel MOS transistor or the gate of the second N-channel MOS transistor and a ground terminal. 3. Each of the delay circuits includes a third P-channel MOS transistor connected in parallel between the gate of the second P-channel MOS transistor or the gate of the second N-channel MOS transistor and the input terminal. A transistor, a third N-channel MOS transistor, and a capacitor connected between the gate of the second P-channel MOS transistor or the gate of the second N-channel MOS transistor and a ground terminal, respectively. The inverter circuit according to claim 1.