JPS6234359Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory protection circuit, and more particularly to a circuit that protects the contents of a memory from write signals accidentally generated when power is turned on and off.

CMOS RAM (Complementary Metal Oxide)
Semiconductor Random Access Memory (Semiconductor Random Access Memory) has extremely low power consumption, so it can be used as non-volatile memory like core memory with battery backup even during power outages. When using CMOS RAM as non-volatile memory, the system power supply V
_cc is supplied to all of the CMOS RAM, CE (chip enable) supply circuit, control unit, peripheral circuits, etc., and when the system power supply V _cc is cut off, memory is supplied from battery BAT1 to the CMOS RAM and CE supply circuit. Provides the voltage necessary to retain content. That is, conventionally, as shown in Fig. 1, when the system power supply V _cc , V _cc +V _F is cut off, the CMOS RAM power is automatically switched to the battery BAT1.
At the same time, measures are taken to prevent the contents of the memory from being destroyed by memory write signals that occur accidentally when the system power is turned on and off.

To ensure that memory contents are retained when the system power is turned on and off, memory CE
By setting the (Chip-Enable) input to a low level when the system power is turned on and off to put the memory in an inactive state, write operations to the memory are prohibited.

In Figure 1, when the system power supply _Vcc is in a normal state, that is, when it exceeds the minimum voltage value, the Zener diode ZD1 turns on and applies a positive voltage above a certain level to the base of the NPN transistor Q1. Q1 turns on and inputs the low level collector potential to the two-input NOR gate N. In this case, when the value of is low, the output of NOR gate N is high, enabling a memory write operation. Also,
When the value of N is high, the output of NOR gate N is low, so the memory is inactive.

Now, when the system power supply V _cc is cut off for some reason or drops below the minimum voltage value, the zener diode ZD1 is turned off and the base of the NPN transistor Q1 is applied with approximately ground potential, so the transistor Q1 is It is turned off, and a high level collector potential is input to the NOR gate N. As a result, even if the value of is at a high level,
Even at a low level, the output of the NOR gate N goes low and the memory becomes inactive, so writing is inhibited.

Note that the voltage value V _F is the forward voltage of the diode _D1 , and when the system power supply V _cc is turned on, a voltage higher by V _F (V _cc + V _F ) power supply.

In this way, the conventional memory protection circuit shown in Figure 1 can prevent memory contents from being destroyed by suppressing unstable signals from the peripheral logic that can occur when the system power is turned on and off. , NPN transistor Q1, a plurality of elements are required to configure the two-input NOR gate N, and the number of circuit elements increases. Furthermore, current flows to the two-input NOR gate N, and leakage current also occurs through the transistor Q1, resulting in wasteful power consumption. When backing up a CMOS RAM using a battery, if the current consumption is large, the battery backup time will be shortened accordingly, so a circuit that consumes as little current as possible is desired.

The purpose of this invention is to respond to these conventional demands by using a circuit with a small number of circuit elements and low leakage current to invalidate accidental write signals that occur when the system power is turned on and off, and to protect the memory contents. The object of the present invention is to provide a memory protection circuit that can effectively maintain the memory.

The memory protection circuit of this invention consists of a PNP transistor that turns on when the power supply voltage exceeds the minimum operating voltage and uses the collector potential as a chip enable output.
The base of the PNP transistor and the power supply voltage are connected to one terminal of the PNP transistor through a resistor, and the chip enable input voltage is connected to the other terminal of the Zener diode.

Hereinafter, an embodiment of the present invention will be explained with reference to FIG.

As shown in Fig. 2, the present invention uses a switching circuit of PNP transistor Q2 and a Zener diode ZD2 to turn on transistor Q2 when the power supply voltage _Vcc exceeds the minimum voltage value. When the voltage value fluctuates greatly, the Zener diode ZD2 and transistor Q2 are both turned off to protect the memory contents from accidental memory write signals.

Resistor R10 and Zena diode ZD2
determines the minimum voltage value of the system power supply _Vcc , and when the system power supply _Vcc exceeds the minimum voltage value
The value of resistor R10 and Zener voltage are determined so that PNP transistor Q2 is turned on. In FIG. 2, the lowest voltage value of the system power supply _Vcc is set to 4.5V. Further, the resistor R11 is a protection resistor (current limiting resistor) for the Zener diode ZD2, and the resistor R12 determines the input level of the CMOS RAM.

In FIG. 2, when the system power supply V _cc is 4.5V or less, a positive potential above a certain value is not applied to the emitter of the PNP transistor Q2.
Regardless of the low level or high level of the signal,
Transistor Q2 is turned off, bringing its collector potential to approximately ground potential. Therefore, CMOS
The CE signal input to the RAM becomes low level, making the memory inactive. On the other hand, when the system power supply V _cc is 4.5V to 5.5V and the signal is low level, the Zener diode ZD2 turns on because it exceeds the Zener voltage, and an appropriate voltage is applied to the base of the PNP transistor Q2. , transistor Q2 is turned on and its collector potential becomes high level. Therefore,
The CE signal input to CMOS RAM goes high, making the memory active.

In this case, if the signal is determined to be high level when the system power supply V _cc exceeds 4.5V, the zener diode ZD2 is in the off state because the zener voltage is not reached, and the transistor Q
Since an appropriate voltage is not applied to the base of transistor Q2, transistor Q2 is turned off, bringing its collector potential to a low level. Therefore, the contents of memory are not destroyed. In addition, if the system logic circuit is designed for 4.5V to 5.5V, 4.5V
Of course, the signal can be reliably brought to a high level when .

Further, diode D2 in FIG. 2 prevents current from flowing from the system power supply (V _cc +V _F ) to the battery (BAT1), and diode D1 prevents current from flowing from the battery (BAT1) to the system power supply (V _cc +
This prevents current from flowing through V _F ).

In FIG. 2, as is clear from the comparison with the conventional circuit of FIG. 1, the number of elements is reduced because there is no need to provide a two-input NOR gate N. Furthermore, since the two-input NOR gate N is not provided and the circuit configuration is simplified, leakage current is low and wasteful power consumption is low. Therefore, CMOSRAM
Backup using batteries is effectively performed.

As explained above, according to the present invention, it is possible to protect the memory contents from accidental write signals that occur when the system power is turned on and off using a small number of elements, and since the leakage current is small, the battery backup time can be increased.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of a conventional memory protection circuit;
The figure is a block diagram of a memory protection circuit showing an embodiment of the present invention. N...2-input NOR gate, Q1, Q2...transistor, ZD1, ZD2...Zena diode, CE...chip enable signal, _Vcc ...
Power-supply voltage.

Claims (1)

[Scope of utility model registration request] A PNP type transistor that conducts when the power supply voltage exceeds a predetermined minimum voltage and supplies a chip enable output signal directly to the memory, and connects the base of the PNP type transistor and the above power supply voltage to one terminal through a resistor. and a chip enable input signal connected to the other terminal of the memory protection circuit.