KR100207824B1 - Backup battery circuit for extending backup time of memory - Google Patents

Abstract

end. TECHNICAL FIELD The present invention relates to a battery of a keyphone system, and more particularly, to a backup battery circuit for prolonging a backup time of data stored in a RAM memory of a keyphone system.

I. The technical problem to be solved by the present invention: Since a separate logic circuit for the chip select (chip select) of the RAM in the conventional circuit, the power of the backup battery in addition to the RAM as well as the logic for the separate chip select in the actual power failure It also solves the problem of consuming a large amount of current by supplying the circuit.

All. SUMMARY OF THE INVENTION The present invention is located in a load between a chip select terminal of an RAM memory and an external supply power line, and normally switches the external supply power by a signal output from the chip select signal generator to switch the RAM memory. The chip select signal is supplied to the chip select terminal of the chip selector, and the chip select signal control unit is configured to supply the power applied from the backup battery to the chip select signal of the chip select terminal of the RAM memory so that the RAM memory unit is not activated. It is characterized by.

la. Important use of the invention: Backup battery circuit for extending the backup time of the memory.

Description

Backup battery circuit to extend backup time of memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a battery of a key phone system, and more particularly, to a backup battery circuit for prolonging a backup time of data stored in a RAM memory in a key phone system.

In general, a memory is divided into a RAM capable of read / write and a ROM dedicated to read. Among them, the RAM is widely used when storing data of a user or storing data of a clock function in the key phone system. Since the RAM generally loses the stored data at the time of power failure, the RAM is connected to a backup battery to supply power to back up the stored data at the time of power failure.

However, the conventional circuit as described above uses a separate logic circuit for chip select of the RAM, so that in case of actual power failure, the backup battery power is supplied to the RAM as well as the logic circuit for a separate chip select. There was a problem that consumes a lot of current.

Accordingly, an object of the present invention is to provide a circuit for increasing the data backup time of a memory by reducing the current consumption of the backup battery used for data backup of the memory in a key failure.

According to an aspect of the present invention, a chip select signal generator for generating a chip select signal is provided to a chip select terminal of a RAM memory, and a backup current is provided to prevent loss of data stored in the RAM memory during a power failure. 1. A backup power supply circuit having a backup battery to be provided;

Located at the load between the chip select terminal of the RAM memory and the external power supply line, the external power supply is switched by a signal output from the chip select signal generator, and the chip select signal is transferred to the chip select terminal of the RAM memory. And a chip select signal control unit configured to supply power supplied from the backup battery to the chip select signal of the chip select terminal of the RAM memory during power failure so that the RAM memory unit is not activated.

1 is a backup battery circuit diagram for extending a backup time of a memory according to an exemplary embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. First, in adding reference numerals to the elements of the drawings, and in describing the present invention, if it is determined that the detailed description of the related known functions or configurations may unnecessarily obscure the gist of the present invention, the detailed description thereof will be described. Omit.

1 is a backup battery circuit diagram for extending a backup time of a memory according to an exemplary embodiment of the present invention. Referring to FIG. 1, the RAM memory 100 stores user data in a key phone system or data of a clock function. The RAM memory chip select signal generator 120 controls an external power supply Vcc by turning on or turning off a switching device NMOS type transistor 110 connected to a rear end thereof. The chip select signal of the RAM memory 100 is generated. The backup battery unit 130 supplies a backup current to the RAM memory 100 so as not to prevent loss of data stored in the RAM memory during a power failure, and simultaneously prevents the RAM memory 100 from being active. The high level current is supplied to the chip select terminal of the RAM memory 100. At this time, the backup battery 130 uses a nickel-cadmium (Ni-Cd) 3.6V, 60mAh capacity. The NMOS type transistor 110 has an internal gate terminal at an output terminal of the chip select signal generator 120 and a source terminal at an external supply power line and a supply power line of a backup battery 130, respectively. And switch to operate by a signal output from the chip select signal generator 120 to supply the current supplied to the source terminal to the chip select terminal of the RAM memory unit 100.

The other diodes D1, D2 and resistors R1, R2, and R3 are used for stable operation of the internal circuit.

Hereinafter, the operation of the present invention through the configuration as described above in detail.

First, when charging the backup battery 130, the power supply voltage Vcc of 5V is charged to about 4.8V through the first diode D1 and the first resistor R1, and the input power supply voltage Vcc is out of power. When discharging, the backup power is supplied to the RAM 100 through the second diode D2 and supplied to the source terminal of the NMOS transistor 110 through the first resistor R1 and the second resistor R2. .

)를 발생한다.In this case, the backup power supplied to the RAM 100 maintains user data and clock function data of the stored key phone system, and the power supplied to the source terminal of the NMOS transistor 110 is the NMOS transistor 110. The chip select signal RAM_ is connected to the chip select terminal of the RAM memory 100 depending on whether

Will occur).

)로 동작하는 소자 일 시 그 칩 셀랙트 신호(RAM_

)가 로우레벨로 공급되면 내부에 저장된 사용자 데이터 및 시계기능 데이터가 손상될 우려가 있기 때문에 상기 엔 모스 트랜지스터(110)의 소오스단의 전위를 하이레벨로 유지시키도록 한다.Therefore, the RAM memory 100 has a low active chip select signal RAM_.

Chip select signal (RAM_)

) Is supplied at a low level, so that user data and clock function data stored therein may be damaged, so that the potential of the source terminal of the transistor 110 is maintained at a high level.

)를 공급한다. 하지만, 정전 시에는 상기 칩 선택신호 발생부(120)가 동작하지 못해 출력되는 신호가 없기 때문에 상기 엔 모스 트랜지스터(110)는 턴-오프 동작한다. 그러므로, 상기 엔 모스 트랜지스터(110)의 소오스단에 인가되는 백업용 배터리(130)의 전류가 그대로 상기 램메모리(100)의 칩 셀렉트단자에 하이레벨로서 공급되어 엔 모스 트랜지스터(110)는 상기 램메모리(100)가 정전 시 액티브되지 않도록 한다.In this case, the NMOS transistor 110 is usually turned on or off by a signal output from the chip select signal generator 120 to select a chip of the RAM memory 100 as a potential of a source terminal. Chip Select Signal (RAM_)

). However, since the chip select signal generation unit 120 does not operate and there is no signal output during power failure, the NMOS transistor 110 is turned off. Therefore, the current of the backup battery 130 applied to the source terminal of the NMOS transistor 110 is supplied as it is to the chip select terminal of the RAM memory 100 as a high level so that the NMOS transistor 110 stores the RAM memory. Ensure that 100 is not active during a power outage.

As a result, as described above, the RAM memory 100 is not activated during a power failure, thereby increasing the data backup time of the memory.

The present invention as described above has the advantage that it is possible to increase the data backup time of the memory by providing a circuit that can reduce the current consumption of the backup battery used for data backup of the memory in the key-phone system.

Claims (3)

In the backup power supply circuit having a chip select signal generator for generating a chip select signal at the chip select terminal of the RAM memory, and a backup battery for supplying a backup current to prevent the loss of data stored in the RAM memory during power failure. In Located at the load between the chip select terminal of the RAM memory and the external power supply line, the external power supply is switched by a signal output from the chip select signal generator, and the chip select signal is transferred to the chip select terminal of the RAM memory. And a chip select signal control unit for supplying power applied from the backup battery to the chip select signal of the chip select terminal of the RAM memory during power outage so that the RAM memory unit is inactivated. Backup battery circuit for extension. The method of claim 1, wherein the chip select signal control unit, Using a MOS type transistor, an internal gate terminal is connected to an output terminal of the chip select signal generator, and a source terminal is connected to an external supply power supply line and a supply power supply line of a backup battery, respectively, to a signal output from the chip select signal generator. By switching to supply the current supplied to the source terminal to the chip select terminal of the RAM memory. The method of claim 1, wherein the chip select signal control unit, A bipolar transistor is used to connect an internal base end to an output end of the chip select signal generator, and a collector end to an external power supply line and a power supply line of a backup battery, respectively, and to output a signal from the chip select signal generator. By switching to supply the current supplied to the collector terminal to the chip select terminal of the RAM memory.

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