JPS6234142B2 - - Google Patents
Info
- Publication number
- JPS6234142B2 JPS6234142B2 JP56147680A JP14768081A JPS6234142B2 JP S6234142 B2 JPS6234142 B2 JP S6234142B2 JP 56147680 A JP56147680 A JP 56147680A JP 14768081 A JP14768081 A JP 14768081A JP S6234142 B2 JPS6234142 B2 JP S6234142B2
- Authority
- JP
- Japan
- Prior art keywords
- metal
- protrusion
- film
- lead
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910052751 metal Inorganic materials 0.000 claims description 43
- 239000002184 metal Substances 0.000 claims description 43
- 238000000034 method Methods 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 11
- 238000005304 joining Methods 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 description 13
- 229910052782 aluminium Inorganic materials 0.000 description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 8
- 229910052737 gold Inorganic materials 0.000 description 7
- 239000010931 gold Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/79—Apparatus for Tape Automated Bonding [TAB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
本発明は金属リードと電極の接続方法に関する
もので、特にフイルムキヤリアのリード先端に理
想的な金属突起を形成する方法を提供するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for connecting metal leads and electrodes, and in particular provides a method for forming ideal metal protrusions at the tips of leads of film carriers.
従来より半導体装置（以下半導体デイバイスと
よぶ）、即ちIC，LSI等は金属細線を用いたワイ
ヤボンデイングにより収納容器リードに接続され
ていた。一方、最近、フイルムキヤリアにより接
続方式が開発され、電卓、時計等の小型・薄型機
器の実装に非常に多く使用されている。第１図
Ａ，Ｂに通常のフイルムキヤリア方式（米国特許
3689991号明細書）を示した。第１図Ａのフイル
ムキヤリア１において、２は半導体デイバイス、
３は半導体デイバイス上に形成された金の金属突
起、４は錫メツキの銅リード、５はリードを保持
する樹脂フイルムである。 Conventionally, semiconductor devices (hereinafter referred to as semiconductor devices), such as ICs and LSIs, have been connected to storage container leads by wire bonding using thin metal wires. On the other hand, a connection method has recently been developed by film carriers, and is now widely used for mounting small and thin devices such as calculators and watches. Figures 1A and B show the conventional film carrier system (US patent
3689991). In the film carrier 1 of FIG. 1A, 2 is a semiconductor device;
3 is a gold metal protrusion formed on the semiconductor device, 4 is a tin-plated copper lead, and 5 is a resin film that holds the lead.
第１図Ｂはフイルムキヤリア１と半導体デイバ
イス２とを接続した状態を示す。 FIG. 1B shows a state in which the film carrier 1 and the semiconductor device 2 are connected.
以上の方式では、半導体デイバイス２のアルミ
電極上に金の金属突起３を形成する必要がある。 In the above method, it is necessary to form gold metal protrusions 3 on the aluminum electrodes of the semiconductor device 2.
この金属突起３の形成はウエハのままの状態で
行なわれるが、ホトエツチング、メタライゼーシ
ヨンに関しある程度の技術力と大幅な設備を必要
とする。 The formation of the metal protrusions 3 is carried out on the wafer as it is, but requires a certain degree of technical skill and extensive equipment regarding photoetching and metallization.
そこでこのような欠点を解決するため、金属突
起付フイルムキヤリアが発明されている。第２図
Ａに金属突起付フイルムキヤリアの概略を示した
が構造的には第１図に示すものとほヾ同様であ
る。異なる点は第２図Ａに示すように、樹脂フイ
ルム２２に付着されたリード２１の先端に突起２
３が形成されていることである。この突起２３の
作成法は種々考えられているが、現状、実用的な
方法として銅のエツチング又はメツキにより突起
を作るものがある。そしてこの突起上に通常は金
メツキがなされる。 In order to solve these drawbacks, a film carrier with metal protrusions has been invented. FIG. 2A schematically shows a film carrier with metal protrusions, which is structurally almost the same as that shown in FIG. The difference is that, as shown in FIG. 2A, there is a protrusion 2 at the tip of the lead 21 attached to the resin film 22.
3 is formed. Various methods have been considered for creating the protrusions 23, but at present, one of the practical methods is to make the protrusions by etching or plating copper. Gold plating is then usually applied on this protrusion.
しかしながら、リードと一体の銅の金属突起は
アルミ電極（半導体デイバイス上の電極）に比べ
固いため、接合面は第２図Ｂの如くになる。即
ち、半導体デイバイス２５上のアルミ電極２４に
金メツキされた銅バンプ（突起）２３の先端がめ
り込むが、銅は固いため横方向のつぶれが生じな
い。したがつてアルミ電極２４上の酸化膜はその
まま沈み込むにすぎず、接合はほとんど側面２６
でしか生じない。これは通常、金線を用いたボー
ルボンドでは金ボールがつぶれる際、横方向への
「ひしやげ」がありその流れによつてアルミ電極
表面の酸化膜が破壊され、良い接合ができるのと
比べると極めて不適合なことである。 However, since the copper metal protrusion integrated with the lead is harder than the aluminum electrode (electrode on the semiconductor device), the bonding surface becomes as shown in FIG. 2B. That is, the tip of the gold-plated copper bump (protrusion) 23 sinks into the aluminum electrode 24 on the semiconductor device 25, but since copper is hard, lateral collapse does not occur. Therefore, the oxide film on the aluminum electrode 24 simply sinks in, and the bonding is mostly on the side surface 26.
It only occurs in This is because when the gold ball is crushed in a ball bond using a gold wire, there is a lateral "heavy" flow that destroys the oxide film on the surface of the aluminum electrode, resulting in a good bond. This is extremely inappropriate in comparison.
以上のことを考慮して、リード先端につける金
属突起として次のことが要求される。 Considering the above, the following is required for the metal protrusion attached to the tip of the lead.
(1) アルミと同等もしくはそれ以下の硬さの金属
が望ましい。(1) A metal with hardness equal to or less than aluminum is desirable.
(2) 半導体デイバイス上の電極に接する部分は球
状又は、とがつていることが望ましい。これは
接触してから、接合までの間に金属突起が大き
く変形し、それによりアルミ電極上の酸化膜が
破られ露出した新鮮なアルミ膜と金属突起とが
容易に合金をつくるからである。(2) It is desirable that the part that contacts the electrode on the semiconductor device be spherical or pointed. This is because the metal protrusion is greatly deformed between contact and bonding, and as a result, the oxide film on the aluminum electrode is broken and the exposed fresh aluminum film and the metal protrusion easily form an alloy.
本発明は、上記の点を勘案してなされたもので
あり、あらかじめ金属突起を別の基板上に形成し
ておき、その金属突起とフイルムキヤリアのリー
ド先端部を位置合せして接着させリード側に金属
突起を転写し、これと電極を接合する方法に関す
るものであり、特に金属突起の先端形状を理想的
な形にする方法を提供するものである。 The present invention has been made in consideration of the above points, and involves forming metal protrusions in advance on another substrate, aligning the metal protrusions with the lead tips of the film carrier, and bonding them to the lead side. The present invention relates to a method of transferring a metal protrusion to a metal protrusion and joining the same to an electrode, and particularly provides a method for making the tip of a metal protrusion into an ideal shape.
以下第３図Ａ〜Ｈをもとにして本発明の一実施
例における金属リードと電極の接続方法について
説明する。第３図Ａに示す３１はシリコン単結晶
基板である。基板３１の主面に保護膜３２を形成
する。この保護膜３２はシリコンのエツチングに
耐えるものならば何でも良く通常は感光性樹脂を
用いる。第３図Ｂの３３は半導体デイバイス電極
配置に対応する部分であり、金属突起を形成する
部分で保護膜はない。 A method for connecting metal leads and electrodes in an embodiment of the present invention will be described below with reference to FIGS. 3A to 3H. 31 shown in FIG. 3A is a silicon single crystal substrate. A protective film 32 is formed on the main surface of the substrate 31. This protective film 32 may be made of any material as long as it is resistant to silicon etching, and photosensitive resin is usually used. Reference numeral 33 in FIG. 3B is a portion corresponding to the semiconductor device electrode arrangement, where a metal protrusion is formed and there is no protective film.
次に第３図Ｃに示すように異方性エツチング
（例えばKOH水溶液によるエツチング）を行うが
基板面指数によりピラミツド型又は三角錐型の穴
すなわち凹部３４ができる。 Next, as shown in FIG. 3C, anisotropic etching (for example, etching with a KOH aqueous solution) is performed, and a pyramid-shaped or triangular pyramid-shaped hole or recess 34 is formed depending on the substrate surface index.
次に第３図Ｄに示す如く表面にPt，PdやITO
等の金属膜３５を形成する。なお、この膜は前記
した金属膜３５でなく、シリコン基板に高濃度の
拡散を行なつた層でも良い。次に第３図Ｅに示す
如く、金属突起に相当する窓あけ３７を有するた
とえばSiO2等の保護膜３６を形成する。金属膜
３５を一方の電極とし、前記凹部に金めつきする
と第３図Ｆの３８で示す前記凹部に対応した凸部
を有する金属突起ができる。前記したPt，Pdや
ITO膜であれば金めつき液の温度を低くするか、
もしくはめつき時の電流密度を高くすると前記金
属膜から容易に剥離しやすい凸部を有する金属突
起３８が形成される。 Next, as shown in Figure 3D, the surface is coated with Pt, Pd or ITO.
A metal film 35 such as the like is formed. Note that this film is not the metal film 35 described above, but may be a layer obtained by performing high concentration diffusion on a silicon substrate. Next, as shown in FIG. 3E, a protective film 36 made of, for example, SiO 2 is formed having apertures 37 corresponding to metal protrusions. When the metal film 35 is used as one electrode and the recessed portion is plated with gold, a metal protrusion having a convex portion corresponding to the recessed portion shown at 38 in FIG. 3F is formed. The above-mentioned Pt, Pd and
If it is an ITO film, the temperature of the gold plating solution should be lowered, or
Alternatively, if the current density during plating is increased, metal protrusions 38 having convex portions that are easily peeled off from the metal film are formed.
次に第３図Ｇに示す如く従来の錫メツキ銅リー
ドのフイルムキヤリア３９を前記金属突起３８に
位置合せし加熱・加圧することにより（金一錫）
合金ができ、第３図Ｈに示す如く、金属突起４０
はリードの弾性力により基板から容易にはなれ、
フイルムキヤリア３９のリード側につく。 Next, as shown in FIG. 3G, a conventional tin-plated copper lead film carrier 39 is aligned with the metal protrusion 38 and heated and pressurized (gold-tin).
An alloy is formed, and metal protrusions 40 are formed as shown in FIG. 3H.
cannot be easily separated from the board due to the elastic force of the lead.
I will be on the lead side of the film carrier 39.
第４図Ａ，Ｂはこのようにして製造したフイル
ムキヤリアを半導体デイバイスにボンデイングす
る状態を示している。第４図Ａの如く、半導体デ
イバイス４２上の電極４３とリード先端４１を位
置合せし、加熱・加圧すると、金属突起の凸部が
押しつぶされると同時に電極４３の表面の酸化膜
をおし破ることにより第４図Ｂに示す如く電極４
３とリード４１とが接合される。 FIGS. 4A and 4B show the state in which the film carrier thus produced is bonded to a semiconductor device. As shown in FIG. 4A, when the electrode 43 on the semiconductor device 42 and the lead tip 41 are aligned and heated and pressurized, the convex part of the metal protrusion is crushed and at the same time the oxide film on the surface of the electrode 43 is broken. By this, the electrode 4 as shown in FIG.
3 and the lead 41 are joined.
なお、上記実施例では金の金属突起と錫メツキ
銅リードで説明したが、金メツキ銅リード又はア
ルミリードでも良い。 In the above embodiment, gold metal protrusions and tin-plated copper leads were used, but gold-plated copper leads or aluminum leads may also be used.
以上説明したように本発明の金属リードと電極
の接続方法は、金属突起を別基板で作製して転写
するので、フイルムキヤリアとしての歩留りは非
常に良い。さらに、金属突起の先端形状がピラミ
ツド状又は三角錐状等の凸部になつているため、
半導体デイバイス上のアルミ電極に接続する際
に、アルミ電極上の酸化膜が破れ、強固かつ確実
な接続が得られる。さらに本発明は基板がくり返
し使用できるため、非常に実用的である等の利点
を有し、工業上の利用価値が高い。 As explained above, in the method for connecting metal leads and electrodes of the present invention, the metal protrusions are produced on a separate substrate and transferred, so the yield as a film carrier is very high. Furthermore, since the tip of the metal protrusion has a convex shape such as a pyramid or triangular pyramid,
When connecting to an aluminum electrode on a semiconductor device, the oxide film on the aluminum electrode is broken, resulting in a strong and reliable connection. Furthermore, the present invention has the advantage of being extremely practical since the substrate can be used repeatedly, and has high industrial utility value.
第１図Ａ，Ｂは従来のフイルムキヤリアによつ
てボンデイングする工程を示す図、第２図Ａ，Ｂ
は従来の突起電極付フイルムキヤリアによつてボ
ンデイングする工程を示す図、第３図Ａ〜Ｈは本
発明の一実施例におけるフイルムキヤリアに金属
突起を形成する製造法を説明するための図、第４
図Ａ，Ｂは同製造法によつて得られたフイルムキ
ヤリアでボンデイングする工程を示す図である。
３１……基板（シリコン単結晶基板）、３３…
…凹部（穴）、３５……金属膜、３８……突起電
極、３９……フイルムキヤリア、４０……突起電
極。
Figures 1A and B are diagrams showing the bonding process using a conventional film carrier, Figures 2A and B
3 is a diagram showing a bonding process using a conventional film carrier with protruding electrodes, FIGS. 4
Figures A and B are diagrams showing a bonding process using a film carrier obtained by the same manufacturing method. 31...Substrate (silicon single crystal substrate), 33...
... recess (hole), 35 ... metal film, 38 ... protruding electrode, 39 ... film carrier, 40 ... protruding electrode.
Claims (1)
程と、前記凹部内に形成した金属層を介して金属
突起を前記凹部に形成する工程と、フイルムキヤ
リアのリード先端部を前記金属突起に位置合せ
し、前記リード先端部と金属突起とを接合した
後、前記リードに接合された前記金属突起を前記
基板の凹部より前記凹部に対応した凸部を有する
前記金属突起を離反せしめる工程と、前記金属突
起の凸部と電子部品の電極とを接合する工程を含
むことを特徴とする金属リードと電極の接続方
法。1. A step of forming a recess at a predetermined position on one main surface of the substrate, a step of forming a metal protrusion in the recess via a metal layer formed in the recess, and a step of attaching a lead end of a film carrier to the metal protrusion. After aligning and bonding the lead tip and the metal protrusion, separating the metal protrusion bonded to the lead from the concave part of the substrate, the metal protrusion having a protrusion corresponding to the concave part; A method for connecting a metal lead and an electrode, the method comprising the step of joining the convex portion of the metal protrusion to an electrode of an electronic component.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56147680A JPS5848445A (en) | 1981-09-17 | 1981-09-17 | Manufacture of film carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56147680A JPS5848445A (en) | 1981-09-17 | 1981-09-17 | Manufacture of film carrier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5848445A JPS5848445A (en) | 1983-03-22 |
| JPS6234142B2 true JPS6234142B2 (en) | 1987-07-24 |
Family
ID=15435845
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56147680A Granted JPS5848445A (en) | 1981-09-17 | 1981-09-17 | Manufacture of film carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5848445A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5999095U (en) * | 1982-12-23 | 1984-07-04 | 三菱重工業株式会社 | press |
| US5208186A (en) * | 1989-02-09 | 1993-05-04 | National Semiconductor Corporation | Process for reflow bonding of bumps in IC devices |
| JP2625662B2 (en) * | 1996-02-13 | 1997-07-02 | 九州日立マクセル株式会社 | Electroformed metal body |
| JP2004221502A (en) | 2003-01-17 | 2004-08-05 | Nec Electronics Corp | Wiring board with bump electrode and its manufacturing method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4869471A (en) * | 1971-12-22 | 1973-09-20 | ||
| JPS5469383A (en) * | 1977-11-15 | 1979-06-04 | Toshiba Corp | Production of semiconductor device |
-
1981
- 1981-09-17 JP JP56147680A patent/JPS5848445A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4869471A (en) * | 1971-12-22 | 1973-09-20 | ||
| JPS5469383A (en) * | 1977-11-15 | 1979-06-04 | Toshiba Corp | Production of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5848445A (en) | 1983-03-22 |
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