JPS6233461A - Semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device using a conductive layer having high conductivity at a semiconductor heterojunction interface, particularly to a semiconductor device with excellent high speed and high frequency characteristics. It is something.

[Conventional technology]

In recent years, heterojunction ΔHanoJ has been used as an ultra-high frequency/ultra-high speed device.
2-+$L Technique J/+%+τUp Nakashisuke Genne 7) is seen as promising. The theoretical approach of HBT was made by HKro@mar, for example in Proceedings of the ITriple E (Prcendin
gs of the IEEE), Volume 70, No. 1, 13
(1982). The main features of HBTs include improved emitter efficiency and current gain, but actual HBT element structures still vary. FIG. 4 shows the structure of a typical HBT. In FIG. 4, for example, in the case of an npn type, 101 is a collector electrode, 102 is an n-type substrate, for example, GaAs, 103 is an n-type first semiconductor layer, for example, GaAs, and 104 is a p-type second semiconductor layer, for example. GaAs.

Reference numeral 105 indicates an n-type third semiconductor layer having a larger electron affinity than the sum of the energy gap of the second semiconductor layer 104, for example, kA, GILQ, 7A8, 106 a pace electrode, and 107 an emitter electrode. FIG. 5 shows an energy band diagram directly below the emitter electrode 107 in a thermal equilibrium state. Here, EC represents the energy level at the lower end of the conduction band, E represents the Fermi level, and EV represents the energy level at the upper end of the valence band. In the HBT shown in FIG. 4, most of the electrons injected from the emitter electrode 107 into the pace layer (second semiconductor layer) 104 reach the collector electrode 101, whereas most of the electrons are injected from the emitter electrode 106 into the emitter layer (second semiconductor layer). The holes injected into the semiconductor layer (3) 105 are:
This becomes extremely small due to reflection by the emitter layer 105, which has a larger energy gap than the paste layer 104.

Therefore, for example, the current amplification factor hFE when the emitter is grounded becomes extremely large.

[Problem that the invention seeks to solve]

However, in the conventional HBT shown in FIG. 4, for example, the space layer 104, which is important for high performance,
The width W of W and the pace resistance rB are in a canceling relationship (that is, W
When , is made smaller, rB increases. ), which has the disadvantage of limiting the performance improvement of HBT. To describe this in detail, consider, for example, the maximum oscillation frequency f1 of the HBT and the switching time 8. As is known, f□8 and τ are approximately given by the following equations.

Here, ft is the cutoff frequency, rB is the base resistance, C3 is the collector capacitance, and rL and CL are the load resistance and load capacitance. It is also given by running in the pace area of minority carriers. W is the base width, and Dn is the diffusion constant of minority carriers (electrons in this case). Furthermore, f is approximately inversely proportional to ρ1-. Paying attention to equations (1) to (3), rB,
It can be seen that reduction of WB and Cc is extremely important for improving the performance of HBT. However, if W is made smaller, r becomes larger, which has the drawback of severely restricting the performance improvement of the HBT as described above. Also, this drawback is that npn type HB
It is clear that this problem is common not only to HBTs but also to pnp type HBTs.

SUMMARY OF THE INVENTION An object of the present invention is to provide a bipolar semiconductor device using a heterojunction which eliminates the drawbacks of the prior art as described above and has excellent high speed and high frequency characteristics.

[Means for solving problems]

The present invention provides the following features: (1) a p-type second semiconductor layer, a high purity or n-type third semiconductor layer on the n-type first semiconductor layer; The sum is large,
A p-type fourth semiconductor layer and a high-purity or n-type fifth semiconductor layer having a smaller sum of electron affinity and energy gap than the fourth semiconductor are sequentially stacked, and the third to fifth semi-consolidated bodies It comprises at least one unit of 84 semiconductor layers composed of 84 layers, and further includes a p-type sixth semiconductor layer and an n-type seventh semiconductor layer on the surface thereof,
A semiconductor device comprising electrodes in ohmic contact with the first and seventh semiconductor layers, respectively, and a control electrode in contact with the semiconductor stack; an n-type second semiconductor layer; a high-purity or p-type third semiconductor layer;
An n-type fourth semiconductor layer having a lower electron affinity than the fourth semiconductor, and a high-purity or p-type fifth semiconductor layer having a higher electron affinity than the fourth semiconductor are laminated in sequence, and A semiconductor laminated layer composed of a fifth semiconductor layer is provided as one unit, at least one unit, and further an n-type sixth semiconductor J bias and a p-type seventh semiconductor layer are provided on the surface thereof, The semiconductor device is characterized in that it has electrodes that are in ohmic contact with the first and seventh semiconductor layers, respectively, and a control electrode that is in contact with the semiconductor stack.

[Principle and operation of the invention]

Hereinafter, the principle and specific effects of the present invention will be explained with reference to the drawings. For convenience of explanation, a specific material will be used, but it is clear that the principles of the present invention can be applied to other materials as well.

FIG. 1(a) is a schematic cross-sectional view showing an example of the basic structure of the semiconductor device of the present invention.

In FIG. 1(a), 11 is a high-resistance substrate, 12 is an n-type first semiconductor layer, and 13 is a p-type second semiconductor IJ 14.
15 is a high purity or n-type third semiconductor layer, 15 is a p-type fourth semiconductor layer having a larger sum of electron affinity and energy gap than the third semiconductor 14, and 16ii is the fourth semiconductor layer.
A fifth semiconductor layer of high purity or n-type, which has a smaller sum of electron affinity and energy supply than the semiconductor 15 of
7 is a p-type sixth semiconductor layer, 18 is an n-type seventh semiconductor layer, 19 is a control electrode, 20 and 21 are the first semiconductor layer 1
This is an ohmic electrode in contact with the second and seventh semiconductor layers 18 .

FIG. 1(b) is an example of an energy Gund diagram directly under the electrode 2o in a thermal equilibrium state in the structure according to the present invention shown in FIG. 1(,). Here, 22 is a two-dimensional hole layer, and E, , E, , Ev are the same as those explained in FIG. 5.

The basic principle of the present invention is that the third semiconductor layer 14 and the fifth
By utilizing the high conductivity and confinement effect within a narrow region of the two-dimensional hole layer 22 formed at the heterojunction interface between the semiconductor 7#16 and the fourth semiconductor layer 15, for example, HBT
To reduce rB and WB when applied to HBT
QIt realizes high performance.

In other words, as is known, the two-dimensional holes formed in the high-purity layers 14 and 16 are less affected by the scattering of impurities, and furthermore, the two-dimensional holes formed in the high-purity layers 14 and 16 are less scattered due to the two-dimensional nature of the originally distributed degrees of freedom. Therefore, it has an extremely large hole mobility μh, especially at low temperatures. For example, in the case of a hole in GaAs, at room temperature μh4400 sub2/v・s 77μ
hri increases dramatically to 4000(7)2/v・8. Although the hole surface density P of this two-dimensional hole layer varies depending on the carrier density and film thickness of each semiconductor layer, it is possible to realize a hole surface density P of about I×10 m at each heterojunction interface.

Furthermore, since the spread of this two-dimensional hole wave is extremely small, approximately 100X at each heterojunction interface, in other words, the hole is confined in the triangular potential well at the heterojunction interface, which reduces the effective pace width. It is expected that this will make a significant contribution.

The Vr layer of τ is the base of the nine-axe I
Consider the sheet resistance R6 in the pace region when B is as thin as 500X. Ro is given by the following formula.

Ro=(qp, μh) −' (4) Here, q is the amount of charge of the electron. In the case of the conventional structure shown in FIG. 4, when W = 500X, there is a depletion layer width due to the pn junction, so the effective width of the space layer 104 is lX1
0 crn density (pace layer 104
) and a donor density of about 5×10 crn (emitter layer 105 and collector layer 103), approximately 30
It is considered to be 0X. In addition, considering that the hole mobility in a semiconducting material with a high acceptor density is greatly reduced compared to the case of high purity, 1. For example, if p-type GaAs is used for the space layer 104, 2/v of μh ~ 100.・It becomes 3. Therefore, R6 in the conventional structure is estimated to be approximately 20kQ10. On the other hand, in the present invention, 8 to R9 at room temperature.
At k10.77, R9 to 0.8 becomes Ω10, and it is clear that the sheet resistance R8 in the pace region, and therefore the pace resistance rB, is greatly improved by the present invention. Furthermore, the value of W, which is often used in conventional structures (≧1000 K)
Since WB can also be made smaller than , τ can be significantly improved from equation (3). Regarding the injection efficiency of the emitter, since the two-dimensional hole layer 22 senses the potential barrier at the heterojunction interface, the confinement effect is high, and therefore it is close to the ideal value of 1.

As explained above, it is clear that the present invention significantly improves r and WB, so that characteristics are improved in both fmaX and τ8, and therefore a semiconductor device with excellent high speed and high frequency characteristics can be obtained. It is.

In the above explanation, the so-called n
Although the pn type has been described, the principles of the present invention can be similarly applied to the so-called pnp type in which holes serve as minority carriers.

FIG. 2(,) is a schematic cross-sectional view showing an example of the basic structure of a pnp type semiconductor device according to the present invention.
, ), 31 is a high-resistance substrate, 32 is a p-type first semiconductor layer, 33 is an n-type second semiconductor layer, 34 is a high-purity or p-type third semiconductor layer, and 35 is the aforementioned first semiconductor layer. 3 is an n-type fourth semiconductor layer having a smaller electron affinity than the semiconductor layer 34 of No. 3; 36 is a high-purity or p-type fifth semiconductor layer having a larger electron affinity than the fourth semiconductor layer 35; 37 is an n-type fifth semiconductor layer;
a p-type sixth semiconductor layer; 38 is a p-type seventh semiconductor layer;
9 is a control electrode, and 40 and 41 are ohmic electrodes in contact with the seventh semiconductor layer 38 and the first semiconductor layer 32.

FIG. 2(b) is an example of an energy band diagram below 4000 electrodes in a state of thermal equilibrium in the structure according to the present invention shown in FIG. 2(a). Here, 42 is a two-dimensional electron layer, and EC, E, Ey are shown in Fig. 1(b).
and is the same as that explained in FIG.

It goes without saying that the semiconductor device according to the present invention has basically the same principles, operations, and effects as the aforementioned npn type semiconductor device.

〔Example〕

Examples of the present invention will be shown below.

(Example 1) A schematic structural cross-sectional view of the HBT in this example is shown in Figure 1 (
, ) is the same. In this example, a high-resistance QaAs substrate is used for 11, and a donor impurity density of 5 x 1 is used for 12.
0" N-type A with a thickness of about 6cm-3 and a film thickness of 5ooo l
4. Ga (,75Aa, 13 with an acceptor impurity density of about 5 x 10110l7' and a film thickness of 100X,
The molar ratio X of AtAa is 0 at the interface with the first semiconductor layer 12.
．． AtX becomes 25, gradually decreases toward the third semiconductor layer 14 side, and becomes zero at the interface with the third semiconductor layer 14.
G1-XAm, the impurity density is l x 10”c at 14
m−' or less, non-doped 7'GaA@ with a film thickness of 300 and an acceptor impurity density of 2X10 cm at 15
p-type AZnsG&, with a film thickness of about 500m
Aa, 16 is undoped GaAs with an impurity density of 1 x 1015 crn-3 or less and a film thickness of 300X, and 17 is undoped GaAs with an acceptor impurity density of about 1 x 10 ctn and a film thickness of 10
At 0X, the molar ratio y of AtAII becomes zero at the interface with 16, gradually increases toward the 18 side, and becomes 0 at the interface with 18.
．． 3, ALyGa 1-yAa was made into 18 with a donor impurity density of about 5X1017m-3 and a film thickness of 5000X.
n-type AAQ, 3Ga, 17A3, ohmic electrodes 20 and 4 are AuG5/Ni electrodes, control electrodes (in this embodiment, for example, ohmic electrode 20 is the emitter electrode of HBT, and 21 is the collector electrode). The base resistance rB in this example is significantly improved compared to the conventional example, and the maximum oscillation frequency f ax is approximately 15 GHz compared to approximately 10 GHz or less in the conventional example.
and increased. Furthermore, τ and τ were also significantly improved due to the reduction in rB. In this example, an ohmic electrode made of AuZn is used as the control electrode 19, but it is clear that IBT operation is also possible in principle (for example, by using a Schottky electrode made of At).

(Example 2) A schematic cross-sectional view of the structure of HBT' in this example is shown in FIG. 3. In this embodiment, as shown in the figure, it is a laminate with 52 to 61 layers. 52 has a donor impurity density of 5×
A GaAa substrate of about 10 α was formed with a donor impurity density of about 5 × 1016 cm−3 and a film thickness of 300
0x At, Ga 117Aa, acceptor impurity density is about 5x10 an, film thickness is 200x
Then, the molar ratio of AtAs gradually decreases and becomes zero at the interface with 55.
GaAs with a film thickness of 300× below ×10 σ, 56
At No. 57, At, 13Gao, and 7As with an impurity density of I X 10''' tyn-3 or less and a film thickness of 30X are used, and at 57, an acceptor impurity density of about 3X18 an and a film thickness of 3
00X of At, Gacl, 7As, 58 with impurity density of I x 10'``cm-'' or less and film thickness of 300X of GaAa, 59 with acceptor impurity density of 5 x 101
At a film thickness of 200X, the molar ratio y of AtAs is 58
It becomes zero at the interface with , and gradually increases toward the 60 side,
Aty9a 1-yA becomes 0.35 at the interface with 60
s, the donor impurity density is 5 x 10” cm at 60
Ata, 35G & a6 with film thickness of 200OR at around -3
sAB with a donor impurity density of 5X10 cm at 61
GaAs with a film thickness of approximately 3000 mm was used, the ohmic electrodes 51 and 63 were made of AuGe/Ni, and the control electrode (so-called base electrode) 62 was made of AuZn.

In this example, when 51' (i7 IIBT collector electrode and 63 are operated as emitter electrodes), fm&X is further improved compared to Example 1, and is approximately 18 GHz.
It became. This is because the introduction of the so-called scatterer layer 56 reduces impurity scattering and increases the two-dimensional hole mobility, the provision of two base electrodes 62, and the two-dimensional hole layer. This is due to the fact that rl was significantly reduced by increasing the number of interfaces, and the emitter injection efficiency was further improved by increasing the effective donor density on the emitter side.

It is clear from the results of the above examples that the present invention has extremely great advantages.

(Example 3) Next, a pnp type embodiment will be described.

The schematic cross-sectional view of the structure in this example is the same as that in FIG. 2(a).

In this example, a high-resistance GaAa substrate is used as 31;
2, the acceptor impurity density is about 5xlOan, and the film thickness is 5oool Ly) p-type kLI12sG& [1
75Aa, donor impurity density in 33 is 5 x 10”
molar ratio of AtAs at a film thickness of 100^
At the interface with 33, AtXGa 1-xAs decreases to 025 at the interface with 34 and becomes zero at the interface with 34, and at 35, undoped GaAs with an impurity density of less than l In 36, the donor impurity density is about 2 x 10'cm-' and the film thickness is 5.
00X ALa, s GiL CL7AII was applied to 37 with an impurity density of 1Xl0 cm or less and a film thickness of 300
A
The molar ratio y of a becomes zero at the interface with 37, gradually increases toward the 39 side, and becomes 03 at the interface with 39.
The acceptor impurity density is about 5x100 and the film thickness is 500 1 p-type Ato to GIL-Aat-139.
3Ga, As to the ohmic electrodes 40 and 41.
The control electrode 39 is made of AuGe/Ni.
electrodes were used.

When this example is applied to an HBT, the mobility and areal density of the two-dimensional electron layer 42 responsible for the base resistance rB are very high, so rB and W are the same as in the previous example.

Therefore, it is possible to improve the performance of fmax, ft, etc., and to reduce τ. Note that HBT operation is possible even if the control electrode 39 is a Schottky electrode.

[Effects of the Invention] As described above, according to the present invention, by using a two-dimensional carrier having high conductivity and a confinement effect formed at the Peter junction interface, the base resistance and the base width can be reduced. This has the effect of realizing an ultra-high frequency and ultra-high speed element that has great advantages such as an improvement in the maximum oscillation frequency and cut-off frequency, and a significant reduction in the base travel time and switching time.

[Brief explanation of drawings]

FIG. 1(a) and FIG. 2(,) are schematic cross-sectional views showing an example of the basic structure of the semiconductor device of the present invention, and FIG. 1(b) and FIG. 2(b) are respective energy bands. Figure, 3rd
The figure is a schematic cross-sectional view showing the structure of Example 2 of the present invention.
The figure is a schematic cross-sectional view showing the structure of an example of a conventional semiconductor device, and FIG. 5 is its energy band diagram. 11 and 31... High resistance substrate, 12... N-type first
Semiconductor layer of 32... Semiconductor layer of p-type cylinder 1, 13...
・P-type second semiconductor layer, 33...N-type second semiconductor layer, 14...High purity or other type third semiconductor layer, 34...High purity or p-type third semiconductor layer 3 semiconductor layers, 1
5... P-type fourth semiconductor layer, 35... N-type fourth semiconductor layer
16... High purity or n-type semiconductor layer, 36... High purity or p-type fifth semiconductor layer, 17... P-type sixth semiconductor layer, 37 ... n-type sixth semiconductor layer, 18 ... n-type seventh semiconductor layer,
38... p-type seventh semiconductor layer, 19 and 39...
Control electrodes, 20, 21, 40 and 41... Ohmic electrodes, 22... Two-dimensional hole layer, 42... Two-dimensional electron layer.

Claims (2)

[Claims] (1) a p-type second semiconductor layer on the n-type first semiconductor layer, a high-purity or n-type third semiconductor layer, which has a larger sum of electron affinity and energy gap than the third semiconductor;
A p-type fourth semiconductor layer, which has a smaller sum of electron affinity and energy gap than the fourth semiconductor layer, and has a high purity or n
The fifth semiconductor layer of the type is sequentially laminated, and at least one unit includes at least one semiconductor laminated layer composed of the third to fifth semiconductor layers, and further a p-type sixth semiconductor layer is formed on the surface thereof. A semiconductor layer and an n-type seventh semiconductor layer are provided, and each of the first and seventh semiconductor layers has an electrode in ohmic contact with the semiconductor layer, and a control electrode in contact with the semiconductor stack. Semiconductor equipment. (2) On the p-type first semiconductor layer, an n-type second semiconductor layer, a high-purity or p-type third semiconductor layer, and an n-type semiconductor layer having a lower electron affinity than the third semiconductor layer. 4 semiconductor layer,
A high-purity or p-type fifth semiconductor layer having a higher electron affinity than the fourth semiconductor is sequentially laminated, and
A semiconductor stack composed of the first to fifth semiconductor layers is 1
It has at least one unit as a unit, and further has n on its surface.
A p-type sixth semiconductor layer and a p-type seventh semiconductor layer are provided, and have electrodes in ohmic contact with the first and seventh semiconductor layers, respectively, and a control electrode in contact with the semiconductor stack. A semiconductor device characterized by: