JPS60242671A - heterojunction bipolar transistor - Google Patents
heterojunction bipolar transistorInfo
- Publication number
- JPS60242671A JPS60242671A JP59098091A JP9809184A JPS60242671A JP S60242671 A JPS60242671 A JP S60242671A JP 59098091 A JP59098091 A JP 59098091A JP 9809184 A JP9809184 A JP 9809184A JP S60242671 A JPS60242671 A JP S60242671A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- base
- type
- doped
- base region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D10/00—Bipolar junction transistors [BJT]
- H10D10/80—Heterojunction BJTs
- H10D10/821—Vertical heterojunction BJTs
- H10D10/881—Resonant tunnelling transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
- H10D62/815—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW]
- H10D62/8161—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices
- H10D62/8162—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices having quantum effects only in the vertical direction, i.e. layered structures having quantum effects solely resulting from vertical potential variation
- H10D62/8164—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices having quantum effects only in the vertical direction, i.e. layered structures having quantum effects solely resulting from vertical potential variation comprising only semiconductor materials
Landscapes
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ベース抵抗がきわめて小さく、超高速動作す
るヘテロ接合バイポーラトランジスタに関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a heterojunction bipolar transistor that has extremely low base resistance and operates at ultra high speed.
従来のへテロ接合バイポーラトランジスタは、第４図に
示すように、ｎ型ＡＡ！ＧａＡ３などの禁制帯幅の大き
いエミッタ領域１とＰ −ＧａＡｓなどのベース領域２
とｎ−ＧａＡｓなどのコレクタ領域３から構成されてい
た。エミッタ領域１の禁制帯幅が大きイタメ、ベース領
域２の正孔のエミッタ側への注入量をきわめて小さくす
ることができ、ベース領域２の正孔濃度ｉ１０”ａｍ−
↑程度に太きくしても十分な電流利得が得られる特徴を
有していた。一方ベース領域２の正孔濃度が大きくなる
と、それにつれて正孔移動度は不純物散乱の影響で小さ
くなシ、正孔濃度×正孔移動度から決まるベース抵抗の
低減が制限される欠点を有していた。The conventional heterojunction bipolar transistor is an n-type AA! transistor, as shown in FIG. An emitter region 1 such as GaA3 with a large forbidden band width and a base region 2 such as P-GaAs.
and a collector region 3 made of n-GaAs or the like. Since the forbidden band width of the emitter region 1 is large, the amount of holes injected into the emitter side of the base region 2 can be extremely small, and the hole concentration in the base region 2 i10"am-
It had the characteristic that sufficient current gain could be obtained even if the thickness was increased to ↑. On the other hand, as the hole concentration in the base region 2 increases, the hole mobility decreases due to the influence of impurity scattering, which has the disadvantage that the reduction in base resistance determined by hole concentration x hole mobility is limited. was.
本発明は、従来のへテロ接合バイポーラトランジスタに
おける上記ベース抵抗の低減が制限されるという問題点
を解決する。The present invention solves the problem of limited reduction in base resistance in conventional heterojunction bipolar transistors.
本発明は、高ドープＵた禁制帯幅の大きい半導体と意識
的にドープしない半導体を交互に重ねた変調ドープした
半導体層をベース領域に用いることによシ、高移動度を
維持した状態で高濃度のべ、−ス領舅を実現し、従来の
ものよシきわめて低抵抗のベース領域金得るものである
。従って従来のものよシ超高速動作するヘテロ接合バイ
ポーラトランジスタが実現できる。The present invention achieves high mobility while maintaining high mobility by using modulation-doped semiconductor layers in the base region, in which highly doped U semiconductors with a large bandgap and intentionally undoped semiconductors are alternately stacked. This achieves a base region of high concentration and provides a base region of extremely low resistance compared to the conventional method. Therefore, it is possible to realize a heterojunction bipolar transistor that operates much faster than conventional ones.
以下に本発明について、具体的に説明するために実施例
を示す。Examples are shown below to specifically explain the present invention.
〔実施例〕
第３図は本発明の実施例の要部であって、４はＰ型ＡＪ
ｘ、Ｇａｔ−ｘｌＡｓなどの大きい禁制帯幅を有する半
導体、５は低不純物濃度のＰ型ＧａＡ、 、 ６は高不
純物濃度のＰ型Ａｌｘ２Ｇａ ｚ−ｘ２ＡｓでＳ、ａ、
７は５と６の多層構成の領域、８はｎ型ＧａＡｓである
。本実施例では、４はエミッタ領域であり、Ｘｌ）０．
３が有効でアシ、−例としてｘｌ＝ｏ、ａｓとした。エ
ミッタ領域４０層の不純物濃度はエミッタ注入効率を上
げるためある程度高い方が良く、ここでは、１−１−１
ＯＸ１０ のＳよ−ドープを用いた。５０層は意識的に
ドープしない層、６の層はＸｓ ＞ Ｌ ＞ ０の条件
が必要でおシ、４の層よシも禁制帯幅を小さくする必要
があ夛、ここでは’）Ｃ２＝ ０．２とし、不純物濃度
は０．５〜５ Ｘ １０１９層ｍ−”のＢｅ−ドープを
用いた。この５と６の多層構成の７の領域がベース領域
として動作する。８の領域はコレクタ領域に相当し１〜
５０ Ｘ 工０ ”ｅｍ−８のｎ型ＧａＡＢを用いた。[Embodiment] Fig. 3 shows the main part of an embodiment of the present invention, and 4 is a P-type AJ.
x, a semiconductor with a large forbidden band width such as Gat-xlAs, 5 is P-type GaA with a low impurity concentration, 6 is P-type Alx2Ga z-x2As with a high impurity concentration, S, a,
7 is a multilayered region of 5 and 6, and 8 is n-type GaAs. In this example, 4 is the emitter region, Xl)0.
3 is valid, and as an example, xl=o, as. The impurity concentration of the emitter region 40 layer should be high to some extent in order to increase the emitter injection efficiency, and here, 1-1-1
OX10 S-doped was used. The 50th layer is a layer that is not intentionally doped, the 6th layer requires the condition of Xs > L > 0, and the 4th layer also needs to have a smaller forbidden band width. 0.2, and the impurity concentration was 0.5 to 5 x 1019 layers m-'' of Be-doped. Region 7 of this multilayer structure of 5 and 6 acts as a base region. Region 8 acts as a collector. Corresponds to the area 1~
N-type GaAB of 50 x 0'' em-8 was used.
本実施例の構造のエネルギバンド図を第１図に示す。ベ
ース領域７のＰ” −Ａ７！ｘ２Ｇａ１−Ｘ２Ａｓ ／
Ｐ−ＧａＡｓの価電子帯のエネルギバンドは図示のごと
くである。Ｐ” −ＡＡ’ｘ、Ｇａｔ−ｘ２Ａｓ ６内
のアクセプタ準位Ａからホールが放出されてＰ −Ｇａ
Ａｓ Ｓ内に蓄積され、ポールＨは低不純物濃度のＰ
−ＧａＡ８５内を伝帳するので図面に縦方向のホールＨ
による移動度が従来のＰ＋−ＣａＡｓの移動度よ多数倍
大きくなシ、ベース抵抗の低減に効果的である。一方、
エミッタから注入される電子Ｅは、図示のごとく、エネ
ルギの高い所から注入されることになるので、伝導帯の
凸凹に影響されることは少ない。FIG. 1 shows an energy band diagram of the structure of this example. P''-A7!x2Ga1-X2As of base region 7 /
The energy band of the valence band of P-GaAs is as shown in the figure. Holes are released from the acceptor level A in P''-AA'x, Gat-x2As 6, and P-Ga
As is accumulated in S, and pole H is P with a low impurity concentration.
- Since the inside of GaA85 is to be transferred, there is a vertical hole H in the drawing.
The mobility of P+-CaAs is many times larger than that of conventional P+-CaAs, which is effective in reducing base resistance. on the other hand,
As shown in the figure, the electrons E injected from the emitter are injected from a place with high energy, so they are hardly affected by the unevenness of the conduction band.
本発明のような変調ドープしたベース領域の正孔の移動
度は３００Ｋにおいて４００ ａｍ”／’Ｖ’ｓｅｃ以
上、７７Ｋにおいて６０００ ａｍ”／Ｖ’ｓｅｃが得
られる。従来の１０”ａｍ−’程度のＰ型Ｇ’ａＡｓベ
ースでは正孔の移動度は３００ Ｋにおいて約１００〜
２００Ｃｍ／ｖ−８ｅＣ５７７Ｋにおいても１０００
ａｍ”／ Ｖ・ｓｅｃ 以下でお９〜変調ドープベース
領域を用いることによ）約５倍のベース抵抗の低減が達
成できる。The hole mobility of the modulation-doped base region according to the present invention is 400 am''/'V'sec or more at 300K and 6000 am''/V'sec at 77K. In the conventional P-type G'aAs base of about 10"am-', the hole mobility is about 100 ~ at 300K.
1000 even at 200Cm/v-8eC577K
By using a modulated doped base region of less than 900 m/V·sec, a reduction in base resistance of about 5 times can be achieved.
一般にバイポーラトランジスタのスイッチ時間ｔはベー
ス抵抗ｒｂとベースコレクタ間容量ＣＢＣの積に比例す
る。従ってｒｂがに倍に軽減された本発明のへテロ接合
バイポーラトランジスタは従来のものより５倍の高速動
作が達成できる。Generally, the switching time t of a bipolar transistor is proportional to the product of the base resistance rb and the base-collector capacitance CBC. Therefore, the heterojunction bipolar transistor of the present invention, in which rb is reduced by 2 times, can achieve a high-speed operation 5 times that of the conventional transistor.
一方、本発明のへテロ接合パイボーラトランジため、第
１図のように不連続で凸凹した形状となる。この場合エ
ミッタ４からベース７へ注入された電子が伝導体の不連
続な部分で反射され電子速度が低減される可能性がある
。ところが、Ｐ型ＧａＡ３５とＡ’Ｘ２Ｇａｌ−Ｘ２Ａ
Ｂ ６の各々の厚さを１０〜５０Ａにすれば、超格子構
造に基づく連続的な伝導帯が形成され、電子速度が減速
されることのない構成が実現できる。他方、各層の厚さ
をこのように薄くした場合には、前述のベース抵抗の低
減の効果が少なくなる場合が生じ易い。従ってベース領
域の多層構造は、エミッタからペースへ注入された電子
速度を速いまま維持し、かつベース抵抗を低減させるた
めの最適構造が存在する。On the other hand, because of the heterojunction pibora transition of the present invention, it has a discontinuous and uneven shape as shown in FIG. In this case, there is a possibility that the electrons injected from the emitter 4 to the base 7 are reflected by the discontinuous portion of the conductor, reducing the electron velocity. However, P-type GaA35 and A'X2Gal-X2A
By setting the thickness of each B6 to 10 to 50 A, a continuous conduction band based on a superlattice structure is formed, and a configuration in which the electron velocity is not slowed down can be realized. On the other hand, when the thickness of each layer is reduced in this way, the effect of reducing the base resistance described above is likely to be reduced. Therefore, the multilayer structure of the base region has an optimal structure for maintaining the high velocity of electrons injected from the emitter to the paste and reducing the base resistance.
本発明の構造を詳細に検討した結果、第３図において４
のＮ−ＡＡ’ｘ、Ｇａｔ−ｘｌＡｓとしてＸ１≧０．３
．５のＰ型ＧａＡｓの厚さｄｌを１０ （ｄｌ＜ａｏｏ
Ｘ、 ６のＰ型ＡＪｘ２Ｇａｔ−ｘｌＡｓとして０．１
≦Ｘ２≦０．３、その厚さｄ２を１０ ＜ｄａ （ａｏ
ｏ Ａ 、Ｐ型不純物濃度を０．５〜５Ｘ１０ｃｍ と
した場合に低いベース抵抗でかつ１００以上の高い電流
増幅率のへテロ接合バイポーラトランジスタが実現でき
た。As a result of a detailed study of the structure of the present invention, in FIG.
N-AA'x, Gat-xlAs, X1≧0.3
．． The thickness dl of P-type GaAs in 5 is 10 (dl<aoo
X, 6 P type AJx2Gat-xlAs as 0.1
≦X2≦0.3, and its thickness d2 is 10 <da (ao
oA, a heterojunction bipolar transistor with a low base resistance and a high current amplification factor of 100 or more was realized when the P-type impurity concentration was set to 0.5 to 5×10 cm.
本発明の主旨の範囲内において、４，５，６，８の各層
をＩｎＧａＡｓ、 ＩｎＡＪＡＢ、 ＩｎＧａＡｓＰ、
ＩｎＰ 等地の化合物半導体で構成することも当然可
能である。Within the scope of the present invention, layers 4, 5, 6, and 8 are made of InGaAs, InAJAB, InGaAsP,
Of course, it is also possible to use a compound semiconductor such as InP.
本発明の構造の最も基本となる領域を第１図と第３図の
実施例によシ説明したが、実際に電圧。Although the most basic area of the structure of the present invention has been explained using the embodiments shown in FIGS.
電流を印加して動作させる時は、第２図のととく４のエ
ミッタ領域の上に１”ＧａＡｓ層４′を設けその上にＡ
ｕＧｅ／Ｎｉ等のオーミック電極４′を付追してエミッ
タ電極を構成し、ベース７のベース電極は、ベース７の
５の領域までエミッタ４の一部の領域に窓開けして、そ
の部分にＣｒ／Ａｕ等のオーミック電極７′を付加し、
コレクタ電極としては、８のｎ−ＧａＡｓ領域まで、４
，７の領域の一部に窓開けして、その部分にｊ、、ｕＧ
ｅ／Ｎｉ等のオーミック電極８′を付加して、それぞれ
４’、 ７’ 、 ８’をエミッタ、ベース。When operating by applying a current, a 1" GaAs layer 4' is provided on the emitter region 4 in FIG.
An ohmic electrode 4' such as uGe/Ni is added to form an emitter electrode, and the base electrode of the base 7 is formed by opening a window in a part of the emitter 4 up to the area 5 of the base 7, and forming a window in that part. Adding an ohmic electrode 7' such as Cr/Au,
As a collector electrode, up to 8 n-GaAs regions, 4
A window is opened in a part of the area of ,7, and j,,uG is placed in that part.
Add ohmic electrodes 8' such as e/Ni, and use 4', 7', and 8' as emitter and base, respectively.
コレクタ端子として電源を接続して利用するものである
。なお、９は半絶縁性のＧａＡｓ基板である。It is used as a collector terminal by connecting a power supply. Note that 9 is a semi-insulating GaAs substrate.
また、ペース電極の低抵抗化のためには、Ｃｒ／Ａｕを
付着する前にその部分にＰ型の不純物たとえばＢｅ等を
イオン注入することなども有効な手段である。これらの
本発明の基本構成部分に付属する部分は、従来のへテロ
接合バイポーラトランジスタですでに一般的に利用され
ている技術であるので、ここでの詳しい説明は省略する
。Furthermore, in order to reduce the resistance of the pace electrode, it is also effective to ion-implant P-type impurities such as Be into the part before depositing Cr/Au. These parts attached to the basic constituent parts of the present invention are technologies already commonly used in conventional heterojunction bipolar transistors, so a detailed explanation will be omitted here.
以上、本発明によれば、従来のへヴロ接合ノくイボーラ
トランジスタのベース抵抗の低減の限界以上にベース抵
抗を低くできるから、従来にない超高速トランジスタが
実現でき、レコ秒（１０１２秒）／ゲート領域の論理Ｉ
Ｃや記憶ＩＣ，また１０ＧＨｚ以上の増幅器や発振器の
構成要素として広範囲な応用分野がある。As described above, according to the present invention, the base resistance can be lowered beyond the limit of base resistance reduction of the conventional Hevro junction Ibora transistor, and an unprecedented ultra-high speed transistor can be realized. )/gate area logic I
It has a wide range of applications as a component of C and memory ICs, as well as amplifiers and oscillators of 10 GHz or higher.
第１図は本発明のへテロ接合バイポーラトランジスタの
実施例のバンドギャップ図、
第２図は本発明のへテロ接合パイボーラド／ヲ゛／ジメ
タの実施例の断面図、
第３図は本発明のへテロ接合ノくイボーラトランジスタ
の実施例の要部断面図、
第４図は従来のへテロ接合ノくイボーラトランジスタの
断面図。
（主な符号）
１− Ｎ −ＡｌＧａＡｓ （エミッタ領域）、２・・
４’−ＧａＡｓ（ペース領域）、 ａ −ｎ −ＧａＡ
ｓ （コレクタ領域）、４ ・＝ Ｎ −ｋｌｘｌＧａ
ｌ−ＸＩＡＳ （エミッタ領域）、５− Ｐ−ＧａＡｓ
ｓ ６− Ｐ−Ａ７！ｘ２Ｇａｔ−ｘ２Ａａ ％ ７
−ペース領域、８・・・ｎ−ＧａＡｓ（コレクタ領域）
、９・・・半絶縁性ＧａＡｓ基板。
特許出願人 日本電信電話公社
代理人弁理士 玉 蟲 久 五 部（外２名）第 １
図
第２図
、 ｒｒFIG. 1 is a bandgap diagram of an embodiment of a heterojunction bipolar transistor of the present invention, FIG. 2 is a sectional view of an embodiment of a heterojunction bipolar transistor of the present invention, and FIG. 3 is a cross-sectional view of an embodiment of a heterojunction bipolar transistor of the present invention. FIG. 4 is a cross-sectional view of a conventional heterojunction Ibora transistor. (Main symbols) 1-N-AlGaAs (emitter region), 2...
4'-GaAs (pace region), a-n-GaA
s (collector region), 4 ・= N −klxlGa
l-XIAS (emitter region), 5-P-GaAs
s6-P-A7! x2Gat-x2Aa% 7
- Pace region, 8...n-GaAs (collector region)
, 9... Semi-insulating GaAs substrate. Patent Applicant Nippon Telegraph and Telephone Public Corporation Patent Attorney Hisashi Tamamushi Department 5 (2 others) 1st
Figure 2, rr
Claims (2)
導体層と高不純゛物濃度で第１の半導体より大きい禁制
帯幅を有する第２の半導体からなる第２の半導体層をそ
れぞれ少なくとも１層以上有する半導体層全ベース領域
とし、エミッタ領域丘第２の半導体よりもさらに大きな
禁制帯幅を有し、第２０半導体の伝導型と反対の伝導型
である第３の半導体からなる第３の半導体層とすること
ｅ＊徴とするヘテロ接合バイポーラトランジスタ。(1) At least a first semiconductor layer made of a first semiconductor with a low impurity concentration and a second semiconductor layer made of a second semiconductor with a high impurity concentration and a bandgap larger than that of the first semiconductor. A third semiconductor layer comprising one or more semiconductor layers, the entire base region of which is an emitter region, a third semiconductor having a larger forbidden band width than the second semiconductor, and having a conductivity type opposite to that of the twentieth semiconductor. A heterojunction bipolar transistor having an e* characteristic as a semiconductor layer.
ａＡｓ 、第２の半導体ｆ ０．５〜５ Ｘ １０１１
０ｌ９” のＰ型不純物をドープしたＡＡｘ２Ｇａ＋−
ｘ２Ａｓ （０，３≧Ｘ２≧０．１）、第３の半導体を
ｎ型のＡＪｘＩＧａｚ−ｘＩＡｓ（Ｘｌ＞０．３） と
し、第１．第２の半導体層の厚さを１０Ａ以上３００八
以下とすることを特徴とする特許請求の範囲第１項記載
のへテロ接合バイポーラトランジスタ。(2) P-type G in which the first semiconductor is not doped with impurities
aAs, second semiconductor f 0.5~5 x 1011
AAx2Ga+- doped with P-type impurity of 0l9”
x2As (0,3≧X2≧0.1), the third semiconductor is n-type AJxIGaz-xIAs (Xl>0.3), and the first. 2. The heterojunction bipolar transistor according to claim 1, wherein the thickness of the second semiconductor layer is 10A or more and 300A or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59098091A JPS60242671A (en) | 1984-05-16 | 1984-05-16 | heterojunction bipolar transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59098091A JPS60242671A (en) | 1984-05-16 | 1984-05-16 | heterojunction bipolar transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60242671A true JPS60242671A (en) | 1985-12-02 |
| JPH0543178B2 JPH0543178B2 (en) | 1993-06-30 |
Family
ID=14210668
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59098091A Granted JPS60242671A (en) | 1984-05-16 | 1984-05-16 | heterojunction bipolar transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60242671A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0273363A2 (en) * | 1986-12-22 | 1988-07-06 | Nec Corporation | Heterojunction bipolar transistor with ballistic operation |
| JPS63260064A (en) * | 1986-08-01 | 1988-10-27 | テキサス インスツルメンツ インコ−ポレイテツド | 3D bipolar wafer and process |
| US4797722A (en) * | 1986-05-23 | 1989-01-10 | U.S. Philips Corporation | Hot charge-carrier transistors |
| US4979009A (en) * | 1987-06-08 | 1990-12-18 | Hitachi, Ltd. | Heterojunction bipolar transistor |
| WO2004040652A1 (en) * | 2002-10-30 | 2004-05-13 | International Business Machines Corporation | Bipolar transistor having a base region with a constant bandgap layer and a graded bandgap layer |
| WO2012102196A1 (en) * | 2011-01-24 | 2012-08-02 | Ｎｔｔエレクトロニクス株式会社 | Semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58114455A (en) * | 1981-12-28 | 1983-07-07 | Nec Corp | semiconductor equipment |
-
1984
- 1984-05-16 JP JP59098091A patent/JPS60242671A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58114455A (en) * | 1981-12-28 | 1983-07-07 | Nec Corp | semiconductor equipment |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4797722A (en) * | 1986-05-23 | 1989-01-10 | U.S. Philips Corporation | Hot charge-carrier transistors |
| JPS63260064A (en) * | 1986-08-01 | 1988-10-27 | テキサス インスツルメンツ インコ−ポレイテツド | 3D bipolar wafer and process |
| EP0273363A2 (en) * | 1986-12-22 | 1988-07-06 | Nec Corporation | Heterojunction bipolar transistor with ballistic operation |
| US4929997A (en) * | 1986-12-22 | 1990-05-29 | Nec Corporation | Heterojunction bipolar transistor with ballistic operation |
| US4979009A (en) * | 1987-06-08 | 1990-12-18 | Hitachi, Ltd. | Heterojunction bipolar transistor |
| WO2004040652A1 (en) * | 2002-10-30 | 2004-05-13 | International Business Machines Corporation | Bipolar transistor having a base region with a constant bandgap layer and a graded bandgap layer |
| US7170112B2 (en) | 2002-10-30 | 2007-01-30 | International Business Machines Corporation | Graded-base-bandgap bipolar transistor having a constant—bandgap in the base |
| WO2012102196A1 (en) * | 2011-01-24 | 2012-08-02 | Ｎｔｔエレクトロニクス株式会社 | Semiconductor device |
| JP2012156206A (en) * | 2011-01-24 | 2012-08-16 | Ntt Electornics Corp | Semiconductor device |
| CN103403848A (en) * | 2011-01-24 | 2013-11-20 | Ntt电子股份有限公司 | Semiconductor device |
| US8754445B2 (en) | 2011-01-24 | 2014-06-17 | Ntt Electronics Corporation | Semiconductor device |
| CN103403848B (en) * | 2011-01-24 | 2016-02-24 | Ntt电子股份有限公司 | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0543178B2 (en) | 1993-06-30 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |