JPS62293644A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To implement high density of minute interconnections, by embedding a first resin film in a recess part in the vicinity of a lower metallic interconnection layer at an opening part of a second light sensitive resin film. CONSTITUTION:A lower Al interconnection layer 3 is formed on a substrate 1 as specified. An SiO2 film 4 is formed on the substrate 1 as an interlayer insulating film. Then, a first photoresist film 5 is applied. Thereafter, the film 5 is etched back untill the surface of the film 4 on the interconnection layer 3 is exposed. A first photoresist film 5a is enbedded and formed at least in a recess part in the vicinity of the interconnection layer 3. Then, a second photoresist film 6 is applied and formed on the substrate 1. A hole, which is wider than the width of the interconnection, is formed only on the interconnection layer 3. With the film 6 as a mask, the film 4 undergoes RIE. Then, a connecting through hole 7 can be formed. After the films 5a and 6 are removed, a specified upper Al interconnection layer 8, which is connected to the through hole 7, is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION 3. Detailed Description of the Invention Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a high-density semiconductor device having multilayer wiring.

2. Description of the Related Art In recent years, semiconductor devices, such as ICs, have been becoming more and more highly integrated, and elements and interconnections have become smaller and denser, and interconnections have become more multilayered.

In particular, there is a demand for the development of a method for manufacturing multilayer wiring that can improve yield without reducing the reliability of ICs even when fine wiring is multilayered.

A conventional method for manufacturing multilayer wiring will be explained with reference to FIG. In FIG. 3, 11 is a Si substrate, 12 is a SiO
2 film, 13 is a lower layer Ad wiring, 14 is a CVD-5in2 film, 15 is a through hole for connection, and 16 is an upper layer Al wiring.

SiO□ is applied to the S1 substrate 11 on which each element has already been formed.
After forming a total of 12 films 12 and depositing an A1 layer on the Si substrate 11, a predetermined lower layer uneven wiring 13 and a wiring connection pad portion 13a (a part of the lower layer uneven wiring) are formed using photoetching technology. (Figure 3 person) After that, the CVD method or plasma CVD method is applied to the Si substrate 111C8i0.
2 film 14 is formed to cover it (FIG. 3B). Then, the lower layer All wiring buff part 13I! is made using photoetching technology! A predetermined connection through hole 15 is opened in the SiO2 film 14 on the L. Here, the dimensions of the pad portion 13fL must be wider than those of the through hole 16 by an amount of alignment allowance. In addition, with the progress of miniaturization of wiring, through holes 15
is formed by anisotropic dry etching (hereinafter referred to as RIB), and becomes a vertical hole with a large aspect ratio (third hole).
Figure C). FIG. 3C is a sectional view taken along the line B-B' in FIG. 4. Thereafter, after depositing the A1 layer on the Si substrate 11, the upper layer mulch wiring 16 is formed using photoetching technology, and the IC is completed (FIG. 3D).

Problems to be Solved by the Invention In the IC manufactured in this way, as shown in FIG.
Here, FIG. 4 is a schematic plan view of the IC in FIG. 3C), since the dimensions of the pad portion 13a of the lower layer Al wiring are wider than the dimensions of the through hole 16, the wiring pitch of the lower layer Al wiring is reduced. There is a limit to this, and this becomes an obstacle to increasing the density of wiring. In addition, as shown in the third diagram, the through hole 15
Since the hole is vertical and has a large aspect ratio, it is difficult for upper-level people to
In the formation of the wiring 16, the step coverage of the upper layer Ad wiring 16 at the stepped portion of the hole deteriorates, and step breakage is likely to occur, which becomes an obstacle to miniaturization of the wiring.

The present invention was made in view of such conventional problems, and aims to provide a method for manufacturing a high-density IC that can form connection through holes equal to the wiring width of the lower layer Ad wiring using a simple manufacturing method. It is said that

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention forms an interlayer insulating film on a semiconductor substrate on which a lower metal wiring is formed, and then insulates the recess at least in the vicinity of the lower metal wiring. After the first resin film is buried and formed, a second photosensitive resin film is formed with openings in a predetermined area on the lower metal wiring, and the interlayer insulating film exposed in this opening is etched to form connection through holes. It is something.

According to the above-described structure, the first resin film is embedded in the recess near the lower metal wiring in the opening of the second photosensitive resin film, so that when the exposed interlayer insulating film is etched, Connection through-holes having a width equal to the wiring width of the lower layer metal wiring are formed in a self-aligned manner.

Embodiment An embodiment of the present invention will be described with reference to FIG. In Fig. 1, 1 is a Si substrate, 2 is a SiO2 film, 3 is a lower layer Ad wiring, 4 is an OV D-5in2 film, 6 is a first photoresist film, 6 is a second photoresist film, and 7 is a through hole for connection. Hole 8 is an upper layer Ag wiring.

First, an S-engineered substrate 1 on which each element (not shown) has already been formed.
After forming a SiO2 film 2 to cover the Si substrate 1 and depositing an aluminum layer 4 (aluminum) as a lower layer interconnection by sputtering on this Si substrate 1, a predetermined lower layer interconnection 3 is formed using a photoetching technique. Figure 1). And this S
A 5102 film 4 is formed as an interlayer insulating film on the i-substrate 1 by CVD or plasma CVD (FIG. 1B).

Next, for example, a first resin film is applied on this Si substrate 1.
A photoresist film 6 is coated and formed. Here, this first
It is desirable that the photoresist film 5 is flat in the vicinity of the lower layer wiring 3 (FIG. 1C). Then this S
The i-substrate 1 is subjected to RIE in an oxygen atmosphere, and the first photoresist film 6 is etched back until the surface of the 5i02 film 4 on the lower layer interconnection 3 is exposed. In this way, the first photoresist film 5a can be embedded at least in the recessed portion near the lower layer interconnection 3 (FIG. 1D).

Next, for example, a second photoresist film 6 is coated as a photosensitive resin film on this Si substrate 1, and an opening is made wider than the wiring width only above a predetermined lower layer wiring 3 (FIG. 1E).
. After that, using the second photoresist film 6 as a mask, for example, C.
The Si02 film 4 is subjected to RIE in an HF gas atmosphere. In this way, in the opening of the second photoresist film 6, the lower layer A
Since the first photoresist film 5& is buried in the recess near the d-wiring 3, the connecting through-hole 7 can be formed by etching away only the exposed SiO2 film 4 (FIG. 1F). FIG. 1F shows a cross section taken along line A--A' in FIG.

After that, the first and second photoresist films 5a are formed.

6 is removed by ashing (Fig. 1G).

Next, after depositing an A1 layer as an upper layer wiring on this Si substrate 1 by a sputtering method, a predetermined upper layer wiring 8 to be connected to the through hole 7 is formed using a photoetching technique.
The IC of this example is completed (Fig. 1H).
.

In the Xa multilayer wiring manufactured in this way, as shown in FIG. 2 (here, FIG. 2 is a schematic plan view of the IC in FIG. 1F), the width of the through hole 7 is The first photoresist film 5 is buried in the recess near the wiring 3! Since the wiring width becomes equal to the wiring width of the lower layer A7 wiring 3 in a self-aligned manner due to L, there is no need to provide a pad portion wide enough for alignment margin as in the conventional case, and the wiring pitch of the lower layer uneven wiring can be reduced.

Moreover, as shown in FIG. In the formation of the through hole 7, the upper layer uneven wiring 8 does not break, so even if the wiring is miniaturized, the I
C reliability and yield will not be lowered.

In this embodiment, the first photoresist film 5 is used as the resin film, but this may be a resin film made of another organic material such as a polyimide film. In addition, the interlayer insulating film was a SiO2 film 4, but this could be a PSG film or a SiO2 film.
This effect can be obtained even with a 5kT 4 film, etc.
Not even.

Effects of the Invention As described above, according to the method of manufacturing a semiconductor device of the present invention, a through hole for connection can be opened in a self-aligned manner by embedding a resin film in the recess near the lower layer kl wiring. This makes it possible to increase the density of fine wiring in a semiconductor device with multilayer wiring.

[Brief explanation of the drawing]

Figures 1-H are process sectional views for explaining the manufacturing method of IC in one embodiment of the present invention, Figure 2 is a schematic plan view of the IC in Figure 1F, and Figure 3 is a conventional IC. FIG. 4 is a schematic plan view of the IC in FIG. 3C. DESCRIPTION OF SYMBOLS 1...Semiconductor substrate, 3...Lower metal wiring, 4...Interlayer insulating film, 6...Resin coating, 6...Photosensitive Polymer resin coating, °γ・・・・・・
Connection through hole, 8... Upper layer metal wiring. Name of agent: Patent attorney Toshio Nakao and 1 other person/
--SL board 4 --- 5L (h Clothes (C) 5 Sheet Δ Figure-g c l-edge 2 Figure 2 8- Lower layer Al arrangement 7-s cleaning Slray water-le Figure 4 ＞ → °gu 1 Q 6

Claims (2)

[Claims] (1) A step of forming a lower metal wiring on one main surface of a semiconductor substrate, a step of providing an interlayer insulating film on the semiconductor substrate, and a step of forming a first resin coating in a recess at least near the lower metal wiring. a step of providing a second photosensitive resin film with an opening in a predetermined region on the lower metal wiring, and a step of etching the interlayer insulating film exposed in the opening of the second photosensitive resin film for connection. 1. A method for manufacturing a semiconductor device, comprising the steps of: forming a through-hole for the semiconductor device; and forming an upper layer metal wiring connected to the through-hole. (2) In the step of providing a resin film, the resin film is applied and formed on the semiconductor substrate, and then the semiconductor substrate is subjected to reactive ion etching in an oxidizing atmosphere to embed the resin film in the recessed portion. A method for manufacturing a semiconductor device according to item 1.