JPS6229238A - Transmitter receiver for start-stop serial data - Google Patents

Abstract

PURPOSE:To simplify a constitution and to improve the convenience for usage by using a counter to count the number of sampling pulses in a start bit width, discriminating a Baud rate and outputting a Baud rate clock pulse from a frequency divider based on the result of discrimination. CONSTITUTION:In receiving a data RD, the leading of a start bit 9a sent at the beginning of the data RD is detected at first by a detector 11 and the output of the detector 11 activates a counter 12 until the counter is inactivated at the trailing of the start bit 9a to count sampling clock pulses CLK thereby discriminating the Baud rate. Then the output of the counter 12 controls a frequency divider 13 to frequency-divide the sampling clock pulse CLK and a Baud rate clock pulse BCP is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an asynchronous serial data transmitting/receiving device.

[Conventional technology]

FIG. 4 is a block diagram showing a conventional asynchronous serial data transmitting/receiving device.

1 is a data bus buffer, 2 is a read/write control circuit, 3 is a modem control circuit, 4 is a transmit buffer,
5 is a transmit control circuit, 6 is a receive buffer,
7 is a receive control circuit, and these are mutually connected by a bus 8.

[Problem that the invention seeks to solve]

Since the conventional transmitter/receiver is configured as described above,
The data transmission speed may be fixed, or a predetermined transmission speed may be selected and set from several types of transmission speeds using software.

In this case, it is necessary to decide where to sample the data, that is, when to start sampling. Fifth
The figure is an explanatory diagram of how to determine the sampling start time, where a is a data waveform having a start bit 9a at the beginning and a stop bit 9b1 at the end, and b is a sampling pulse waveform.

As is clear from the figure, the width of the start pitch (9a) sent at the beginning of the data is already known.

There is a problem in that it is necessary to find 1/2 of this start bit width W, that is, the middle position of the start bit width W, and start sampling from this middle position.

This invention was devised to solve the above-mentioned problems, and its purpose is to provide an asynchronous serial data transmitter/receiver that can automatically determine the transmitter's port rate and receive data. shall be.

Precautions to Solve Problem C] The asynchronous serial data transmitting/receiving device according to the present invention includes a counter that counts the number of sampling pulses within the start bit width and determines the porate rate, and a counter that determines the porate rate based on the output of this counter. It has a frequency divider that outputs a porate clock pulse.

[Effect]

In the transmitting/receiving device according to the present invention, the porate is determined by counting the number of sampling pulses within the start bit width with a counter, and the porate clock pulse is outputted from the frequency divider based on the result of this determination.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, the same parts as in FIG. 4 are given the same reference numerals, and 10 is a sampling control circuit.

FIG. 2 is a block diagram showing an example of the sampling control circuit 1o, in which 11 inputs the received data RD (FIG. 3 a) and the sampling clock pulse CLK (?: Jc3 FIG. b), and inputs the received data RD. Detector for detecting rising edge, 1
2 is the sampling clock pulse CLKi count within the width of the start bit 9a based on the output of the detector 11 (
The counter 13 shown in FIG. 3C is a frequency divider which divides the frequency of the sampling clock pulse CLK' based on the output of the counter 12 and outputs the porate clock pulse BCP.

Next, the operation will be explained. When receiving data RD, first, the detector 11 detects the rising edge of the start bit 9a sent at the beginning of this data RD, and
The counter 12 is activated by the output of the detector 11 until it becomes inactive at the falling edge of a, and the sampling clock pulse CLK is counted to determine the porate. The frequency divider 13 is controlled by the output of the counter 12 to divide the frequency of the sampling clock pulse CLK and output a porate clock pulse BCP.

〔Effect of the invention〕

As described above, according to the present invention, the porate rate of received data is automatically determined and the porate clock pulse is output based on the determination result, so that the porate setting means or the sampling start time can be determined. No operation required.

This has the effect of providing an asynchronous serial data transmitting/receiving device that has a simple configuration and is easy to use.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an asynchronous serial data transmission/reception device according to an embodiment of the present invention, FIG. 2 is a block diagram of a sampling control circuit, FIG. 3 is a signal waveform diagram of each part of FIG. 2, and FIG. 4 5 is a block diagram of a conventional asynchronous serial data transmitting/receiving device, and FIG. 5 is an explanatory diagram of determining sampling start timing. 12 is a counter, 13 is a frequency divider, CLK is a sun 7'I
J song clock pulse, 90L is start focus, BC
P is porate clog pulse. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Patent Applicant Mitsubishi Electric Co., Ltd. Agent Patent Attorney 1) Hiroshi Sawa (2 others) 2nd @ 9o Nisdart Got

Claims (1)

[Claims] A counter that receives a start bit sent at the beginning of data and counts sampling clock pulses input within the width of the start bit to determine the port rate of the transmitter, and a counter that determines the sampling clock pulse based on the output of this counter. An asynchronous serial data transmitter/receiver equipped with a frequency divider that divides the frequency and outputs a porate clock pulse.