JPS62291062A - Manufacture of thin film transistor - Google Patents
Manufacture of thin film transistorInfo
- Publication number
- JPS62291062A JPS62291062A JP61132821A JP13282186A JPS62291062A JP S62291062 A JPS62291062 A JP S62291062A JP 61132821 A JP61132821 A JP 61132821A JP 13282186 A JP13282186 A JP 13282186A JP S62291062 A JPS62291062 A JP S62291062A
- Authority
- JP
- Japan
- Prior art keywords
- drain electrode
- electrode
- island
- source electrode
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000010409 thin film Substances 0.000 title claims description 9
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 229910052751 metal Inorganic materials 0.000 claims abstract description 3
- 239000002184 metal Substances 0.000 claims abstract description 3
- 239000010408 film Substances 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 5
- 238000007796 conventional method Methods 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910001120 nichrome Inorganic materials 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
Landscapes
- Liquid Crystal (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
3、発明の詳細な説明
(産業上の利用分野)
この発明は、信頼性の高い薄膜トランジスタ(以下TP
Tと略す)の製造方法に関する。[Detailed Description of the Invention] 3. Detailed Description of the Invention (Field of Industrial Application) This invention provides a highly reliable thin film transistor (hereinafter referred to as TP).
(abbreviated as T).
(従来の技術)
第3図は従来のTPTの要部の平面図であり、第4図は
このTPTの断面図である。両図のA。(Prior Art) FIG. 3 is a plan view of the main parts of a conventional TPT, and FIG. 4 is a sectional view of this TPT. A in both figures.
A′、c 、 c’は互いに対応している。この第3図
、第4図によシ、従来のTPTの製造方法について述べ
る。A', c, and c' correspond to each other. Referring to FIGS. 3 and 4, a conventional TPT manufacturing method will be described.
この第3図、第4図に示すごとく、透光性絶縁物基板1
上に、ニクロム(NjCr) 、タングステン(W)。As shown in FIGS. 3 and 4, a transparent insulating substrate 1
On top, nichrome (NjCr) and tungsten (W).
モリブデン(Mo) 、クロム(cr )などよりなる
金属層を200〜1000^の厚みで真空蒸着法または
スパッタ法により被着形成し、所定のパターンに加工し
てゲート電極2を形成する。A metal layer made of molybdenum (Mo), chromium (Cr), etc. is deposited to a thickness of 200 to 1000 mm by vacuum evaporation or sputtering, and processed into a predetermined pattern to form the gate electrode 2.
その上に、ゲート絶縁膜3となるシリコン窒化膜(Si
Nx)をNH3と5IH4を主成分ガスとして、グロー
放電法により、0.3μm −0,5μmの膜厚で堆積
させる。On top of that, a silicon nitride film (Si
Nx) is deposited to a film thickness of 0.3 μm to 0.5 μm by a glow discharge method using NH3 and 5IH4 as main component gases.
さらに、その上に活性ノー4となるアモルファスシリコ
ン膜k SiH4ガスのグロー放電法により0.1〜0
.2μm堆積したのち、TPTとなる部分以外は加工し
、除去して島状にノゼターンニングして、ゲート絶縁膜
3と活性層4を形成する。Furthermore, on top of that, an amorphous silicon film with an active level of 0.1 to 0.0
.. After depositing 2 μm, the portion other than the portion that will become TPT is processed, removed, and nose-turned into an island shape to form a gate insulating film 3 and an active layer 4.
次に、ドレイン電極5.ソース電極6となる0、5〜1
.0μmの厚みのアルミ(ロ)層iAZの真空蒸着法と
加工によシ形成することで、TPTが完成する。Next, the drain electrode 5. 0, 5 to 1, which becomes the source electrode 6
.. The TPT is completed by forming an aluminum (b) layer iAZ with a thickness of 0 μm by vacuum evaporation and processing.
このTPTは、その後ソース電極6に接続するように透
明電極7を形成し、TPTと透明電極を2次元に配置す
ると、液晶表示装置のTFTアレイとして利用される。This TPT is then used as a TFT array of a liquid crystal display device by forming a transparent electrode 7 so as to be connected to the source electrode 6, and arranging the TPT and the transparent electrode two-dimensionally.
(発明が解決しようとする問題点)
しかしながら、このような従来のTPTの製造方法では
、ゲート絶縁膜3および活性M4の薄膜による0、4〜
0.7μmの段差B(第4図)のため、M層のスラップ
カバレージが悪く、ドレイン電極5が加工時に、第3図
、第4図のC、C’で示すように断線しやすいという問
題点があった。(Problems to be Solved by the Invention) However, in such a conventional TPT manufacturing method, the thin film of the gate insulating film 3 and the active M4
Due to the 0.7 μm step B (Figure 4), the slap coverage of the M layer is poor, and the drain electrode 5 is prone to disconnection as shown by C and C' in Figures 3 and 4 during processing. There was a point.
これを防止するためには、前記ドレイン電極幅5を広く
するなどが考えられるが、これらはTPT素子自体の寸
法を大きくしてしまう。したがって、高密度にTPTを
配置してTPTパネルを作成することは困難となる。In order to prevent this, it is conceivable to increase the width of the drain electrode 5, but this increases the size of the TPT element itself. Therefore, it is difficult to create a TPT panel by arranging TPT at high density.
この発明は、前記従来技術がもっている問題点のうち、
ドレイン電極が断線し易い点と、高密度にTPTを配置
することが困難である点について解決した薄膜トランジ
スタの製造方法全提供するものである。This invention solves the problems of the above-mentioned prior art.
The present invention provides a complete method of manufacturing a thin film transistor that solves the problems of the drain electrode being easily disconnected and the difficulty of arranging TPTs in a high density.
(問題点を解決するための手段)
この発明は、薄膜トランジスタの製造方法において、ド
レイン電極またはソース電極が接するTFTO島部分の
形状をカギ型またはジグザグ型に加工したのちドレイン
電極を形成する工程を導入したものである。(Means for Solving the Problems) The present invention introduces a step of forming a drain electrode after processing the shape of the TFTO island portion in contact with the drain electrode or the source electrode into a hook shape or a zigzag shape in a method for manufacturing a thin film transistor. This is what I did.
(作 用)
この発明によれば、薄膜トランジスタの製造方法におい
て、以上のような工程を導入したので、ドレイン電極が
接するTFTの島をカギ型またはジグザグ型に形成した
のち、ドレイン電極またはソース電極を島の上に重ねて
形成し、重ね合わせた部分の段差の長さを長くし、エツ
チング液がステップ部に入りにくくなるように作用し、
したがって、前記問題点を除去できる。(Function) According to the present invention, the above-described steps are introduced in the method for manufacturing a thin film transistor, so that after forming the island of the TFT in contact with the drain electrode in a key shape or a zigzag shape, the drain electrode or the source electrode is formed. It is layered on top of the island, increases the length of the step at the overlapped part, and acts to make it difficult for etching liquid to enter the step.
Therefore, the above problem can be eliminated.
(実施例〕
以下、この発明の薄膜トランジスタの製造方法の実施例
について図面に基づき説明する。第1図はその一実施例
を説明するためのTPTの要部平面図である。(Example) Hereinafter, an example of the method for manufacturing a thin film transistor of the present invention will be described with reference to the drawings. Fig. 1 is a plan view of the main part of a TPT for explaining one example.
この第1図において、第3図、第4図と同一部分には同
一符号を付して述べる。第1図において、従来技術を用
いて、透光性絶縁物基板上にゲート電極2を形成し、こ
のゲート電極2上にゲート絶縁膜3と活性層4を順次堆
積する。In FIG. 1, the same parts as in FIGS. 3 and 4 will be described with the same reference numerals. In FIG. 1, a gate electrode 2 is formed on a transparent insulating substrate using a conventional technique, and a gate insulating film 3 and an active layer 4 are sequentially deposited on the gate electrode 2. As shown in FIG.
次にゲート絶縁膜3と活性層4を加工してTFTO島(
素子分離)を形成する。このとき第1図に示すごとく、
ドレイン電極5が接するTFTO島(a −Si /S
iNx )部分の形状をカギ型(第1図10と11)に
加工する。Next, the gate insulating film 3 and active layer 4 are processed to form TFTO islands (
element isolation). At this time, as shown in Figure 1,
A TFTO island (a-Si/S
iNx ) portion is shaped into a key shape (FIG. 1 10 and 11).
このかぎ型10.11の加工法はレジストをマスクにし
てCFJ十02などのガスを用いたプラズマエツチング
により容易に行える。This method of processing the hook shapes 10 and 11 can be easily performed by plasma etching using a gas such as CFJ 102 using a resist as a mask.
このように、カギ型10.11の加工を行ったのち、再
び従来技術を用いてドレイン電極5.ソース電極6を被
着し、加工することによ、pTFTが完成する。After processing the key shape 10.11 in this way, the drain electrode 5.1 is processed again using the conventional technique. A pTFT is completed by depositing and processing the source electrode 6.
TFTの島部分の形状を部分的にカギ型にして、カギ型
の上にドレイン電極を重ね合せて形成した理由は、
(1)重ね合せ部の段差の長さが、従来(直線状)よυ
も長くなること、
(2) カギ型にしてコーナを作ることで、エツチン
グ液が、ステップ部に入シにくくなること、である。The reason why the shape of the island part of the TFT is partially made into a key shape and the drain electrode is overlaid on the key shape is as follows: (1) The length of the step at the overlapping part is longer than that of the conventional (straight line). υ
(2) By making the corner into a key shape, it becomes difficult for the etching solution to enter the step part.
その後、このTPTは従来技術と同様にして、透明電極
7′f:形成し、TPTと透明電極7全2次元に配置す
ると、液晶表示装置のTFTアレイとして利用される。Thereafter, transparent electrodes 7'f: are formed on this TPT in the same manner as in the prior art, and when the TPT and transparent electrodes 7 are arranged in two dimensions, it is used as a TFT array of a liquid crystal display device.
また、上述のカギ型のかわりに、第2図に示すようにジ
グザグ型12.13を用いても同様の効果が得られる。Moreover, the same effect can be obtained by using a zigzag shape 12, 13 as shown in FIG. 2 instead of the above-mentioned key shape.
(発明の効果)
以上、詳細に説明したように、この発明によれば、ドレ
イン電極またはソース′ぼ極が接するTFTの島部分の
形状をカギ型またはジグザグ型に加工したのち、ドレイ
ン電極またはソース電極をその部分に重ね合せて形成し
たので、加工時に断線するという問題点を解決すること
ができ、したがって、ドレイン電極およびソース電極の
断線がない信頼性の高いTPT=に歩留りよく製造する
ことが可能となる。(Effects of the Invention) As described in detail above, according to the present invention, after processing the shape of the island portion of the TFT that is in contact with the drain electrode or the source' polarity into a key shape or a zigzag shape, Since the electrode is formed by overlapping that part, it is possible to solve the problem of disconnection during processing, and therefore, it is possible to manufacture highly reliable TPT with high yield without disconnection of the drain electrode and source electrode. It becomes possible.
第1図はこの発明の薄膜トランジスタの製造方法の一実
施例を説明するための要部の平面図、第2図はこの発明
方法の他の実施例を説明するための要部の平面図、第3
図は従来の6i膜トランジスタの装造方法全説明するた
めの要部の平面図、第4図は従来方法を説明するための
要部の断面図である。
2・・・ゲートぼ極、3・・・ゲート絶縁膜、4・・・
活性層、5・・・ドレイン電極、6・・・ンース′五極
、7・・・透明電極、10.11・・・カギ型、12.
13・・・ジグザグ型。
第 1 図′FIG. 1 is a plan view of essential parts for explaining one embodiment of the method for manufacturing a thin film transistor of the present invention, and FIG. 2 is a plan view of essential parts for explaining another embodiment of the method of the present invention. 3
The figure is a plan view of the main parts for explaining the entire method of manufacturing a conventional 6i film transistor, and FIG. 4 is a sectional view of the main parts for explaining the conventional method. 2... Gate polarity, 3... Gate insulating film, 4...
Active layer, 5...Drain electrode, 6...Nose' pentode, 7...Transparent electrode, 10.11...Key shape, 12.
13... Zigzag type. Figure 1'
Claims (1)
極を形成する工程と、 (b)上記ゲート電極上に絶縁膜および活性層を順次堆
積する工程と、 (c)上記ゲート絶縁膜および活性層をドレイン電極ま
たはソース電極と接する部分をかぎ型またはジグザグ型
に加工してトランジスタの島を形成する工程と、 (d)上記島状にドレイン電極およびソース電極を被着
する工程と、 よりなる薄膜トランジスタの製造方法。[Claims] (a) A step of depositing a metal layer on a transparent insulating substrate to form a gate electrode; (b) A step of sequentially depositing an insulating film and an active layer on the gate electrode. (c) processing the portion of the gate insulating film and the active layer in contact with the drain electrode or the source electrode into a hook shape or zigzag shape to form a transistor island; (d) forming the drain electrode and the island in the island shape; A method for manufacturing a thin film transistor, comprising a step of depositing a source electrode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61132821A JPS62291062A (en) | 1986-06-10 | 1986-06-10 | Manufacture of thin film transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61132821A JPS62291062A (en) | 1986-06-10 | 1986-06-10 | Manufacture of thin film transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62291062A true JPS62291062A (en) | 1987-12-17 |
Family
ID=15090348
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61132821A Pending JPS62291062A (en) | 1986-06-10 | 1986-06-10 | Manufacture of thin film transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62291062A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0220830A (en) * | 1988-07-08 | 1990-01-24 | Sharp Corp | Thin film transistor array |
JP2002122885A (en) * | 2000-10-18 | 2002-04-26 | Nec Corp | Liquid crystal display device |
-
1986
- 1986-06-10 JP JP61132821A patent/JPS62291062A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0220830A (en) * | 1988-07-08 | 1990-01-24 | Sharp Corp | Thin film transistor array |
JP2002122885A (en) * | 2000-10-18 | 2002-04-26 | Nec Corp | Liquid crystal display device |
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