JPS62290233A - Transmission right taking over system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a system for taking over transmission rights between a plurality of communication devices connected in a loop. .

[Conventional technology]

LAN (Local Area N@work),
In various on-premises control equipment, etc., as proposed in Japanese Patent Application No. 59-260800 filed separately by the present applicant, transmission lines are used to connect multiple communication devices that transmit and receive data. After establishing a connection, the direction of data signal transmission is determined, and when one communication device acquires the transmission right and is transmitting, the other communication device relays the signal received from one transmission path, and the other communication device relays the signal received from one transmission path. When transmitting to a transmission path and acquiring a new transmission right upon completion of transmission, the communication device requesting the transmission right generally uses a token.
), a code indicating the priority of the transmission right is added to the transmission right request signal and transmitted, and the one in each communication device with the higher priority acquires the transmission right.

[Problem that the invention seeks to solve]

However, in the past, in order to ensure transmission right handover, a takeover signal, etc. is transmitted and received in addition to the transmission right request signal9, which requires extra transmission time and requires each communication device to receive Judging whether the signal should be relayed and transmitted or should be received by itself, and when receiving a transmission right request signal, deciding whether it should acquire the transmission right or whether it should relay and transmit without acquiring it. This is done after all signals are received, and if relay transmission is to be performed, the time required to make a decision is added to each communication device, creating a problem in which the delay time caused by the decision to transmit the transmission right request signal increases, in particular. ing.

[Means for solving problems]

In order to solve the above-mentioned problem, the present invention is constructed by the following means.

That is, in the above method, the received signal is transmitted with a time delay of at least "i1 bit," and when the self requests the transmission right, the received priority code is compared with the own priority code. Each communication device is equipped with a circuit that transmits its own priority code in place of the received priority code when its own priority is high, and if the communication device already has the transmission right, the received transmission right request signal is In response to this transmission right request signal, a takeover designation signal indicating the next communication device to acquire the transmission right is sent, and after the transmission of this takeover designation signal, the transmission right is relinquished, and each other communication device relays and transmits the takeover designation signal, and then the communication device that acquires the transmission right transmits a confirmation signal after acquiring the transmission right according to the reception of the takeover designation signal, and each other communication device transmits the confirmation signal. In addition to relaying and transmitting, the communication device that has acquired the transmission right is confirmed.

[Effect]

Therefore, due to the hardware circuit provided for each communication device, the reception signal 4 is delayed by only 1 bit, causing it to be relayed and transmitted. When requesting the right to send, if the priority code is higher than the received priority, the priority code after the own priority code is transmitted, and the transmission speed for the 4mm request is increased, while the received request for the right to send If the signal differs from its own, the transmission right is relinquished accordingly, the acquisition of the transmission right is confirmed by a takeover designation signal, and the acquisition status of the transmission right is confirmed by a confirmation signal, and the transmission right is relinquished. The transfer of rights and confirmation of this will become faster and more reliable.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to figures showing examples.

FIG. 2 is a block diagram showing the entire configuration, in which a plurality of communication devices (hereinafter referred to as STA) CEA-cgD are connected to transmission lines 2, -2.
, and in this example, the signal is transmitted in the direction indicated by the arrow. For example, 5TA-CEA acquires the transmission right, and 5T
When transmitting to A-CED, 5TA-CEB
, CGC relays and transmits the received signals.

FIG. 3 is a block diagram showing the details of each 5TA-CE. An interface (hereinafter referred to as I/F) 1b is provided for the main device 1a of the 5TA-CE, and is connected to the receiver RI. One transmission line 2R is connected, and a D-type 7-lip-flop circuit (hereinafter referred to as FFC) 11 is interposed as a delay element between the transmission line 2R and the other transmission line 2S. Reception 4 given from I/F'1b
In response to the clock pulse αX synchronized with the signal SR, the received signal SR given to the data terminal is sequentially held and output Q.
As a result, a delay of 1 bit is given to the reception signal 4, and the signal is transmitted to the transmission path 2S as the transmission signal Ss.

Further, the output Q of the FFC11 is connected to the transmission line 2S via the switch SW, and when the I/F1b generates the control signal S, the switch SW responds to the output of the F'F'C11. Since Q is switched to the transmission output SO of I/Flb and connected to the transmission line 2S, the signal from I/F1b is transmitted to the transmission line 2S.

FIG. 4 is a block diagram showing a specific configuration of the main device 1a, I/F 1b, FFC 11, and switch SW.
Variable memory (hereinafter referred to as RAM) 22, fixed memory (hereinafter referred to as
ROM') 23, bus controller (hereinafter referred to as BCT) 2
4. Serial-parallel converter such as shift register (hereinafter referred to as 5PC)
31, “0” bit deletion circuit (hereinafter referred to as 29) 32,
CRC (Cyclic Redundancy)
ck,) detection circuit (hereinafter referred to as CHD) 33, abort (A
bort, ) ・Idle detection circuit (hereinafter referred to as AAD)
34. CRC signal generation circuit (hereinafter referred to as CRG) 35.
Abort signal generation circuit (hereinafter referred to as ASG > 3 s), parallel-to-serial converter (hereinafter referred to as PSC) 37 such as a shift register,
A “0” bit insertion circuit (hereinafter referred to as ZIS) 38 etc. is provided, and the transmission line 2R and the other reception signals SR to ZEL32 are provided.
Please follow the HDLC procedure such as JISC63B3.
After removing the ゛°° bits, it is made into parallel data in 5PC31 and is given to CPU21 via mother 11j39, and CPU21 reads ROM via BCT24.
23, and while accessing predetermined data to the RAM 22, it makes judgments on received data and control judgments, controls the CRG 35 and ASG 36 as necessary, and provides parallel data transmission data to the psc 37.

Then, the transmission data becomes serial data in the PSC 37, a CRC signal from the CRG 35 is inserted, and the transmission data is transmitted to the ZIS 3 via the transmission circuit (hereinafter referred to as 5SC) 40.
8, the 'o' bit is inserted in ZIS38 according to the OHDLC procedure described above, and an abort signal from ASG3B is inserted when transmission is interrupted as necessary. No.S8
Sent as .

Note that the reception signal is also given to the SR function 34, and the CPU 21 performs predetermined control according to the detection power of this and the output indicating the check result of the CRD 33.
Depending on the conditions, DMA (Di r @c t Me
mor7Access,) by control! 78PC31
The received data from the PSC is directly stored in the RAM 22 via the BCT 24, or the contents of the RAM 22 are directly stored in the PSC.
37.

In addition, ZEL32O output includes 5SC40K1 and 7'
j are applied to the data terminals of the FFC 11, and these outputs Q are applied to the gates 41. ZIS3 via OR gate 42
When the reception is on, the CPU 21 gives a clear signal to the clear terminal CL of the control OFF'C431, 43g, and the FFC43,
.

43 is in the reset state, its output Q is the logical value "Oo", and the A, 'JD gate 44 is turned off, while the output of the inverter 45 is the logical value "1゛°".
Since the 0 gate 41 is in the on state, the signal from the output Q of the FFC 11 is given to the ZIS 38 as in FIG. 3, and this is transmitted as the transmission No. 4 Ss.

In contrast to the above, when the user obtains the transmission right, FFC4
Since the CpU 21 gives the preset signal PSE to the preset terminal PR of 32, the FFC 43□ is set to set the output Q to 1°°, and while the AND gate +44 is turned on, the output of the inverter 45 is set to "O". , the static gate 141 is turned off, the signal from the delay circuit 46 is applied instead of the output Q of the FFC 11 to the input of the ZIS 38 via the gate 44 and the OR gate 42, and this is sent to the transmitter 4.
The mode becomes a transmission mode in which the signal is transmitted to the transmission path 2S as the signal sg.

On the other hand, when the CPU 21 determines that a transmission right request should be made to the PSC 37, it sends "1" indicating the priority of the transmission right.
°゛, “011” to set the transmission right request signal including the code in combination, this content is the clock pulse C
The data is sequentially sent out as serial data in accordance with LK and applied to an exclusive OR (hereinafter referred to as EXOR) gate 47.

That is, if the CPU 21 determines to start receiving the transmission right request signal, the CPU 21 sends the transmission data including the code indicating the priority of the transmission right request to the PSC 3 before receiving the code indicating the priority.
It is designed to be set to 7.

Therefore, when the output of ZEL 32 contains a similar code indicating the received priority, this is what is applied to the other input of XOR gate 47.
2. ZEL32 (7) If the output force is 'o' and the output of PSC3γ is 1°', the output of the P2XOR gate 47 is 1', which is sent to the FF via the arm gate 48.
The clock pulse C43 is applied to the data terminal of C43.
FFC431 is set in response to LK, FFC43s is also set in response to this, and in order to make the output Q 1°°, the R gate 44 is turned on as described above, and the delay is completed by the delay circuit 46. The output of PSC3γ is the transmission number S
It can be sent as s.

The details of these operating conditions will be described later, and the output Q of the FFC43□ and the OR gate 42
The output of is given to the CPU 21 via the bus 39,
Based on these, the CPU 21 determines whether or not its own transmission data set in the PSC 37 has been transmitted.

FIG. 5 (5) shows an example of the contents of a transmission right request signal indicating the above situation. In this case, the signal includes an 8-bit start flag 51, a global code 52 indicating that it should be received by all STAs, Transmission right request code 53, priority code 54, and source code 5 indicating the address of the transmitting STA
5, according to the CRC signal 56 and end flag 57)
In the configuration, when the receiving No. 4 SR is in the state shown in the figure, the priority code 54 indicates "2" in binary notation, and the priority code 54 is added at the source STA which is indicated by the rooooooool J of the source code 55. The selected priority is ■.

On the other hand, the transmission right request signal that the own STA should transmit as the transmission number s5 has the start flag 51, global code 52, transmission right request code 53, and end flag 57 that are the same as the reception number 4 SR. Only the priority code 54, source code 55, and CRC signal 56 are different, and in this example, the priority is "4" in binary, so the priority of reception number 4 is The priority level ■ is high, and the user can request transmission rights preferentially.

Therefore, according to FFC11 in Fig. 4, υ, reception number 4 sR
is delayed by 1 bit, and is transmitted as the transmission signal S8. At the same time, the reception signal 4 SR and the signal from the PSC 37 are compared by the EXOR gate 47, and the start flag 51 to priority code 54 are Since the bits up to the 5th bit are the same, the output of the IEXOR game) 47 remains "0'°," but when it reaches the 6th bit of the priority code 54, the received No. 4 SR is "0" and the output of the 5RG 47 is "0". The output is "1°", the judgment condition that self priority is high is established, and as mentioned above, the output of EXOR gate 47 changes to "1°",
Instead of the priority code of the received No. 4 SR, its own priority code is transmitted, and from then on, the output of the PSC 37 is transmitted in the same way.

Note that the delay circuit 46 connects the output of the PSC 37 and the FFC 11.
This is to match the timing with the output of
In this case, the delay time should be set to ``::1 bit''.

(in Figure 5) is the clear signal stone, the output Q of FFC432
Control signal S sent out from. , and a timing chart showing changes in the preset signal PSE;
When the PU 21 determines that the received No. 4 SR has become the priority code 54 of the transmission right request signal and also determines that it should also request the transmission right, it responds by sending the clear signal CLR as " From 0'° to "1'°, FFC43
□, 43□ are released from the reset state, and the preset signal PSE is set to a no-signal state of "1". , which turns on the AND gate 44.

Note that the CPU 21 transmits its own transmission right request signal to another ST.
All transmission lines 2, to 2. After completing one cycle and failing to receive data, the FF determines that it can acquire the right to transmit and sets the preset signal PSE to "0".

It has become a matter of force.

On the other hand, FIG. 5(C) shows the STA which is transmitting received No. 4 SR.
In the timing chart similar to (B), the clear signal CLR is in a no-signal state of 1°, the preset signal standard is in a preset state of "0", and the control signal Sc is "1°"), the AND gate 44 is kept on, and the output of the PSC 37 is transmitted as the transmission signal Ss.

FIG. 6 is a timing chart showing the signal status in the tower section of FIG.

Since FFC11 responds to the start-up υ that changes to
The output (,) of EL32 becomes the output (b) of FFC11 with a delay of the clock pulse (1) by the Soi cycle, while the output of P
The output (c) of the SC37 receives an equivalent delay from the delay circuit 46 and becomes the delayed output (d), and both outputs (a),
The output of the EXOR gate 47 (
, ) changes to 1", it is initially reset and FFC43
Since the output Q of □ is “1”, the minute gate 4B
When the output (f) of
3□ is set, and the output Q(g) is turned to l'' and the output Q is turned to 0''.

Therefore, the gate 48 is immediately turned off and the output (
f) is returned to "0°", the FFC431 is reset by the rising edge of the next clock pulse (1), and the output (g) is set to "0", but the output (g) is connected to the clock terminal CK of the FFC43s. output value) is “0” to “1”.
When the transition to 1c occurs, the FFC 43 becomes υ set by 1° of the output (C) applied to the data terminal, and after time 1c, the tD (h) of the FFC 43 becomes 1
'° is maintained, and this is the control signal S. Closed gate 4
4 and inverter 45.

Therefore, in both FIGS. 5(G) and 5(B), it is determined that the received priority is also higher than the own priority, and the switch SW is controlled accordingly.

FIG. 1 is a timing chart showing the status of signal transmission and reception between STAs when this method is applied to the method disclosed in the above-mentioned Japanese Patent Application No. 59-260800. further requests possession of the transmission right, the transmitter S adds its own priority ■ to the request signal CTA indicating the request for the transmission right and transmits it, and this is received by the receiver R at 5TA-CEB. , due to the above-mentioned operation, the judgment of its own high priority (2) is delayed, and when this is added, it is transmitted as a request signal CTB with a delay of one bit.

This transmission is received by 5TA-CEc, but this
Also, based on the judgment of its own high priority V, this is added and transmitted as a request signal CTc with a delay of 1 bit, 5TA-σ. In this case, this is transmitted without relaying due to a delay of almost 1 bit, and 5TA
- Received at the CIA.

Then, 5TA-CEA transmits its own transmitted request signal c
'rA011) is not received, it is determined that the transmission right that has been occupied so far should be abandoned, and the received request signal CT
, (V) is stored once and then CT is used as a transfer designation signal.
It transmits cTc'(V), which is different from c(v), and when this is relayed sequentially and received by 5TA-CEC, 5TA-+Jc further transmits this and acquires the transmission right. After determining that the activation signal OK is sent as a confirmation signal, this is relayed one after another, and if it can be received by itself, other 5TA-CEA,
CE, , and CED also determine that 5TA-CEc has confirmed that it has acquired the transmission right, and enter the transmission state.

Furthermore, upon receiving the validation signal OK after re-receiving the request signal CTc' (V), 5TA-CIA relinquishes the transmission right and does not re-relay the request signal CTc' (V). , 5TA-CEB, and CED, in response to receiving the activation signal OK, confirm that 5TA-CE has acquired the transmission right, as described below.

Therefore, the relay transmission of the received signals is reduced with only a delay of y1 bit, and the time required for relaying is significantly shortened. Although the time required for transmission is the same, the overall transmission speed is improved, and various data transmission and control responsiveness are realized at higher speeds.

Furthermore, by completing one cycle of the request signal, the handover designation signal, and the confirmation signal, the transmission right can be reliably taken over, and the time required for the handover can be shortened.

However, so-called free tokens, visit tokens, etc. may be used as the request signal and the handover designation signal, and the activation signal OK is originally a global signal (hereinafter referred to as GLS) that should be received by all STAs. However, it is the same even if a separate signal is used as the confirmation signal instead of using this as the confirmation signal.

FIG. 7 is a general flowchart of the control situation by the CPU 21, which executes instructions in the ROM 23 while accessing necessary data to the RAM 22.

That is, 'Initialize' 101 K, 5 each
A determination is made as to whether TA-CEA-CEr is a primary side that has the transmission right or a secondary side that does not have the transmission right, and in accordance with this result, the “Primary side?” 102 determination is made. , the necessary parts are cleared.

Note that step 101 is performed when the power is turned on or when the power supply recovers from a power outage.
Each 5TA-(JA-CBD) has a waiting time determined for each address number according to its address number, and if no signal is received during this time, it is determined that it has the right to transmit, and it is unable to receive signals from others. If so, it is determined that there is no transmission right.

If step 102 is Y (YES), the preset signal is set to "Ooo", the switch SW is controlled, and the "transmission mode setting" 111 is performed. is selected, and a request signal with a code indicating this priority is sent as “self-CT transmission” 121
It is monitored by the same signal "CT reception?" 122 to see if it is received through all the transmission paths, and if this is N (No), and the timer in the CPU 21 waits for a certain period of time "TRI". Progress?" While 123 is N, repeat steps 122 and after, and if step 123 becomes Y due to time-up of the timer, the counter in the CPU 24 will repeat " until the set maximum number of repeated transmissions MK is reached.
Number of transmissions - M? ” via 124ON, step 12
1 and subsequent steps are repeated, and as step 124 becomes Y,
``Abnormal processing''.

The process moves to step 125, where an alarm is sent out and displayed.

While steps 123 and 124 are N, step 122 is Y.
If so, check whether this was sent by the user or not.
T? ” Judging from 131, if this is N,
This is the reception of a request signal CT from a source other than the self, and the buffer memory IJ using a part of RAM η is sent to BFM “BFM+”.
-CT" 132 stores and temporarily accumulates the received request signal, and the "Receive CT transfer" 133 transmits this content as the takeover designation signal Cτ, and the clear signal CLR is set to "0.
’° and perform “receive mode setting” 134,
If the validation signal "OK received?" 135 as a confirmation signal is Y, the transmission right is abandoned and the process moves to "receive mode setting" 183, which will be described later.While step 135 is N, step 123 Same as ゜124, for a certain period of time “TRI
Progress? "°136" is monitored, and when it becomes Y, "transmission mode setting" 137 is performed in the same manner as in step 111, and "number of transmissions = M?" ” Step 133 and subsequent steps are repeated via step 138, and as step 136 becomes Y,
Return to step 121.

Moreover, if step 131 becomes Y, it means that the user has acquired the transmission right, so the activation signal “O” is sent as a confirmation signal.
K transmission" 141 is performed, and as in steps 122 to 124, the same signal 'OK reception?" While 142 is N,
Step 141 and subsequent steps are repeated via Y in 143 for a certain period of time "TR1 elapsed?" and N in 144 for "Number of transmissions=M?", and when step 144 becomes Y, the process moves to step 125.

If step 142 becomes Y while step 144 is N, when new transmission data is generated, it is checked whether the priority of this data is υ higher than the priority transmitted in step 121. Therefore, “occurrence priority>sent priority?”
In order to make the determination in step 151 and to continuously transmit data with the same priority, the priority transmitted in step 121 is compared with the highest priority among the other data to be transmitted. Other highest priority=transmitted priority?" 152, and when step 152 is N, steps 121 and subsequent steps are repeated to give other STAs a chance to acquire the transmission right, while step 151 is YES. In response to this, steps 121 and subsequent steps are repeated to notify other STAs that there is data to be transmitted with a higher priority than the previous time.

When step 151 is N and step 152 is Y, "data transmission processing" 153 is performed, and step 15
1 and subsequent steps are repeated, and until step 131 becomes N, it transmits its own transmission data in order from the one with the highest priority, but when a request signal CT with a higher priority is transmitted from another STA, step 131 is N, and step 1
If 34 is Y, “receive mode setting” 18 described later
Move to 3.

Regarding the above, when step 102 is N, the switch SW is controlled by setting the clear signal CLR to 'O°°, and after performing the "reception mode setting" 161, the self checks "Is there data to be sent?" 162. and if this is Y, then the fifth
Give your own priority code 54 and subsequent ones shown in the figure to the PSC 37 and "Set data to psc".

163, and in response to the request signal "CT reception?" 171 from another STA becoming Y, as shown in FIG. Depending on the output Q and the output of the OR gate 42, it monitors whether or not its own priority code 54 or later has been transmitted, and after determining "Self priority or reception priority?" 181, if this is N, then Since its own transmission priority is higher than other transmission priorities, it is determined that it has the right to transmit, but in response to Y in step 181, it is determined that the transmission right is not granted to itself, and in step 161. After similarly performing "receiving mode setting" 183, "receiving data processing" 184 and "monitoring processing" 185, step 162
Repeat the following.

Note that if step 181 is Y, the received request signal CT is
Through the R gate 42, the signal is relayed and transmitted as is, with only a delay of 1 bit.

On the other hand, if step 181 is N, clear signal “CL
By R="O" 191, riF'FC43, 43 paste 7l! and then monitor “Receive on C?” 192.
If the request signal received in response to this Y determines "self Cτ?" 193 corresponding to the own request signal transmitted between steps 172 to 181, and if this is Y, the transmission right can be overwritten. Adashi, “Transmission mode setting” 196
in the same way as step 111, and then step 14
1, whereas when step 193 is N, it is impossible to acquire the transmission right, so as in step 132, “
After performing BFM4-σ” 194, step 18
Move to 3.

Further, while step 192 is N, the predetermined time “TRfi” determined as TR□kTo is similar to step 123.
Progress? ” 195 is monitored, and while this is N, steps 192 and subsequent steps are repeated, and the process moves to step 125 according to this Y.

FIG. 8 is a flowchart showing the details of step 153. sb, "Is the transmission data GLS?" 201 is determined, and if this is N, only "data transmission" 202 is performed, but when step 201 is Y, " GLS transmission” 211
In addition, whether or not this is received via all transmission paths is monitored by "Transmission GLS reception?" 212. While this is N, "TR progress?" is displayed for a certain period of time as in steps 123 and 124. 213 Y and “Number of transmissions = M?
Steps 211 and subsequent steps are repeated via N in ``214'', and when step 214 becomes Y, ``abnormality processing n215'' is performed as in step 125.

If step 212 becomes Y while step 214 is N, the enabling signal "OK" is sent as in steps 141 to 144.
Send” 221 and the same signal “OK received?゛.

Fixed time “TR□ elapsed?” 22 via N of 222
3, “Number of transmissions = M?” corresponding to Y of this 224
Step 221 and subsequent steps are repeated via N, and when step 224 becomes Y, the process moves to step 215. If the OK flaw signal can be received while step 224 is N, step 222 becomes Y.

FIG. 9 is a flowchart showing the details of step 184, in which "Received data is GLS?" 301 is determined according to Y of "Received data?" 300, and this is N.
If so, perform “BFM←Clear” 302 for GLS, then check “Addressed to self?” 303 based on the address code of the destination added to the received data, and check Y for this.
"Content decoding" 304 is performed according to the content.

Also, when step 301 is Y, the content is the validation signal ``OK?'' 311 is determined, and if the result is N, GLS is stored in the shipper memory BFM by ``BFM 4-GLS'' 312. However, by repeating step 162 and subsequent steps in FIG.
Content 1? ” 321, and according to Y of this, “Read BFM contents 322” is performed, and the process moves to step 304.

FIG. 10 is a flowchart showing details of step 185), in which the main table and sub-table shown below are provided as specific areas in the RAM 22, and these are used.

In other words, the main table (hereinafter referred to as MT) and the sub-table (hereinafter referred to as ST) correspond to each of the 5TA-CEA-CED, and the operating status of each STA is monitored during a certain monitoring period. If it is determined to be normal, a code indicated by a Q mark is stored, and similarly, if it is determined to be abnormal, a code indicated by an X mark is stored in correspondence with each other, and registration is performed accordingly.

/゛' 7, / Table 1 Table 2 Table 3 Note that for the MTs in Table 1, the judgment results during the previous monitoring period can be registered as they are, and the MTs in Table 3 will be used for the next It is used as the MT in Table 1 during the monitoring period.

In FIG. 10, "Power ON?" 401 is determined, and if this is Y'''C6, all X are registered to MT" 402
After performing the "timer star" 411 provided in the CPU 21 to specify a certain monitoring period,
Perform all X registration ``412'' to T, and depending on the result of step 304, which STA ``CEi acquires the transmission right?゛″
421, and if this is Y, "MT's CEi
=X? ” 422, and if it is Y, perform “Register MT-8T to CEI” 431. For example, if CDI = CEA, set the status as shown in Table 2.
5TA-CEi due to “CEl recovery notification” °432
It performs processing such as displaying that the device has recovered from an abnormality to normal, and storing in the RAM 22 a message that it can be selected as a communication partner.

In addition, if step 422 is NT:
Go to ×Register''433, for example, CEI = CEB
Now let's take the example shown in Table 2) and write "Timer time up?"
” While 441 is N, steps 421 and subsequent steps are repeated,
After performing a "judgment process" 442 in response to Y in step 441, the above operations are repeated through step 162 and subsequent steps in FIG.

Therefore, for example, if 5TA-CEA and CEc acquire the transmission right in sequence and 5TA-CEB and CED do not acquire the transmission right, the state shown in Table 2 will be υ. MT that showed the previous result
The contents are finally updated and become the ones in Table 3.

In other words, in step 442, the contents of the following table are executed.

Table 4 Note that "abnormality occurrence notification" includes the same display as in step 432 and the RAM2 notification that the communication partner cannot be selected.
2, etc. can be executed.・Therefore, if all of the 5TA-CEA-CEDs or at least a plurality of 5TA-CEA-CEDs perform the above operations, an abnormality will be determined based on the comparison at the time of "x registration" in Table 4, and the corresponding actions will be taken. At the same time as the notification is made, the recovery to normality is also notified in step 432, and these are notified in each STA, so even if any STA loses the monitoring function, the overall monitoring function will not be lost. First, the reliability of the entire system is improved.

Alternatively, step 431 may be for ST only, MT registration may be included in step 442, and step 43
Similar results can be obtained by similarly including 2 in step 442.

As a result of the above, the time required for relaying each signal and switching and transmitting priority request signals between STAs connected in a loop is greatly reduced, the overall transmission speed is improved, and the minimum necessary Signal transmission and reception ensure that the transfer tank is taken over and the acquisition status is confirmed, and the operating status of each STA is also accurately monitored, achieving high responsiveness and reliability in data transmission and control. do.

As a delay element, it is preferable to use FFC11 since it also exhibits a waveform shaping effect, but other elements or circuits may be used, and the delay time can be changed from 1 bit to within a range that does not cause any practical problems. The same is true for large or small, and the configuration in Figure 4 can be arbitrarily selected according to the conditions, and in Figure 5 (4), the order of each bit is inverted except for the priority code 54. The grade of this may be determined not only in (1) to (g) but also according to the conditions, and the destination address code of the data signal is When all are designated at the same time, various modifications are possible, such as allowing each designated STA to maintain the receiving mode.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, the time required for relaying and switching and transmitting priority request signals between STAs connected in a loop is greatly reduced, and the overall transmission speed is improved. At the same time, it is possible to perform the minimum necessary signal transmission and reception, to confirm the transmission right handover and acquisition status, to achieve high speed data transmission and high responsiveness of control status, and to achieve overall high reliability. This realizes remarkable effects in various data transmission and control.

[Brief explanation of the drawing]

The figures show an embodiment of the present invention, Fig. 1 is a timing chart showing the transmission and reception status of signals between each STA, Fig. 2 is a block diagram showing the overall configuration, and Fig. 3 is a block diagram showing the configuration of the STA. , FIG. 4 is a block diagram showing the specific configuration of STA, FIG. 6 is a timing chart showing the state of the signals in each part of FIG. 4, FIG. 7 is a general flowchart,
8 to 10 are flowcharts showing the lower routine of FIG. 7. 2, ~24.2R, 23...Transmission line, 11°430
．． 432...FFC (flip-flop circuit), 2
1...CPU (processor), 22...RA
M (variable memory), 23... ROM (fixed memory), 31... spa (serial parallel converter), 37...
...psc (parallel-serial converter), 40...SSC
(sending circuit), Φ gate at 41, 44, 48...
42 ・ ・ ・ ・OR gate, 45 ・ ・ ・ ・
Inverter, 46...Delay circuit, 47...EX
OR (exclusive OR) gate, 53... Transmission right request code, 54... -Priority code, CEA-CED
...STA (communication equipment), SR...reception number 4, Ss...transmission number, SO...transmission output,
RI...Reception input, SW...Switcher, CT
...Transmission right request signal, OK...confirmation signal. Patent Applicant Yamatake Honeywell Co., Ltd. Agent Masaki Yamakawa (-712 persons) Figure 1 Figure 2 Figure 3 R Figure 6 tc (1) "Kuchukuchi Lororo Loro L Figure 9

Claims (1)

[Claims] Consisting of a plurality of communication devices connected in a loop, a signal received from one transmission path is relayed and transmitted to the other transmission path, and the communication device requesting the transmission right sends the transmission right request signal. In this method, the received signal is transmitted with a time delay of at least 1 bit, and when the transmitter requests the transmission right, the received signal is transmitted with a code indicating the priority of the transmission right. Each communication device is provided with a circuit that compares the priority code with its own priority code and transmits its own priority code in place of the received priority code when the priority code of the self is high. When the received transmission right request signal is different from its own, the communication device transmits a takeover designation signal indicating the communication device that will acquire the transmission right next in response to the transmission right request signal, and The transmission right is relinquished after the transmission of the transmission right, and each of the other communication devices relays and transmits the said takeover designation signal, and the next communication device to acquire the transmission right relinquishes the transmission right in accordance with the reception of the said takeover designation signal. A transmission right handover method characterized in that a confirmation signal is transmitted after acquiring the transmission right, and the confirmation signal is relayed and transmitted to other communication devices, and the communication device that has acquired the transmission right is confirmed.