JPS62290231A - Transmission right handover method - Google Patents

Abstract

PURPOSE:To contrive efficient data transmission in terms of each communication equipment by shorting time required for relaying and switching a preferential right request signal and taking over the transmission right through minimum signal exchange. CONSTITUTION:In terms of communication equipments STA(CEA-CED) connected in a loop, each STA hourly transmits a transmission signal SS by delaying a reception signal SR by at least about one bit. If it requests the transmission right, it compares a received prioirty code and its own code. If its own code is of higher priority, it transmits its own code instead of the received code. If it has the transmission right and a received transmission right request signal CT different from its own code, it responds the signal CT, transmits a taking over designation signal CT' showing an STC that will take over the transmission right next time. Other STCs relay and transmit the taking over desgination signal CT'. The STA to take over the transmission right next time acquires the transmission right after it receives the taking over designation signal CT'.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a system for taking over transmission rights between a plurality of communication devices connected in a loop.

[Conventional technology]

LAN (Local Area Network)
), various on-premises control equipment, etc., as proposed in Japanese Patent Application No. 59-260800 filed separately by the applicant, a transmission line is used to connect multiple communication devices that transmit and receive data. After connecting as a serial loop, the transmission direction of the data signal is determined, and while one of the communication devices acquires the transmission right and is transmitting, the other communication device relays the signal received from one transmission path. When transmitting to the other transmission path and acquiring a new transmission right upon completion of transmission, the communication device requesting the transmission right generally uses a token (Token).
A code indicating the priority of the transmission right is added to a transmission right request signal called ``en)'' and transmitted, and the communication device having a high priority acquires the transmission right.

[Problem that the invention seeks to solve]

However, in the past, in order to ensure transmission right handover, a takeover signal, etc. was sent and received in addition to the transmission right request signal, which required extra transmission time and required each communication device to receive four reception signals. When receiving a transmission right request signal, it determines whether it should acquire the transmission right or whether it should relay and transmit without acquiring it. If the process should be repeated or relayed after all signals have been received, the time required to make a decision will be added to each communication device, causing a problem in which the delay time caused by the decision in transmitting the wA request signal will not increase. ing.

[Means for solving problems]

In order to solve the above-mentioned problem, the present invention is constructed by the following means.

That is, in the above-mentioned method, the received signal is transmitted with a time delay of at least one bit, and when it requests the transmission right, it compares the received priority code with its own priority code. Each communication device is equipped with a circuit that transmits its own priority code in place of the received priority code when its own priority exceeds the limit, and if the communication device already has the transmission right, the received transmission right request signal is In response to this transmission/1j right request signal, a takeover designation signal indicating the next communication device to acquire the transmission right is transmitted, and each of the other communication devices relays and transmits the takeover designation signal, and then A communication device that acquires the transmission right at the time of transmission is assumed to acquire the transmission right in accordance with the reception of the takeover designation signal.

[Effect]

Therefore, by using the hardware circuit provided for each communication device, the received signal No. 4 is transmitted by multiple relays, receiving only the delay of the first pit, and the delay time due to relaying is reduced. When the self requests the transmission right, if the received priority is higher than the received priority, the priority code of the self or later is transmitted, and the transmission of the transmission right request signal is also speeded up. If the received transmission right request signal is different from the own, the transmission right is acquired by the takeover designation signal transmitted in response to this, and the transmission right can be taken over quickly and reliably.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to figures showing examples.

FIG. 2 is a block diagram showing the entire configuration.
In this row, signals are transmitted in the direction shown by the arrow. For example, 5TA-CEA acquires the transmission right, and 5TA-CEA
When transmitting to CED, 5TA-CEB, C
Each EC relays and transmits received signals. Figure 3 is a block diagram showing the details of each 5TA-CE. One transmission line 2R is connected to the receiving input RI of this I/F) 1b, and a D-type 7 lip-flop circuit ( Hereinafter, the FFC) 11 intervenes, and in response to the clock pulse CLK synchronized with the reception No. 4 SR given from the I/F 1b to the clock terminal CK of this FFC, the reception No. 4 SR given to the data terminal is sequentially held. As a result, a delay of y1 bits is given to the reception signal 4, and the signal is transmitted to the transmission path 2S as the transmission signal Ss.

Further, the output Q of the FFC 11 is connected to the transmission line 2S via the switch SW, and l:t, x/7tb is the control signal S.
When c occurs, the switch SW responds and switches from the output Q of the FFC 11 to the transmission output SO of the I/F 1b and connects it to the transmission line 2S, so the signal from the I/F 1b is transmitted to the transmission line 2S. become something that

FIG. 4 shows main devices i 1 a , I/'F1 b ,
This is a block diagram showing the specific configuration of the FFC 11 and the switch SW, a processor such as a microprocessor (hereinafter referred to as CPU) 21, a variable memory (hereinafter referred to as RAM) 22,
Fixed memory (hereinafter referred to as ROM) 23, bus controller (
BCT) 24, serial/parallel converter such as a shift register (hereinafter referred to as 5pa) 31, "O' bit deletion circuit (hereinafter referred to as 2EL) 32, CRC (Cyclic Radund
an+cy Check,) detection circuit (hereinafter referred to as CHD)
33. Abort/idle detection circuit (
34 (hereinafter referred to as AAD), CRC signal generation circuit (hereinafter referred to as CR
G) 35, Abort signal generation circuit (hereinafter referred to as ASG) 36
, parallel-to-serial converters such as shift registers (hereinafter referred to as PSC)
37, 'O' bit insertion circuit (hereinafter referred to as ZIS) 38 etc. is provided, and the reception signals SR to ZE of the transmission line 2R and beyond are provided.
In L32, the "0" bit is deleted according to the HDLC procedure such as JISC6363, and the data is converted into parallel data in 5PC31 and sent to CPU21 via bus 39.CPU21 receives RO via BCT24.
It executes the command in M23, makes judgments on received data and control decisions while accessing predetermined data in the RAM 22, and executes the instructions in CRG35.M23 as necessary. It controls the ASG 36 and provides parallel data transmission data to the PSC 37.

Then, in the transmission data PSC 37, the serial data and the CRC signal from the CRG 35 are inserted, and the transmission data is transmitted to the ZI 838 via the transmission circuit (hereinafter referred to as 5SC) 40.
In the zI838, a ``0'' bit is inserted according to the HDLC procedure described above, and if necessary, an abort signal from the ASG36 is inserted to interrupt the transmission. It is transmitted as a transmission number Ss.

In addition, the received signal SR is also given to AAD34,
While the CPU 21 performs predetermined control according to the detection power of this and the output indicating the check result of the CRD 33, depending on conditions, the DMA (DirectM@mory
Under Accesa, ) control, the received data from 5PC31 is directly stored in RAM22 via BCT24,
Alternatively, the contents of the RAM 22 are sent directly to the PSC 37. Also, the ZEL 3217) output is given to the data terminal of the FFC 11 included in the 5SC 40, and its output Q is the AND game) 41.01 ? ZI83B through gate 42
When in reception mode, the clear terminal CL of this is applied to the control FFC431, 432.
The CPU 21 gives a clear signal CLR to F F C4.
3lN '3'' is in the reset state, so its output Q is the logical value @O'', AND gate 44
is turned off, while the output of the inverter 45 becomes a logical value of 1.
Since # is j5 and the AND gate 41 is in the ON state, the signal from the output Q of 1cFFc11 is given to ZIS 38 as in FIG. 3, and this is transmitted as the transmission signal Ss. .

In contrast to the above, when the user obtains the transmission right, FFC4
Since the CPU 21 gives the preset signal PSE to the preset terminal PR of 32, the FFC 432 is set to output Qt-"1", and the AND gate 44 is turned on, while the output of the inverter 45 is set to "0" and the
Transmission in which the gate 41 is turned off, the signal from the delay circuit 46 is applied instead of the output Q of the FFC 11 to the input of the ZI 338 via the AND gate 44 and the OR gate 42, and this is sent to the transmission line 2S as the transmission signal Ss. mode.

On the other hand, when the CPU 21 determines that a transmission right request should be made to the PSC 37, 1" indicates the priority of the transmission right.
In order to set a transmission right request signal containing a code based on the combination of fiQjl+, this content is the clock pulse CL.
The data are sequentially sent out as serial data in accordance with K and applied to an exclusive OR (hereinafter referred to as EXOR) gate 47.

That is, if the CPU 21 determines to start receiving the transmission right request signal, the CPU 21 sends the transmission data including the code indicating the priority of the transmission right request to the PSC 3 before receiving the code indicating the priority.
7 is to be set to 0. Therefore, when the output of ZEL 32 contains a similar code indicating the received priority, this will be applied to the other input of EXOR gate 47.
ZEL32 output is 0'', PSC37 output is '1''
If the condition is met, the output of EXOR gate 47 becomes 1#, which is applied to the data terminal of FFC431 via AND gate 48, FFC431 is set in response to clock pulse CLK, and FFC432 is set in response to this.
is also set to produce the output Qt-''1'', so the AND gate 44 turns on, and the output of the PSC 37 delayed by the delay circuit 46 is sent out as the fourth transmission signal Ss.

The details of these operating conditions will be described later, and the output Q of the FFC 432 and the OR gate 42
The output of is given to the CPU 21 via the bus 39,
The CPU 21 determines whether or not its own transmission data set in the PSC 37 has been transmitted.

Figure 5 shows an example of the content of a transmission right request signal that indicates the above situation.In this case, the signal includes an 8-bit start flag 51 and a global flag 52 that indicates that it should be received by all STAs. , a transmission right request code 53, a priority code 54, a transmission source code 55 indicating the address of the transmission STA,
The signal is generated by the CRC signal 56 and the end flag 57, and in the illustrated state, the reception No. 4 Sa is the priority code 5.
4 indicates "2" in binary, sender code 5
The source ST indicated by roooooooolJ of 5
The priority added to A is ■.

On the other hand, the transmission right request signal that the own STA should transmit as the transmission No. 4 SS has the same start 72 tag 51, global code 52, transmission right request code 53, and end flag 57 as the reception No. 4 SR. Only the priority code 54, sender code 55 and CRC signal 56 are different. In this example, the priority is "4" in binary, so the priority of reception number 4 is different. The priority level (2) of the self is high, and the self can request the transmission right preferentially.

Therefore, according to FFC11 in FIG. 4, reception number 4 SR
is delayed by y1 pit and is transmitted as transmission number 4 Ss, and the signal from reception number 4 SR and PSC37 is E.
Since the start flag 51 to the fifth bit of the priority code 54 are compared by the XOR gate 4γ, the output of the EXOR gate 47 remains 0#, whereas
When reaching the 6th pit of priority code 54, the reception No. 4 SR
is "O", and the output of 5FLG47 is "1", the judgment condition that its own priority is high is established, and as mentioned above, 9EX
The output of the OR gate 47 changes to "1" and the reception No. 4 Svt
Instead of the priority code of , its own priority code is transmitted, and from then on, the output of the PSC 37 is transmitted in the same way.

Note that the delay circuit 46 connects the output of the PSC 37 and the FFC 11.
This is to match the timing with the output of
In this case, the delay time may be set to ``i1 bit''.

FIG. 5(B) is a timing chart showing changes in the control signal Sc sent from the output Q of the clear signal CLRX FFC 432 and the preset signal PSE. When it is determined that the priority code of
31 and 432, and set the preset signal PSE to a no-signal state of '1#.
When C is 11'', the AND gate 44 is turned on.

Note that the CPU 21 transmits its own transmission right request signal to another ST.
When it has gone around all the transmission lines 21 to 24 via A and is received by itself, it judges that it can acquire the transmission right, sets the preset signal PSE to "0" and forcibly sets the FFC 432. 〇 On the other hand, Fig. 5 (C) shows the STA transmitting the received No.
The timing chart is similar to Φ) in Φ), clear signal CLR is 1#, no signal state, preset signal PS
E is in the preset state of 0#, and in response, the control signal Sc becomes 11'', the AND gate 44 is kept on, and the output of the PSC 37 is transmitted as the transmission No. 4 Ss.

FIG. 6 is a timing chart showing the signal status in each part of FIG. 4. In order for F'F'C11 to respond, Z
The output (a) of EL32 is the clock pulse (1) because μ
While the output (b) of the FFC 11 is delayed by a period of one cycle,
The output (e) of the psc37 receives an equivalent delay from the delay circuit 46 and becomes the delayed output (d), so that both image outputs (JL)
, (e) When the output (e) of EXOR gate 4T changes to '1#, it is initially reset and the FF
Since the output Q of C431 is 11#, the output (f) of the AND gate 48 becomes 1'', and following this, the FFC431 is set at time t according to the rising edge of the clock pulse (i), and the output Q (?)@1″
At the same time, the output signal is changed to "0".

Therefore, the AND gate 48 is immediately turned off and the output (f) is returned to '0', and at the rising edge of the next clock pulse (+), the FFC 431 is reset and the output (f) is returned to '0'. '', the output (is given to the clock terminal CK of FFC432, and the output (is 0'' to '1'')
When switching to te, the FFC 431 is set to 1'' of the output (c) applied to the data terminal, and at the time te.
Thereafter, the output (h) of the FFC 432 maintains '1', and this is sent to the AND gate 44 and the inverter 45 as the control signal Sc.

Therefore, in both FIGS. 5A and 5B, it is determined that the received priority is higher than the received priority, and the switch SW is controlled accordingly.

FIG. 1 is a timing chart showing the signal transmission and reception status between each STA when this method is applied to the method according to the above-mentioned Japanese Patent Application No. 59-260800. further requests possession of the transmission right, the transmitter S adds its own priority ■ to the request signal CTA indicating the request for the transmission right and transmits it, and this is received by the receiver R at STA/CEB. , The above-mentioned operation determines the high priority level (2) of itself, and this is added and transmitted as the request compensation code CTB due to the delay of the SO1 pit.

This transmission is received by 5TA-CEc, but
In 5TA-CHD, this is added as a request signal CTc with a delay of 1 bit due to the judgment of its own high priority V, and in 5TA-CHD, this is not repeated multiple times due to the delay of 1 bit. has been sent and
5TA-CEA.

Then, 5TA-CEA transmits the request signal C transmitted by itself.
Since TA(1) is not received, it is determined that the transmission right that has been occupied so far should be abandoned, and the received request signal CTc
(V) is accumulated once, and then CTC (
5TA-CEc transmits CTc'(a) which is different from V), and when this is relayed sequentially and received by 5TA-CEc, 5TA-CEc further transmits it and acquires the transmission right. It is determined that the activation signal has been activated, and the activation signal OK is sent as a confirmation signal, and this is relayed sequentially and goes around.
If it can be received by itself, other 5TA-CEA, CE
B and CEo also judge that 5TA-CEc has confirmed that it has acquired the transmission right, and enter the transmitting state. In response to receiving the validation signal QK after reception, the transmission right is relinquished and the request signal CTC' (g) is not re-relayed. Confirmation that 5TA-CEc has acquired the transmission right will be performed as described below. Therefore, the received and received signals are relayed with only a 1-bit delay, and the time required for relaying is greatly shortened. At the same time, the time required for relaying the transmission right request signal and switching to the own transmission right request signal is also reduced, which improves the overall transmission speed and speeds up the transmission of various data and control responsiveness. Realize.

In addition, the transmission right is reliably handed over through one cycle of the request signal, the handover designation signal, and the confirmation signal, and the time required for the handover is shortened.

However, the request signal and takeover designation signal may be used in so-called free tokens and visit tokens, and the activation signal OK is originally used to validate the global signal (hereinafter referred to as GLS) that should be received by all STAs. However, it is the same even if this is not used as a confirmation signal and a separate signal is used as a confirmation signal.

Note that the transmission and reception of the confirmation signal may be omitted; in this case, 5TA-CEA relinquishes the transmission right according to the transmission and reception of the takeover signal, and each 5TA-CEn and CEn acquires the transmission right at CTA-CEc. It is only necessary to confirm that it has been carried out.

FIG. 7 is a general flowchart of the control situation by the CPU 21. In addition, according to the instructions in the ROM 23, the necessary data is executed while accessing the RAM 22.

In other words, 'initialize #101, each ST
A judgment is made as to whether A-CEA-CED is a primary side having the transmission right or a secondary side not having the transmission right, and depending on the result, a determination is made as to "Primary side?" 102. , the necessary parts are cleared.

Note that step 101 is performed in response to power-on or recovery from a power outage, etc., and the determination of "primary side?" is, for example, a waiting time set for each 5TA-CEA according to the address number of the CED. If a signal is not received during this period, it is determined that it has the right to transmit, and if a signal from another is received, it is determined that it does not have the right to transmit.

If step 102 is Y (YES), the preset signal psEf: "o" is used to control the switch SW and "transmission mode setting" 111 is performed. and send a request signal with a code indicating this priority to one self-CT.”
121, and monitors whether or not this is received via all transmission paths using the open signal "CT reception?"122;
If this is N (No), and while the partial time "' TR1 elapsed t-123 by the timer in the CPU 21 is N, step 122 and subsequent steps are repeated, and step 123 becomes Y due to the timer time-up. Until the counter in the CPU 21 reaches the set maximum number of repeated transmissions M?, “Number of transmissions=M?” ”124ON, step 121
The following steps are repeated, and when step 124 becomes Y, step 6
The process moves to ``abnormality processing'' 125, where an alarm is sent out and displayed.

While steps 123 and 124 are N, step 122 is Y.
If so, check whether this was sent by the user or not.
T? ” 131, and if this is N, the request signal CT is not received from a source other than the self, and the buffer memory BFM using a part of the RAM 22 is sent “B F Ml-
CT" 132 stores the received request signal and accumulates it once, transmits this content as a takeover designation signal CT' to "Receive CT Transfer" 133, and sends a clear signal CLR"
0", perform the "Reception mode setting" 134, and then perform the validation signal as a confirmation signal @OK received?" 135 is Y, abandon the transmission right and perform the 1 reception mode setting #1 described later.
83, while step 135 is N,
Similar to step 12 124, monitor the partial time "'Tn! elapsed?" 136, and when this becomes Y, perform "transmission mode setting" 13γ as in step 111.
Number of transmissions = M? ” Step 133 and subsequent steps are repeated via step 138, and as step 136 becomes Y, the process returns to step 121.

Moreover, if step 131 becomes Y, it means that the self has acquired the transmission right, so the activation signal "O" is sent as a confirmation signal.
K transmission" 141 is performed, and the same signal "'OK received?' as in steps 122 to 124. ``While 142 is N, a certain period of time @TRI elapsed 7'' 143 Y and ``Number of transmissions = M
? ” Step 141 and subsequent steps are repeated through N in 144, and as step 144 becomes Y, step 1
Move to 25.

If step 142 becomes Y while step 144 is N, when new transmission data is generated, it is checked whether the priority of this data is higher than the priority transmitted in step 121. Therefore, 1 Occurrence priority > Sent priority? ”
Based on the determination in step 151 and the contrast between the highest priority among the other data to be transmitted and the priority transmitted in step 121, for the purpose of continuously transmitting data with the same priority, 6 other highest Priority = Sent priority? If step 152 is N, step 121 and subsequent steps are repeated to give other STAs an opportunity to acquire the transmission right.
The following steps are repeated, and other STAs are notified that there is transmission data with a higher priority than last time.

When step 151 is N1 and step 152 is Y, 'data transmission processing #153 is performed, and step 15
1 and subsequent steps are repeated, and until step 131 becomes N, it transmits its own transmission data in order from the one with the highest priority, but other STA may also transmit a request signal CT with a high priority, and step 131 131 is N and step 1
If 34 becomes Y, the process moves to reception mode setting 183, which will be described later.

Regarding the above, when step 102 is N, the switch SW is controlled by the clear signal CLRt-'0#, and the check is made to "1 transmit data up?" 162 after performing reception mode setting #161. If this is Y, the own priority code 54 and later shown in FIG.
Give it to 37 @ psc Heteta date "163,
Request signal “CT reception M?” from other STA 171
Toner OK response L;, as shown in Fig. 5 CB), perform clear signal @CLR = "1" ” 172, F
It monitors whether or not its own priority code 54 or later has been transmitted according to the output Q of the FC 432 and the output of the OR gate 42, and determines "self priority <receiving priority?" 181, and if this is N, determines that its own transmission priority is higher than other transmission priorities and that it has the right to transmit, but in response to Y in step 181, it determines that it is not given the transmission right, and in step Same as 161, perform 6 reception mode setting 183, and set 184 and 6 ``Receive data processing''.
After performing the monitoring process 185, steps 162 and subsequent steps are repeated.

Note that if step 181 is Y, the received request signal CT is
The signal is relayed and transmitted as is through the R gate 42, with only one bit of delay.

On the other hand, if step 181 is N, clear signal "C
After resetting the JFFCs 43x and 43g using LR="Q" 191, monitor "'CT'received?" 192, and the request signal received in response to Y is sent to step 172.
193 corresponding to the self-request signal transmitted between 181 and 181. If this is Y, it means that the transmission right has been acquired, and the ``transmission mode setting'' 196 is performed in step 111. , and then proceed to step 141, whereas step 19
When 3 is N, it is impossible to acquire the transmission right, so after performing 'BFM+CT'' 194 in the same manner as step 132, the process moves to step 183.

Further, while step 192 is N, the predetermined time "'T defined as T+at<<Tnz, similar to step 123, is
R2 progress? 195 is monitored, and while this is N, steps 192 and subsequent steps are repeated, and the process moves to step 125 according to this Y.

FIG. 8 is a flowchart showing the details of step 153. 'Is the transmitted data GLS?' ” Judging 201,
If this is N, only 1 data transmission ``202'' is performed, but when step 201 is Y, ``GLS transmission'' 211 is performed.
After doing this, check whether this is received via all transmission paths or not by 1 transmission GLS reception? ``212 is monitored, and while this is N, a certain period of time is displayed as in steps 123 and 124'' TR1 elapsed? ” 213 Y and “Number of transmissions =
x? ”214ON and repeating the sump 211 and later,
When step 214 becomes Y, "abnormality processing" 215 is performed in the same manner as step 125.

If step 212 becomes Y while step 214 is N, the activation signal @OK is sent as in steps 141 to 144.
Transmission” 221, and open signal 'OK received? ``Determination of 223, corresponding to Y of this ``Number of transmissions = M? ” 224 through N of step 221 and step 224
If the OK M signal can be received while step 224 is N, then step 222 becomes Y.

FIG. 9 is a flowchart showing the details of step 184. ``In response to the Y of 300, determine ``Is the received data GLS?'' 301, and if this is N, check the ``BFM for GLS'' ← After clearing #302, the address code of the destination added to the received data. Based on “Self-addressed? ” 303 and performs ``content decoding # 304 according to Y”.

Moreover, when step 301 is Y, the content is the validation signal @OK? “Judge 311 and if the result is N”
"BFM4-GLS" 312 sender memory BF
GLS is stored in M, and as the step 311 becomes Y through steps 300 and 301 by repeating steps 162 onward in FIG. According to Y”BF
"Reading the contents of M" 322 is performed, and step 304
Move to.

FIG. 10 is a flowchart showing details of step 185! +, The main table and sub-table shown in the table below are provided in the RAM 22 as given areas, and these are to be used.

In other words, a main table (hereinafter referred to as MT) and a sub-table (hereinafter referred to as ST) correspond to each STA-CEA-CED, and
If the operating status is determined to be normal, the code indicated by an ○ mark will be displayed.
Similarly, if it is determined that there is an abnormality, the codes indicated by the x marks are stored in correspondence with each other, and registration is performed based on these codes.

MT Table 2. .

MT Table 3 ST Note that the MTs in Table 1 are registered with the judgment results during the previous monitoring period, and the MTs in Table 3 are used as the MTs in Table 1 in the next monitoring period. It will be done.

In Figure 10, 'Power ON? ' Determine 401, and if it is Y, 'register all x to MT' Initialize by 402 and start 1 timer set in CPtJ21 to regulate a certain monitoring period.'
After performing step 411, perform all X registration fi' 412 to the "ST" shown in Table 1, and depending on the result of step 304, which STA "cgi" acquires the transmission right? ``421 is determined, and if this becomes, ``MT's CEi:X? "422
Check and if this is Y, perform O registration #431 to CEi of MT-8T, for example, CEl =
In CEA, the status is as shown in Table 2, and "CEI recovery notification" is
At 432, the 5TA-CEi performs processing such as displaying that the 5TA-CEi has recovered from an abnormality to normal and storing in the RAM 22 a message that it can be selected as a communication partner.

If the result in step 422 is N, "Register ST to CEi" 433 is performed. For example, if CE1=CEB, the procedure shown in Table 2 is performed, and 'Timer time up?' ”
While 441 is N, steps 421 and subsequent steps are repeated, and 1 judgment processing ``442'' is performed in response to Y in step 441, and the above operations are repeated through steps 162 and subsequent steps in FIG.

Therefore, for example, if 5TA-CEA and CEC acquire the transmission right next time, but 5TA-CEB and CED do not acquire the transmission right, the state shown in Table 2 will be established. When shown, the contents of MT that showed the previous results are finally updated and become those shown in Table 3.

That is, in step 422, the contents of the following table are executed.

Table 4 Note that ``Abnormality Occurrence Notification'' displays the same display as in step 432 and also indicates that the communication partner cannot be selected.
Processing such as storing to 2 is executed.

Therefore, if all of the 5TA-CEA-CEDs or at least a plurality of 5TA-CEA-CEDs perform the above operations, an abnormality will be determined based on the comparison at the time of "x registration" in Table 4, and a corresponding notification will be issued. At the same time, the recovery to normality is also notified in step 432, and this is done in each STA, so even if any STA loses its monitoring function, the overall monitoring function will not be lost. The reliability of the entire system is improved.

So, step 431 is based on ST only, and MT's ○
Registration may be included in step 442 and step 432
An equivalent result can be obtained by similarly including .

Through the above steps, the time required for relaying each signal and switching and transmitting priority request signals between STAs connected in a loop is greatly reduced, the overall transmission speed is improved, and the minimum necessary signal The handover of transmission rights and acquisition status are reliably confirmed during transmission and reception, and the operating status of each STA is also accurately monitored, achieving high responsiveness and reliability in data transmission and control. .

However, when using FFC11 as a delay element, it is suitable because it also exhibits a waveform shaping effect, but other elements or circuits may also be used, and the delay time can be changed from 1 pit to 1 point as long as there is no practical problem. The same goes for large or small, and the configuration in Figure 4 can be arbitrarily selected according to the conditions, and in Figure 5 (4), the order of each bit is reversed except for the priority code 54. You can also send it.

In addition, the priority may be determined by assigning a code indicating the importance to each transmitted data, and the rank of this is (1) to (
In addition to 1), it may be determined according to the conditions, and the destination address code of the data signal is determined by the STA that has the right to transmit.
Various modifications are possible, such as when all other STA's are designated at the same time, each designated STA may maintain the receiving mode.

In addition, if the validation signal 0Kt as a confirmation signal is omitted, a request signal CT as a takeover signal may be used in place of each of the steps in FIGS. 7 to 10 regarding this.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, the time required for relaying and switching and transmitting priority request signals between STAs connected in a loop is greatly reduced, and the overall transmission speed is improved. At the same time, transmission rights are handed over by the minimum necessary signal transmission and reception, resulting in faster data transmission, higher responsiveness of control status, and overall higher reliability. Exhibits remarkable effects in data transmission and control.

[Brief explanation of drawings]

The figures show an embodiment of the present invention, Fig. 1 is a timing chart showing the transmission and reception status of signals between each STA, Fig. 2 is a block diagram showing the overall configuration, and Fig. 3 is a block diagram showing the configuration of the STA. , Figure 4 is a block diagram showing the specific configuration of STA, Figure 5 shows the configuration of the transmission right request signal, and Figure 5) and (C) show changes in the clear signal, control signal, and preset signal. 6 is a timing chart showing the signal status in each part of FIG. 4, FIG. 7 is an overall flowchart, and FIGS. 8 to 10 are flowcharts showing the lower routine of FIG. 7. It is. 21~24.2R, 2S-・O・Transmission line, 11.431
．． 432..., FFC (flip-flop circuit), 2
1...CPU (7'), 22...RA
M (variable memory), 23...ROM (fixed memory)
, 31...5pc (serial-parallel converter), 37...
psc (parallel-serial converter), 40...5SC (sending circuit), 41.44.48...AND gate, 42
・ ・ Fist ・OR gate, 45 ・ O@ φ inverter, 4611...delay circuit, 47 φ...EXO
R (exclusive OR) gate, 53...Transmission right request code, 54...Priority code, CEA-CED
...@5TA (communication equipment), SR...reception number,
Ss...Transmission number, SO...Transmission output, RI
...Reception input, SW...switcher, CT...
- Transmission right request signal.

Claims (1)

[Claims] Consisting of a plurality of communication devices connected in a loop, a signal received from one transmission path is relayed and transmitted to the other transmission path, and the communication device requesting the transmission right sends the transmission right request signal. In this method, the received signal is transmitted with a time delay of at least 1 bit, and when the transmitter requests the transmission right, the received signal is transmitted with a code indicating the priority of the transmission right. Each communication device is provided with a circuit that compares the priority code with its own priority code and transmits its own priority code in place of the received priority code when the priority code of the self is high. When the received transmission right request signal is different from its own, the communication device transmits a takeover designation signal indicating the communication device that will acquire the transmission right next in response to the transmission right request signal, and each other communication device The transmission right handover method is characterized in that the handover designation signal is relayed and transmitted, and the next communication device that acquires the transmission right acquires the transmission right in accordance with reception of the handover designation signal.