JPS62288980A - Image display memory writing control method - Google Patents

Abstract

PURPOSE:To write data in a frame memory at a high speed without increasing the number of address busses by providing an address control circuit to not only read out data from plural line memories but also write data in the same addresses of plural banks in a memory for picture display. CONSTITUTION:Plural high-speed line memories 31 are read out successively by successive addresses sent from an address control circuit 5 through a line memory address bus 7. Meanwhile, the same address is supplied to plural banks of a memory 4 for picture display of the frame memory from the circuit 5 through a frame memory address bus 8, and the write of data read from memories 31 to the same addresses of plural banks of the memory 4 is terminated simultaneously with completion of read from memories 31, and thus, data is practically quickly written in the frame memory without increasing the number of address busses. Similarly, data are written simultaneously in specific address words of specific banks of the frame memory.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Required] In an ultrasonic diagnostic apparatus equipped with an image display memory consisting of a plurality of banks and reading data in an interleaved manner, the image display memory to multiple banks at the same time,
Or, a line memory with a high speed of -m or more for transferring ultrasound tomographic image data to a specific bank consisting of multiple bits, and a line for transferring data from the line memory to the above-mentioned image display memory. By providing an address control circuit that generates a memory address and a two-image display memory address, image data can be transferred from the line memory to
the same address of multiple banks of the image display memory;
Or, it is designed to simultaneously write to a specific address word in a specific bank.

, [Industrial Application Field] The present invention relates to a write control method for an image display memory (frame memory) of an ultrasonic diagnostic apparatus. - With recent advances in the hardware of ultrasound diagnostic equipment, there is a demand for improved image quality of ultrasound tomographic images displayed on display devices, and the scanning speed of ultrasound signals sent to the living body has increased. As a result, it has become necessary to increase the speed of write/read operations for image display memory (hereinafter referred to as frame memory).

On the other hand, with advances in semiconductor technology, high-speed random access memories (hereinafter referred to as RAM) have become economically available, and these high-speed I/O memories have become economically available. Focusing on the fact that the access time for AM is sufficiently fast compared to the access time for large-capacity frames, the image data of an ultrasound tomographic image is once stored in a set of two high-speed RAMs. The image data stored in the line memory is read out sequentially at high speed to form 5 pieces of write data, and then written all at once to the low-speed frame memory. If applicable.

It is expected that a write control method that makes full use of the frame memory access time can be obtained.

[Prior art and problems to be solved by the invention] FIG. 4 is a diagram illustrating a frame memory writing method in a conventional ultrasound diagnostic device, and shows an example of the configuration of the ultrasound diagnostic device. FIG. 5 is a diagram showing an example of the structure of a frame memory.

Conventionally, the frame memory 4 of an ultrasound diagnostic apparatus has a fifth
As shown in the figure, if the frame memory is composed of, for example, 512 x 512 pixels and has an 8-bank configuration, image data of specific 8 pixels is written to the nth address of each bank, and the image data of the next 8 pixels of each bank is written. The configuration is such that the next eight pixels are written to the n-1th address, -1.

However, in conventional sector-type ultrasound diagnostic equipment, the fourth
As shown in the figure, the image data of ultrasound probe 1 is
/D converter 2 performs analog-to-digital conversion, and the fifth
When transferring the digital data to the frame memory 4 whose details are shown in the figure, the data (indicated by diagonal lines in FIG. 5) corresponding to the sampling points on the sector-type ultrasonic scanning line 41 are transferred to the frame memory 4 whose details are shown in the figure. On the memory 4, each bank is different, and it is not possible to write to multiple banks at the same address at the same time.

Therefore, as shown in Figure 4, for example, if the frame memory is structured to have two address buses (address buses 1, 2) and 8a, two pieces of data can be written at the same time. In order to perform high-speed data writing, there is a problem in that the number of address buses must be further increased.

In view of the above-mentioned conventional drawbacks, the present invention aims to provide a method for writing data into a frame memory at high speed by taking advantage of the high speed of line memory without increasing the number of address buses. be.

[Means for solving problems]

FIG. 1 is a diagram showing an example of the configuration of an image display memory write control system according to the present invention.

The present invention includes an image display memory 4 which is composed of a plurality of memory banks and reads display data by interleaving the output of each bank, and which is sequentially transferred from an image data source (ultrasonic probe) 1. In an image display device that writes image data to the image display memory 4, reads out and displays the written image data, and stores the image data sequentially, a high-speed line memory 3 of - or more sets.
, a read address 7 for the line memory 3 for writing the contents of the line memory 3 to the same address of a plurality of specific banks of the image display memory 4, and the image display memory 4. An address control circuit 5 is provided which generates a write address 8 to the memory for reading out the image data of the plurality of line memos 6-3 and displaying the image in the memory for displaying the image.
The configuration is such that data can be written to the same address in multiple banks of 4 at the same time.

[Effect]

That is, according to the present invention, in an ultrasonic diagnostic apparatus equipped with an image display memory consisting of a plurality of banks and reading data in an interleaved manner, a plurality of banks of the image display memory are read out simultaneously or with a plurality of bits. In order to transfer data of an ultrasound tomographic image to a specific bank consisting of a - set or higher high-speed line memory, and a line memory address when transferring data from the line memory to the image display memory, 5. By providing an address control circuit that generates an address for the image display memory, image data can be transferred from the line memory to the same address in a plurality of banks of the image display memory, or to a specific address in one bank. Since the image data is written simultaneously into the image display memory, the image data that is being serialized can be taken into the image display memory at high speed without increasing the number of address buses for the image display memory.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

The above-mentioned FIG. 1 is a diagram showing a configuration example of the image display memory write control method of the present invention, FIG. 2 is a diagram showing a write operation according to the present invention as a time chart, and FIG.
The figure shows another example of the structure of the image display memory of the present invention, in which the address control circuit 5. and related features are the means necessary to carry out the invention. Note that the same reference numerals indicate the same objects throughout the figures.

Hereinafter, referring to FIG. 1, FIG. 2, FIG. 5, or FIG. 3,
An image display memory (frame memory) write control method according to the present invention will be explained.

First, in FIG. 1, obtained from the ultrasonic probe 1,
The ultrasonic waves reflected from the living body for each scan are transferred to the A/D converter 2.
The reflected wave data for each scan is converted into a digital signal and written into each set 31 of the high-speed line memory 3, which is composed of a plurality of sets.

In a sector-type ultrasonic tomographic image, as shown in FIG. Therefore, it is necessary to write data in the line memory 3 at a different address to the same address on the frame memory 4, which is made up of a plurality of banks.

FIG. 2 is a time chart showing the write operation at this time. For example, the address "b",
c, d, and e” in the control signal generation circuit 10.
Based on the control signal (timing signal) 9 from Although eight banks are shown in FIG. 5, control is performed such that, for example, address "y" is written in each bank (four banks in this figure).

=9- That is, the data to be written to bank 0 of the frame memory 4 is written at address b of group 31 of line memory 3 (shown with diagonal lines,
The same applies hereafter) and reads the data from the write register (
(not shown).

Similarly, the data at address C of set 31 of line memory 3 is stored in the panchromatic write register, the data of address d of set 31 of line memory 3 is stored in bank 5, and the data of address d of set 31 of line memory 3 is stored in bank 4. At the timing (strobe signal) 9 when all the writing is completed, the above four image data are written into each bank of the frame memory 4, for example, at address y''. (See b = e in Figure 5.) In this way, if the access time of the line memory 3 is sufficiently fast compared to the access time of the frame memory (in the example of Figure 4), , 4:l ratio), generally, n pieces of image data lO- are read out from the line memory, and when the readout is completed, they can be simultaneously written to the same address in each bank of the frame memory 4.

In the above embodiment, the same address of a plurality of banks is assigned to adjacent pixels on the frame memory 4, but as shown in FIG. Pixels/elements are stored in the same bank, for example, bank 0.1,
2. - each bit of the word constituting each address (for example, loquat) 7, 6, 5. ．． 4. ) may be assigned.

In this case as well, image data is read from the line memory 3 at the positions on the frame memory 3 (indicated by diagonal lines in FIG. 3) of the image data corresponding to adjacent sampling points on the ultrasound scanning line 41. Even within the same bank, the word address and bit position within the command are different, so in the same way as above, data to be written from the address control circuit 5 to a specific address word of a certain bank (b in Figure 1) It is necessary to generate a line memory address to read "e).

□ In this way, the present invention writes image data sent in time series for each ultrasonic scanning cycle to an image display memory (frame memory) composed of a plurality of banks. A plurality of line memories are provided for temporarily accumulating time-series data for each scanning cycle at high speed, and a plurality of image data stored in each line memory can be written to the frame memory at the same time. Reading from a different address in the line memory 1. The feature is that data is written to a frame memory with a slow access time at the same time when the editing is completed.

〔Effect of the invention〕

As described above in detail, the image display memory write control method of the present invention is applicable to an ultrasonic diagnostic apparatus equipped with an image display memory consisting of a plurality of banks and reading data in an incremental manner. In order to simultaneously transfer the data of the ultrasonic UrN image to multiple banks of display memory, data is transferred to -1- or more high-speed line memories, and from the line memories to -1- the image display memory. By providing an address control circuit that generates a line memory address and an address for one image display memory, image data can be transferred from the line memory to the same address in multiple banks of the image display memory, or to a specific address. Specific address buses of the banks are written at the same time, so it has the effect that image data that is serialized can be taken into the image display memory at high speed without increasing the number of address buses for the image display memory. .

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the configuration of an image display memory write control system according to the present invention. FIG. 2 is a timing diagram showing a write operation according to the present invention. FIG. 4 is a diagram illustrating a writing method to a frame memory in a conventional ultrasonic diagnostic apparatus. FIG. 5 is a diagram showing an example of the configuration of a frame memory. It is. In the drawings, 1 is an ultrasonic probe, and 2 is an A/D converter. 3 is a line memory, and 31 is each set of line memories. 4 is image display memory (frame memory). 41 is an ultrasonic scanning line. 5 is an address control circuit, and 6 is a data bus. 7 is a line memory address bus. 8 is a frame memory address bus. 9 is a control signal. 10 is a control signal generation circuit, c and - are addresses of the line memory. X+V+'-'- is the frame memory address. 7shi-heme 7su no 4 affirmation, Ake 1ε show 1 graduation 5 do

Claims (1)

[Claims] An image display memory (4) consisting of a plurality of memory banks and reading out display data by interleaving the output of each bank, the image being sequentially transferred from the image data source (1). In an image display device that writes data to the image display memory (4) and reads and displays the written image data, one or more sets of high-speed line memories (3) that sequentially hold the image data; to the line memory (3) for writing the contents of the line memory (3) to the same address of a plurality of specific banks or a specific address of a specific bank in the image display memory (4); An address control circuit (5) that generates a read address (7) and a write address (8) to the image display memory (4) is provided, and the image data of the plurality of line memories (3) is read out. , an image display memory write control method characterized in that the image display memory (4) is controlled to write to the same address in a plurality of banks or to a specific address in a specific bank at the same time.