JPH01206391A - Image display device - Google Patents

Abstract

PURPOSE:To miniaturize a scale of the whole device and to reduce the cost by providing an image display memory which can store data of a plural piece portion of each different image, and a control means which can execute a simultaneous display to plural image display means by reading out simultaneously different image data in this memory. CONSTITUTION:By storing the data of a plural piece portion of each different image by utilizing a relation of a physical structure of an image display memory 12 and an address space, and reading out simultaneously different image data in this memory 12 under a control of a control means 19, a simultaneous display to plural image display means 17, 18 is executed. Accordingly, in spite of a fact that plural image display means 17, 18 exist, a hardware for forming the control means 19 is used for both purposes. In such a way, although the title device is a comparatively small scale and inexpensive, it can execute a simultaneous display of plural images being different from each other.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to an image display device that displays an image based on captured image data, and particularly to an image display device that can display different images simultaneously. Concerning what you do.

(Conventional technology) The basic configuration of the image display device is shown in FIG.

This image display device 1 is connected to a processor bus 3,
Under the control of processor 2. That is, image data for display and control data regarding image display are transferred to the display device 1 via the processor bus 3 under the control of the processor 2 . The display bag @1 includes an image display memory 4 that stores image data, a D/A (digital/analog) converter 5 that converts the image data in this memory 4 into an analog signal, and a D/A converter 5 that converts the image data in this memory 4 into an analog signal. A CRT display 6 for visualizing the output and an image display memory 4゜D/
The controller 7 controls the operation of the A converter 5 and the CRT display 6.

In the above configuration, the image data written into the image display memory 4 under the control of the controller 7 is read out again at a predetermined timing in the display system under the control of the controller 7, and is sent to the CRT display 6 via the D/A converter 5.
and displayed. The display image is changed by rewriting the stored contents of the image display memory 4.

By the way, when displaying 1Q images of C images by an X-ray CT device or the like, there are cases where it is desired to display a plurality of different images at the same time. For example, when an imager performs image copying, an image or an eye shadow image is displayed simultaneously with an image for operator observation, or when a plurality of images are compared and examined in image interpretation diagnosis. In order to realize such image display, conventionally, a plurality of display devices 1 as shown in FIG. 5 are prepared, and they are connected to a processor bus 3.
It was designed to transfer different image data to each image display device by connecting to the image display device.

(Problem to be Solved by the Invention) However, according to the above configuration, the image display memory 4
．． D/A converter5. Since the CRT display 6 and controller 7 are all increased, (1) the entire device becomes large-scale. ■There is a disadvantage of second class which is high cost.

SUMMARY OF THE INVENTION The present invention aims to eliminate the above-mentioned drawbacks, and an object of the present invention is to provide an image display device that is relatively small-scale and inexpensive, and that can simultaneously display a plurality of mutually different images. It is in.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides an image display memory capable of storing data for a plurality of mutually different images, and a plurality of images by simultaneously reading out different image data in this memory. and a control means that enables simultaneous display of the images on the image display means.

(Function) The image display memory of conventional devices is usually 1024
A matrix size of approximately 1024 x 1024 has been applied, and with this matrix size, data for three images can be stored if the display size is 640 x 512. Therefore, by utilizing the relationship between the physical structure of this one image display memory and the address space, data for multiple mutually different images can be stored, and different image data in this memory can be simultaneously controlled by a control means. By reading and outputting, simultaneous display on a plurality of image display means can be performed. Therefore, the scale of the image display memory in the present invention is not much different from that of the conventional device. Furthermore, since different image data in the image display memory are simultaneously read out under the control of the control means, even though there are a small number of image display means, the hardware forming the control means can also be used. can do. Therefore, compared to simply arranging a plurality of image display devices 1 (see FIG. 5) in parallel as in the conventional device, it is possible to reduce the size and cost of the entire device.

(Example) Hereinafter, the present invention will be specifically explained with reference to Examples.

In this embodiment, it is assumed that image data in which shading information per pixel is expressed by 4 pixels or more will be handled, and a case will be described in which two different images are each displayed in 256×25671 pixels.

FIG. 1 shows an embodiment of the invention.

J: sea urchin shown in the figure.
10, knot circuit 111 image display memory 12, 1st.
Second shift register 13.14° 1st. 2nd D/A
Converters 15, 16. CRT display 17, 18
．． It has one controller.

Random addresses and random data are transferred via processor bus 3, for example, similar to the conventional device of FIG. The image display memory 12 has a 256x512x4 bit configuration, for example, as shown in FIG. A second dual-port RAM (Random Access Memory) 12a, 12b is applied. FIG. 3 shows the general structure of a dual port RAM.

'This dual port RAM is 64k x 4 bit (25
6 bits) and has a random port and a serial port. The random port is an input/output port for 4-bit parallel data, and the address of this parallel data is specified from the address input terminal. In addition, a serial address can also be specified from this address input terminal, and the 256
Unit line data (indicated by hatching in the figure) is transferred all at once to a shift register inside the RAM in response to data transfer input. Furthermore, the data in this shift register is sequentially sent to the outside from a 4-bit serial port at the timing of the shift clock. A bank of the image display memory 12 is formed by such a dual port RAM.

1 in Figure 1. 2nd dual port RAM12
In a and 12b, rENJ is an enable terminal, rAJ is an address input terminal, ll10'' is a random port, rDTJ is a data transfer input terminal, rsOJ is a serial port, and rsc
J is a shift clock input terminal. Multiplexer 1
0 is under the control of the system controller 19 and the random address is passed through this multiplexer 10 to the first,
The address is input from the address input terminal A to the second dual port RAMs 12a and 12b. The upper (MSB) bit of this random address is used for switching memory banks. In other words, the upper bits of the random address are
It is directly input to the enable terminal EN of the first dual-port RAM 12a, but the second dual-port RAM
The signal is inverted by the NOT circuit 11 and then inputted to the enable terminal EN of 12b.

For this reason, 1. second dual port RAM 12a,
12b are never enabled at the same time. Therefore, in writing image data to the image display memory 12, the first. Second dual port RAM 12a, 1
2b can be treated as a continuous memory space. Further, the serial address, data transfer, shift 1 to clock are output from the system controller 19, and the 1st to 1st clocks are output from the system controller 19. Second dual port RAM 12a.

The signal is input to each input terminal A, DT, and SC provided in 12b. Here, the control means in the present invention is functionally realized by this controller 19. Note that in reality, write enable (WE>) and row address strobe (RAS)
), column address strobe (CAS), etc., but these are omitted for convenience of explanation.

Dual port RAM12 under the control of one controller
The data sent from each serial port SO of a and 12b is transferred to the shift register 13 located at the subsequent stage.
．． 14 through the first. Second D/A converter 15.1
6, where it is converted into an analog signal and then converted into an analog signal. It is adapted to be captured on a second CRT display 17,18. Shift register, D/A converter.

Although there are two CRT displays, they operate at the same timing under the control of the system controller 19.

Here, the first. The second CRT display 17, 18 is an example of image display means in the present invention.

Next, the operation of the embodiment device configured as described above will be explained.

Image data is written into the image display memory 12 as follows.

Under the control of the controller 19, the multiplexer 10
A state is reached in which a random address can be selected and sent to the first and second dual port I RAMs 12a and 12b.
4-bit/pixel image data is written to b. Writing of image data is performed from the random port I10.

Since the upper bit of the random address is used for memory bank switching, the first... Image data is alternatively written to the second dual port RAMs 12a and 12b.

Here, the first . 2nd CT both images X-ray CT
tomographic image obtained with the device) Pl.

Pl respectively 1st. Second CRT display 17.
18, the first dual port R
The data of the first CT images 1 will be written into the AM 12a, and the data of the second CT images 2 will be written into the second dual port RAM 12b. The first and second CTs written in the image display memory 12
Both pictures P1.

P2 is schematically shown.

Image data reading from the image display memory 12 and its display are performed as follows.

Under the control of the controller 19, the multiplexer 10
A state is reached in which a serial address can be selected and sent to the first and second dual port RAMs 12a and 12b. In this state, the serial address is 1. Second dual port RAM 12a.

12b from the address input terminal A at the same time. Also, 1st. Second dual port RAM 12a, 12b
The data transfer input terminals D T , , 1:redata transfer are simultaneously input to the data transfer input terminals DT, , 1:redata transfer is simultaneously input to the data transfer input terminals DT, and a shift clock is simultaneously input from the shift clock input terminal SC. As a result, 1. 2nd dual port RAM1
From the Silal Boat SO of 2a and 12b, the first
．． The data of the second CT images P1 and P2 will be output simultaneously. That is, under the control of the controller 19, different first . The data of both second CT images P1 and P2 are read out simultaneously.

1st. Second dual port RAM 12a.

The C image data output from each serial port SO of 12b is the first one. Second shift 1 register 13
．． 14, the first and second D/A
After being converted into analog signals by converters 15 and 16, the first . It is captured on a second CRT display 17, 18 and is visualized there. Therefore, the first. Both CT images P1 and P2, which are different from each other, are simultaneously displayed on the second display 17, 18.

In this way, in the present embodiment, data for a plurality of different images are stored in the image display memory 12, and the different image data in the memory 12 are simultaneously read out under the control of the controller 19. Since simultaneous display is possible on each CRT display 17 and 18, the controller 19 can be used even though there are two CRT displays. In addition, in the device of this embodiment, the storage capacity of the image display memory 12 is 25
Although the memory size is 6 x 512 x 4 bits, it is normal to use a memory larger than the display matrix even in conventional devices, and the image display memory 12 is not much different in scale from that of the conventional device.

Therefore, like the conventional device, the image display device 1 (see FIG. 5)
Compared to the case where different image displays are made possible by simply arranging several units in parallel, the device of this embodiment can be made smaller as a whole, which is advantageous in terms of installation space, and it is also easy to reduce costs. be. Also, 1st. The display images on the second CRT display 17, 18 are the same as those on the first. This can be easily changed by rewriting the contents of the second dual port RAMs 12a and 12b. Furthermore, the image lfi
When creating shadows, if the main image is displayed on one CRT display and the shooting image is displayed on the other CRT display, the image V will be displayed regardless of the main image display.
It is possible to perform image copying by

Although one embodiment of the present invention has been described above, it goes without saying that the present invention is not limited to the above-described embodiment, and that various modifications can be made.

For example, in the above embodiment, the first. 2nd dual port RA
Although the description has been made regarding the image display memory 1″2 having M12a and M12b, the normal dynamic R
An image display memory may be formed using AM. In addition, the first example in the above embodiment. 2nd (7) T' Near /L/Port R'AM12a.

Since 12b forms a bank of the image display memory 12, the number of RAMs can be appropriately determined depending on the display matrix and the number of bits of image data to be displayed.

Furthermore, in the above embodiment, the first. Although only the case where different images are displayed simultaneously on the second CRT display 17 and 18 has been described, this display mode and both displays 17 and 17
．． A control system may be added to 18 to switch between a mode in which the same image is displayed simultaneously, a mode in which images are displayed using only one display, etc., and each display mode may be switched as necessary. . This control system is configured, for example, from the output side of the image display memory 12 to the first. This can be easily realized by simply controlling the switching of the image data transmission path leading to the second CRT display 17, 18.

Note that three or more images can be displayed simultaneously by storing three or more image data in the image display memory.

[Effects of the Invention] As detailed above, according to the present invention, by utilizing the relationship between the physical configuration of the image display memory and the address space, it is possible to display multiple It is possible to provide an image display device capable of simultaneously displaying two images.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is an explanatory diagram of an image display memory, and Fig. 3 is a dual port R
FIG. 4 is an explanatory diagram of an image in an image display memory, and FIG. 5 is a block diagram of a conventional device. 12... Memory for image display, 17, 18... CRT display (image display means)
, 19...controller (control means). Figure 4 Figure 5

Claims (2)

[Claims] (1) In an image display device equipped with a plurality of image display means and capable of displaying different images for each image display means, an image display memory capable of storing data for a plurality of mutually different images; an image display device comprising: a control means for simultaneously reading out different image data to enable simultaneous display on the image display means; (2) The image display device according to claim 1, wherein the image display memory includes a plurality of dual port RAMs.