JPS62281343A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62281343A JPS62281343A JP61125108A JP12510886A JPS62281343A JP S62281343 A JPS62281343 A JP S62281343A JP 61125108 A JP61125108 A JP 61125108A JP 12510886 A JP12510886 A JP 12510886A JP S62281343 A JPS62281343 A JP S62281343A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- semiconductor chip
- mounting substrate
- semiconductor
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 148
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 238000000034 method Methods 0.000 claims description 17
- 230000003287 optical effect Effects 0.000 claims description 14
- 230000008054 signal transmission Effects 0.000 claims description 4
- 238000013459 approach Methods 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000013307 optical fiber Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
3、発明の詳細な説明
〔産業上の利用分野〕
本発明は、半導体装置に関し、特に、突起電極を介在さ
せて半導体チップを搭載基板に搭載する半導体装置に適
用して有効な技術に関する。[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor device, and is particularly applicable to a semiconductor device in which a semiconductor chip is mounted on a mounting substrate with protruding electrodes interposed therebetween. related to effective techniques.
フェースダウンボンディング方式を採用する半導体装置
は、第15図(要部断面図)で示すように構成されてい
る。つまり、半導体装置は、搭載基板1の搭載面の電極
IAと半導体チップ2の素子面の電極2Aとの間に突起
電極3を介在させ、半導体チップ2を搭載基板lに搭載
している。突起?ii圓3は1例えば、半田材料で構成
されている。A semiconductor device employing the face-down bonding method is configured as shown in FIG. 15 (cross-sectional view of main parts). That is, in the semiconductor device, the protruding electrode 3 is interposed between the electrode IA on the mounting surface of the mounting substrate 1 and the electrode 2A on the element surface of the semiconductor chip 2, and the semiconductor chip 2 is mounted on the mounting substrate l. protrusion? ii The circle 3 is made of, for example, a solder material.
この種の半導体装置は1次の製造方法で形成される。This type of semiconductor device is formed using a primary manufacturing method.
まず、半導体チップ2の電極2A上に、図示しないバリ
アメタル層を介在させて、突起電極3を形成する。突起
電極3は、半田メッキ法、半田浸し法若しくは半田蒸着
法で形成する。First, the protruding electrode 3 is formed on the electrode 2A of the semiconductor chip 2 with a barrier metal layer (not shown) interposed therebetween. The protruding electrodes 3 are formed by a solder plating method, a solder dipping method, or a solder evaporation method.
次に、搭載基板1の電極IA上に前記突起電極3を接触
させ、搭載基板1の搭載面の中心点に半導体チップ2の
素子面の中心点を一致させ、搭載基板1と半導体チップ
2との位置合せを行う。電極IAと突起電極3とは、前
述と同様に1図示しないバリアメタル層を介在させて接
触させる。Next, the protruding electrode 3 is brought into contact with the electrode IA of the mounting substrate 1, and the center point of the element surface of the semiconductor chip 2 is aligned with the center point of the mounting surface of the mounting substrate 1, so that the mounting substrate 1 and the semiconductor chip 2 are connected. Perform alignment. The electrode IA and the protruding electrode 3 are brought into contact with each other with a barrier metal layer (not shown) interposed therebetween, as described above.
次に、リフロ一工程すなわち全体を加熱して突起電極3
を溶融させる熱処理工程を施す。このリフロ一工程によ
って、突起電極3と電極IA、2Aの夫々とを電気的に
接続し、半導体チップ2は搭載基板1に搭載される。リ
フロ一工程は、位置合せが行われた搭載基板1と半導体
チップ2とを自動的に搬送ベルトで搬送し、この搬送中
に配設された電気炉内で行われる。Next, a reflow step, that is, heating the entire protruding electrode 3
A heat treatment process is performed to melt the Through this reflow step, the protruding electrode 3 and each of the electrodes IA and 2A are electrically connected, and the semiconductor chip 2 is mounted on the mounting substrate 1. In the reflow step, the aligned mounting substrate 1 and semiconductor chip 2 are automatically conveyed by a conveyor belt, and are carried out in an electric furnace provided during this conveyance.
前述のリフロー工程において、突起電極3の酸化を防止
するために使用されるフラックスが流動や沸騰を生じ、
半導体チップ2に第16図(要部断面図)に示す外力F
が生じる。また、リフロ一工程において、搬送ベルトの
振動によって外力Fが生じる。このため、リフロ一工程
後に、電極IAと電極2Aとにずれ量δのずれを生じ、
搭載基板1の搭載面の中心点と半導体チップ2の素子面
の中心点との位置合せを精度良く行うことができない。In the above-mentioned reflow process, the flux used to prevent the protruding electrode 3 from oxidizing flows and boils.
An external force F shown in FIG. 16 (cross-sectional view of main parts) is applied to the semiconductor chip 2.
occurs. Further, in the reflow step, an external force F is generated due to vibration of the conveyor belt. Therefore, after one reflow process, a deviation of δ occurs between the electrode IA and the electrode 2A,
The center point of the mounting surface of the mounting substrate 1 and the center point of the element surface of the semiconductor chip 2 cannot be precisely aligned.
前記ずれ及δ、すなわち搭載基板1と半導体チップ2の
夫々の中心点のずれ量は、突起ff1f43の寸法や形
状に依存するが、概ね数十〜数百[μmコにも達する。The deviation and δ, that is, the amount of deviation between the center points of the mounting substrate 1 and the semiconductor chip 2, depend on the dimensions and shape of the protrusion ff1f43, but reach approximately tens to hundreds of micrometers.
この程度のずれ量δは、単に搭載基板1と半導体チップ
2との電気的な接続を目的とする半導体装置においては
問題とならない。しかしながら、半導体チップ2がレー
ザ等の発光素子若しくはフォトダイオード等の受光素子
を有し、かつ、搭載基板1が光ファイバー、先導波路等
の光信号の伝達経路を有する場合は問題になる。発光素
子若しくは受光素子と伝達経路との間で光信号の伝達を
行うためには、数[μm]程度の位置合せ精度が必要と
されろためである。つまり、前述のように、太きなすれ
敗δを生じるので、半導体装置は、電気的な接続を行え
るが、高精度に位置合せを行うことができないという問
題を生じる。This amount of deviation δ does not pose a problem in a semiconductor device whose purpose is simply to electrically connect the mounting substrate 1 and the semiconductor chip 2. However, this becomes a problem when the semiconductor chip 2 has a light emitting element such as a laser or a light receiving element such as a photodiode, and the mounting substrate 1 has an optical signal transmission path such as an optical fiber or a guiding waveguide. This is because positioning accuracy on the order of several [μm] is required to transmit optical signals between the light emitting element or the light receiving element and the transmission path. In other words, as described above, since a large slippage δ occurs, the semiconductor device can perform electrical connection, but there is a problem that alignment cannot be performed with high precision.
本発明の目的は、突起ffi極を介在させて、半導体チ
ップを搭載基板に搭載する半導体装置において、半4体
チップと搭載基板とを電気的に接続すると共に1画者を
高精度に位置合せすることが可能な技術を提供すること
にある。An object of the present invention is to electrically connect a half-quad chip and a mounting board and to align one imager with high precision in a semiconductor device in which a semiconductor chip is mounted on a mounting board by interposing a protruding ffi pole. The goal is to provide technology that enables
本発明の他の目的は、簡単な構成で前記目的を達成する
ことが可能な技術を提供することにある。Another object of the present invention is to provide a technique that can achieve the above object with a simple configuration.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の以下の記述及び添付図面によって説明する。The above and other objects and novel features of the present invention are explained by the following description of the specification and the accompanying drawings.
本願において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
本発明は、半導体チップの第1電極と搭載基板の第2?
I!極との間に突起電極を介在させ、前記半導体チップ
を搭載基板に搭載する半導体装置において、前記半導体
チップの第1mti;;の配設位lrtを、前記突起電
極のりフロー後に生じる復元力が、前記半導体チップの
中心点と搭載基板の中心点とが実質的に一致する方向に
作用するように、前記搭載基板の第2電極の配設位置に
対してずらしたことを特徴とするものである。The present invention provides a first electrode of a semiconductor chip and a second electrode of a mounting substrate.
I! In a semiconductor device in which the semiconductor chip is mounted on a mounting substrate with a protruding electrode interposed between the protruding electrode and the protruding electrode, the restoring force generated after the protruding electrode glue flows causes the first mti; The center point of the semiconductor chip and the center point of the mounting board are shifted relative to the arrangement position of the second electrode of the mounting board so that the center point of the semiconductor chip and the center point of the mounting board substantially coincide with each other. .
前述の手段によれば、リフロ一工程で生じる外力によっ
て、半導体チップの中心点と搭載基板の中心点とにずれ
を生じても、前記突起電極の復元力が夫々の中心点を実
質的に一致するように作用するので1両者を電気的に接
続すると共に、高精度の位置合せをすることができる。According to the above-mentioned means, even if the center point of the semiconductor chip and the center point of the mounting board are misaligned due to an external force generated in one reflow process, the restoring force of the protruding electrode allows the respective center points to substantially coincide. Therefore, it is possible to electrically connect one and the other and to perform highly accurate positioning.
以下、本発明の一実施例ついて、図面を用いて具体的に
説明する。Hereinafter, one embodiment of the present invention will be specifically described using the drawings.
なお、実施例を説明するための全図において、同一機能
を有するものは同一符号を付け、その繰り返しの1説明
は省略する。In all the figures for explaining the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations will be omitted.
〔発明の実施例1〕
本発明の実施例!である半導体装置の概略構成を第1図
(単心体チップ側から見た平面図)で示し、第1図のI
I −II線で切った断面を第2図で示す。[Example 1 of the invention] Example of the invention! The schematic configuration of a semiconductor device is shown in FIG. 1 (a plan view seen from the single-core chip side), and I
A cross section taken along line I-II is shown in FIG.
第1図及び第2図に示すように、半導体装置は、搭載基
板4の搭載面に形成された電極4Aと半導体チップ5の
素子面に形成された電極5Aとの間に突起電極6を介在
させ、半導体チップ5を搭載基板4に搭載している。As shown in FIGS. 1 and 2, the semiconductor device includes a protruding electrode 6 interposed between an electrode 4A formed on the mounting surface of the mounting substrate 4 and an electrode 5A formed on the element surface of the semiconductor chip 5. Then, the semiconductor chip 5 is mounted on the mounting board 4.
半導体チップ5は、レーザ等の発光素子若しくはフォト
ダイオード、フォトトランジスタ等の受光素子が構成さ
れている。半導体チップ5は、例えば、シリコン、ガリ
ウム・ヒ素等で構成されている。The semiconductor chip 5 includes a light emitting element such as a laser, or a light receiving element such as a photodiode or a phototransistor. The semiconductor chip 5 is made of, for example, silicon, gallium arsenide, or the like.
半導体チップ5を搭載する部分の搭載基板4には、光信
号を伝達する光ファイバー、先導波路からなる光信号伝
達経路の光信号受光部又は光信号発光部が構成されてい
る。この光信号受光部若しくは光信号発光部は、前記半
導体チップSの発光素子からの光信号を入力する、若し
くは受光素子に光信号を出力するように構成されている
。搭載基板4としては、例えば、シリコン、炭化シリコ
ン、セラミック等で構成されている。The part of the mounting substrate 4 on which the semiconductor chip 5 is mounted is configured with an optical signal receiving section or an optical signal emitting section of an optical signal transmission path consisting of an optical fiber and a leading waveguide for transmitting an optical signal. This optical signal receiving section or optical signal emitting section is configured to input an optical signal from the light emitting element of the semiconductor chip S or to output an optical signal to the light receiving element. The mounting substrate 4 is made of, for example, silicon, silicon carbide, ceramic, or the like.
突起電極6は、電極4A、5Aの夫々に接続される部分
よりも中心部分の断面々積が大きな太鼓型形状で、その
断面形状が円形状で構成されている。突起電極6は1例
えばSu、Pbの夫々、若しくはSu、Pb、Inの夫
々を主成分とする半田材料で構成されている。The protruding electrode 6 has a drum-shaped shape in which the cross-sectional area of the center portion is larger than that of the portion connected to each of the electrodes 4A and 5A, and the cross-sectional shape is circular. The protruding electrode 6 is made of, for example, a solder material containing each of Su and Pb, or each of Su, Pb, and In as a main component.
搭載基板4の?ti極4A、半導体チップ5の電極5A
の夫々と突起電146との接続は、第3図(要部拡大断
面図)に示すように、夫々、バリアメタルFW4B、5
Bを介在して行われる。バリアメタル層4B、5Bは、
例えば、突起電極6側からAu、Cu、Tiを順次重ね
合せた3層構造で構成されている。Auは、主に、Cu
の酸化防止と、突起電極6とのぬれ性を向上する。Cu
は、主に。Mounting board 4? Ti electrode 4A, electrode 5A of semiconductor chip 5
As shown in FIG. 3 (enlarged sectional view of the main part), the connection between each of these and the protrusion 146 is made using barrier metals FW4B and 5, respectively.
This is done through B. The barrier metal layers 4B and 5B are
For example, it has a three-layer structure in which Au, Cu, and Ti are sequentially stacked from the protruding electrode 6 side. Au is mainly Cu
oxidation prevention and improves wettability with the protruding electrode 6. Cu
Mainly.
AuとTiとのぬれ性を向上する。Tiは、主に。Improves the wettability between Au and Ti. Ti is mainly.
1[4A、5Aの夫々の腐食を防止するバリアメタル層
として働く。1[Works as a barrier metal layer to prevent corrosion of 4A and 5A.
この半導体装置は、第1図及び第2図に示すように、半
導体チップ5の電極5Aの配設位置を、搭載基板4の電
[唄4Aの配設位置に対して、半導体チップ5の中心点
P、方向に、所定のずれ量αだけずらして構成されてい
る。換言すれば、搭載基板4の電極4Aの配設位置は、
半導体チップ5の電極5Aの配設位置に対して、半4体
チップ5の中心点P工(又は搭載基板4の中心点P2)
方向と反対方向に、所定のずれ量αだけずらして構成さ
れている。配設位置をずらした電極4A、m極5Aの夫
々に接続される突起電極6は、傾いた(後述する水平面
とのなす角度0を有する)状態に構成される。As shown in FIGS. 1 and 2, in this semiconductor device, the arrangement position of the electrode 5A of the semiconductor chip 5 is set at the center of the semiconductor chip 5 with respect to the arrangement position of the electrode 4A of the mounting substrate 4. It is configured to be shifted by a predetermined shift amount α in the direction of point P. In other words, the arrangement position of the electrode 4A on the mounting board 4 is as follows.
With respect to the arrangement position of the electrode 5A of the semiconductor chip 5, the center point P of the half-quad chip 5 (or the center point P2 of the mounting board 4)
It is configured to be shifted by a predetermined shift amount α in the opposite direction. The protruding electrodes 6 connected to the electrodes 4A and m-poles 5A whose arrangement positions are shifted are arranged in an inclined state (having an angle of 0 with a horizontal plane, which will be described later).
このように構成される半導体装置は、第4図(半導体装
置の模写図)に示すように、単純なバネ系のモデルに置
き換えることができる。The semiconductor device configured in this manner can be replaced with a simple spring-based model, as shown in FIG. 4 (reproduction diagram of the semiconductor device).
符号6を符してバネで置き換えた突起電顕6は、リフロ
一工程中で溶融した状態を示している。搭載基板4.半
導体チップ5の夫々は剛体と見なすことができる。搭載
基板4の搭載面方向若しくは半導体チップ5の素子面方
向、すなわち水平面方向の突起電極6のバネ定数に′は
、突起′市(船6のバネ定数をに、バネと水平面とのな
す角度をOとすると、次式く1〉で表わすことができる
。The protrusion electron microscope 6 denoted by the reference numeral 6 and replaced with a spring shows a state in which it is melted during one reflow process. Mounting board 4. Each of the semiconductor chips 5 can be considered a rigid body. The spring constant of the protruding electrode 6 in the direction of the mounting surface of the mounting board 4 or the element surface of the semiconductor chip 5, that is, in the horizontal plane direction, is the angle between the spring and the horizontal plane. When O, it can be expressed by the following formula (1).
k’ = k cos20 −・・
Q>第4図に示すモデル化された半導体装置は、バネ定
数に′の2つのバネが水平面方向に並列に接続された状
態であり、全体の水平面方向のバネ定数には、次式〈2
〉で表わすことができる。k' = k cos20 -...
Q> The modeled semiconductor device shown in FIG. 4 has two springs with spring constants ′ connected in parallel in the horizontal direction, and the overall spring constant in the horizontal direction is expressed by the following equation
〉
K = 2 k’ ・・・・・・ 〈
2〉したがって、搭載基板4の中心点Piと半導体チッ
プ5の中心点Plとのずれ量δは、リフロ一工程におい
て生しる水平面方向に作用する外力をドとすると、次式
〈3〉で表わすことができる。K = 2 k' ・・・・・・〈
2> Therefore, the amount of deviation δ between the center point Pi of the mounting board 4 and the center point Pl of the semiconductor chip 5 is expressed by the following equation <3>, where the external force acting in the horizontal direction that occurs in one reflow process is d. can be expressed.
δ =F/K ・・・・・・ く3〉式
く1〉乃至〈3〉は、外力Fが一定の場合、水平面とな
す角度θが大きくなる程、バネ定数Kが大きくなり、ず
れ量δを小さくできることを意味する。つまり、半導体
チップ5の電極5Aの配設位置を、搭載基板4の電極4
Aの配設位置に対して、半4体チップ5の中心点P1方
向に大きくずらす程(ずれitαを大きくする程)、外
力Fによるずれ量δを小さくすることができる。したが
って、半導体装置は、搭載基板4の中心点P2と半導体
チップ5の中心点P、とを実質的に一致するように、突
起電極6の復元力(第1図において矢印へ方向に作用す
る力)が作用するように構成されている。この突起電極
6の復元力は、リフロ一工程後に自動的に作用する。δ = F/K ・・・・・・ Equations 1 to 3 show that when the external force F is constant, the larger the angle θ with the horizontal plane, the larger the spring constant K, and the amount of deviation. This means that δ can be made small. In other words, the arrangement position of the electrode 5A of the semiconductor chip 5 is changed to the position of the electrode 5A of the semiconductor chip 5.
The larger the shift in the direction of the center point P1 of the half-quad chip 5 with respect to the arrangement position of A (the larger the shift itα is), the smaller the shift amount δ caused by the external force F can be. Therefore, in the semiconductor device, the restoring force of the protruding electrode 6 (the force acting in the direction of the arrow in FIG. ) is configured to work. The restoring force of the protruding electrode 6 automatically acts after one reflow process.
電極4Aの配設位置と電極5Aの配設位置とのずれ量α
と、外力Fが加わった場合に外力Fと反対方向に作用す
る突起電極6の復元力との関係を第5図に示す。第5図
は、突起電極6として半田材料を用い、突起電極6の形
状を考慮してwt密に解析した結果を示している。Amount of deviation α between the arrangement position of electrode 4A and the arrangement position of electrode 5A
FIG. 5 shows the relationship between this and the restoring force of the protruding electrode 6 that acts in the opposite direction to the external force F when the external force F is applied. FIG. 5 shows the results of a wt dense analysis using a solder material as the protruding electrode 6 and taking into account the shape of the protruding electrode 6.
第5図に示すように、搭載基板4の′rtL極4Aの配
設位置と半導体チップ5の電極5Aの配設位置とのずれ
量αを大きくする程、突起電極6の復元力(外力Fによ
るずれ量δを小さくシ、中心点p、。As shown in FIG. 5, as the amount of deviation α between the arrangement position of the 'rtL pole 4A of the mounting board 4 and the arrangement position of the electrode 5A of the semiconductor chip 5 is increased, the restoring force of the protruding electrode 6 (external force F Reduce the amount of deviation δ caused by the center point p.
P2の夫々を実質的に一致させる方向に作用する力)が
大きくなる。(the force acting in the direction of substantially matching each of P2) increases.
このように、半導体装置において、半導体チップ5の電
極5Aの配設位置を、突起電極6のリフロ一工程後に生
じる復元力が、半導体チップ5の中心点P工と搭載基板
4の中心点P2とが実質的に−fiする方向に作用する
ように、搭載基板4の電極4Aの配設位置に対してずら
したことにより。In this way, in the semiconductor device, the restoring force generated after the reflow process of the protruding electrode 6 changes the arrangement position of the electrode 5A of the semiconductor chip 5 between the center point P of the semiconductor chip 5 and the center point P2 of the mounting substrate 4. By shifting the position of the electrode 4A of the mounting board 4 so that it acts in the direction substantially -fi.
リフロ一工程で生じる外力Fによって、中心点P0.P
2の夫々がずれ量δのずれを生じても、突起11iti
6の復元力Aが夫々の中心点P、、P2を実質的に一致
するように作用するので1両者を電気的に接続すると共
に、搭載基板4と半導体チップ5とを1H′6精度で位
置合せすることができる。搭載基板4と半導体チップ5
とは、夫々の中心点P0゜P2を数CAtrn]程度の
高精度で位置合せすることができる。The center point P0. P
Even if each of the projections 11it and 2 is shifted by the amount of shift δ,
The restoring force A of 6 acts to substantially align the respective center points P, , P2, so that both are electrically connected and the mounting board 4 and semiconductor chip 5 are positioned with 1H'6 accuracy. Can be combined. Mounting board 4 and semiconductor chip 5
This means that the respective center points P0 and P2 can be aligned with a high precision of several CA trn].
しかも、このように構成される半導体装置は。Moreover, the semiconductor device configured in this way.
リフロ一工程中に生じる外力Fに対して、リフロ一工程
後に、前記復元力Aを自動的に生じさせることができる
。The restoring force A can be automatically generated after one reflow process with respect to the external force F generated during one reflow process.
なお、本実施例1は、4つの突起電極6を有する半導体
装置において、全ての突起電極6を傾けて復元力Aを積
極的に構成したが1本発明は、4つ以上の複数の突起電
極6を有する半導体装置において、全て若しくは少なく
とも4つの突起電極6を傾けて復元力Aを積極的に構成
してもよい。In the first embodiment, in a semiconductor device having four protruding electrodes 6, all the protruding electrodes 6 are tilted to actively create the restoring force A. 6, the restoring force A may be positively constructed by tilting all or at least four protruding electrodes 6.
本実施例■は、前記実施例Iに比入で、突起電極の復元
力をさらに大きくした、本発明の他の実施例である。This embodiment (2) is another embodiment of the present invention in which the restoring force of the protruding electrode is further increased compared to the above-mentioned embodiment I.
本発明の実施例■である半導体装置の概略構成を第6図
(半導体チップ側から見た平面図)で示し。FIG. 6 (a plan view seen from the semiconductor chip side) shows a schematic configuration of a semiconductor device which is Embodiment 2 of the present invention.
第6図の■−■線で切った断面を第7図で示す。FIG. 7 shows a cross section taken along the line ■-■ in FIG. 6.
本実施例■の半導体装置は、第6図及び第7図 ゛に
示すように構成されている。つまり、半導体装置は、前
記実施例■と同様に、半6体チップ5の電極5Aの配設
位置を、搭載基板4の電jJfA4 Aの配設位置に対
して、半導体チップ5の中心点I)i方向に、所定のず
れ景αだけすらして構成されている。これと共に、半導
体装置は、電極5Aの寸法(突8電極6との接続面積)
を、電極4Aの寸法(突起電極6との接続面積)に比へ
て小さく (又は逆に大きく)構成している。The semiconductor device of this embodiment (2) is constructed as shown in FIGS. 6 and 7. In other words, in the semiconductor device, the electrodes 5A of the half-six-piece chip 5 are arranged at the center point I of the semiconductor chip 5 with respect to the arrangement position of the electrode 5A of the mounting substrate 4, as in the above-mentioned embodiment (2). ) It is constructed with only a predetermined shift scene α in the i direction. Along with this, the semiconductor device has dimensions of the electrode 5A (connection area with the protruding 8 electrodes 6).
is configured to be smaller (or conversely larger) than the dimensions of the electrode 4A (the connection area with the protruding electrode 6).
第8図(半導体装置の要部断面図)に電極4A、電極5
Aの夫々の寸法を同一で構成した場合の半導体装置を示
す。第9図(半導体装置の要部断面図)に電極4Aの寸
法に比べて電極5Aの寸法を小さく構成した場合の半導
体装置を示す。第8図。Figure 8 (cross-sectional view of main parts of a semiconductor device) shows electrode 4A and electrode 5.
A semiconductor device in which each dimension of A is configured to be the same is shown. FIG. 9 (a sectional view of a main part of a semiconductor device) shows a semiconductor device in which the dimensions of the electrode 5A are smaller than the dimensions of the electrode 4A. Figure 8.
第9図の夫々に示す半導体装置の突起電極6は、各々、
2点を中心とする半径Rで描かれる太鼓形状で構成され
ている。第8図に示す半導体装置は、電極4A、’iY
!極5Aの夫々の半径比を1:1で構成し、第9図に示
す半導体装置は、電極4A、電Vi!5 Aの夫々の半
径比を1.5 : Lで構成している。このような条件
で構成される第9図に示す半導体装置は、第8図に示す
半導体装置の復元力を1とすると、約2.5倍の復元力
を得ることができる。The protruding electrodes 6 of the semiconductor device shown in each of FIGS.
It is composed of a drum shape drawn with a radius R centered on two points. The semiconductor device shown in FIG. 8 includes electrodes 4A, 'iY
! In the semiconductor device shown in FIG. 9, in which the radius ratio of each pole 5A is 1:1, the electrode 4A, the electrode Vi! The radius ratio of each of the 5A is 1.5:L. The semiconductor device shown in FIG. 9 constructed under such conditions can obtain a restoring force approximately 2.5 times higher than the restoring force of the semiconductor device shown in FIG. 8, which is 1.
このように、半導体装置において、半導体チップ5の電
極5Aの配設位置を、搭載基板4の電極4Aの配設位置
に対して、半導体チップ5の中心点P1方向に、所定の
ずれ景αだけすらして構成すると共に−電tM 5 A
、 電極4Aの夫々の寸法を異なる寸法で構成するこ
とにより、前記実施例Iと同様に、搭載基板4と半導、
体チップ5とを電気的に接続し、かつ両者を高精度で位
置合せすることができると共に、復元力Aをより大きく
することができるので、より両者を高精度で位置合せす
ることができる。In this way, in the semiconductor device, the arrangement position of the electrode 5A of the semiconductor chip 5 is shifted by a predetermined deviation α in the direction of the center point P1 of the semiconductor chip 5 with respect to the arrangement position of the electrode 4A of the mounting substrate 4. As well as composing - electric tM 5 A
, By configuring the electrodes 4A with different dimensions, the mounting substrate 4 and the semiconductor,
Since it is possible to electrically connect the body chip 5 and align the two with high precision, and to increase the restoring force A, it is possible to align the two with high precision.
本実施例■は、前記実施例1.IIの夫々に比べて、突
起電極の復元力をさらに大きくした1本発明の他の実施
例である。This Example (2) is the same as that of Example 1. This is another embodiment of the present invention in which the restoring force of the protruding electrode is further increased compared to each of II.
本発明の実施例■である半導体装置の概略構成を第10
図(半導体チップ側から見た平面図)で示し、第10図
のXI−X[線で切った断面を第11図で示す。The schematic structure of the semiconductor device which is Embodiment ① of the present invention is shown in 10th
(a plan view seen from the semiconductor chip side), and FIG. 11 shows a cross section taken along the line XI-X in FIG. 10.
本実施例■の半導体装置は、第10図及び第11図に示
すように構成されている。つまり、半導体装置は、前記
実施例1.Hの夫々に比へて、搭載基板4に多くの電極
4A□〜4A、を設け、半導体チップ5にも多くの電極
5A、〜5 Asを設け。The semiconductor device of Example 2 is constructed as shown in FIGS. 10 and 11. In other words, the semiconductor device of Example 1 is the same as that of Example 1 above. Compared to each of the electrodes H, more electrodes 4A□ to 4A are provided on the mounting substrate 4, and more electrodes 5A and 5As are provided on the semiconductor chip 5.
各々を突起電極6で接続している。そして、半導体装置
は、前記実施例■、■と同様に、半導体チップ5の電極
5Aよ、5A2の夫々の配設位置を。Each is connected by a protruding electrode 6. In the semiconductor device, the electrodes 5A and 5A2 of the semiconductor chip 5 are arranged in the same manner as in the above embodiments (1) and (2).
搭載基板4の電極4A1.4A、の夫々の配設位置に対
して、半導体チップ5の中心点P工方向に。In the direction of the center point P of the semiconductor chip 5 with respect to the respective arrangement positions of the electrodes 4A1 and 4A of the mounting board 4.
夫々、所定のずれ量α1.α2だけずらして構成されて
いる。夫々のずれ量α1.α2、すなわち、電極5A工
と4A、の配設位置、電tIIi5A、と4A2の配設
位置の夫々は、中心点P1方向に近づくにつれて小さく
構成されている。夫々の復元力A 1gA2は、中心点
P、から半導体チップ5の周辺に向うにつれて大きくな
るように構成されている。A predetermined deviation amount α1. It is configured to be shifted by α2. Each deviation amount α1. α2, that is, the arrangement positions of the electrodes 5A and 4A, and the arrangement positions of the electrodes tIIi5A and 4A2 are configured to become smaller as they approach the direction of the center point P1. Each restoring force A1gA2 is configured to increase from the center point P toward the periphery of the semiconductor chip 5.
また、電極4A、、5A、の夫々の配設位置は、中心点
P1と一致しているのでずらしていない。Furthermore, the positions of the electrodes 4A, 5A are not shifted because they coincide with the center point P1.
このように、半導体装置において、搭載基板4に多くの
電極4A、〜4A、を設け、半導体チップ5にも多くの
atisA工〜5A、を設け、各々を突起電極6で接続
すると共に、電極5A、、5A2の夫々の配設位置を、
電極4A工、4A2の夫々の配設位置に対して、半導体
チップ5の中心点P1方向に、各々、所定のずれ量α4
.α2だけずらして構成することにより、前記実施例I
と同様に、搭載基板4と半導体チップ5とを電気的に接
続し、かつ両者を高精度で位置合せすることができると
共に、複数の突起電極6で復元力をより大きくすること
ができるので、より両者を高精度で位置合せすることが
できる。In this way, in the semiconductor device, the mounting substrate 4 is provided with many electrodes 4A, 4A, and the semiconductor chip 5 is also provided with many atisA electrodes 5A, each connected by the protruding electrode 6, and the electrode 5A. , 5A2, the respective installation positions are as follows.
A predetermined deviation amount α4 is applied to the respective arrangement positions of the electrodes 4A and 4A2 in the direction of the center point P1 of the semiconductor chip 5.
.. By shifting by α2, the above embodiment I
Similarly, it is possible to electrically connect the mounting substrate 4 and the semiconductor chip 5 and align them with high precision, and the restoring force can be increased by the plurality of protruding electrodes 6. Therefore, both can be aligned with high precision.
また、電極4A1.4A2の夫々の配設位置を。Also, the respective arrangement positions of the electrodes 4A1 and 4A2.
電極5A、、5A2の夫々の配設位置に対して、中心点
P工に近づくにつれて各々のずれ量α1.α2を小さく
構成することにより、特に、突起電極6の密度が高くな
る中心点P、側において、@接する突起電極6間の短絡
を低減することができる。With respect to the respective arrangement positions of the electrodes 5A, 5A2, each deviation amount α1. By configuring α2 to be small, it is possible to reduce short circuits between the protruding electrodes 6 in contact with each other, particularly on the center point P side where the density of the protruding electrodes 6 is high.
〔発明の実施例IV)
本実施例■は、前記実施例i、n、mの夫々とは別に、
突起電極の復元力が作用する方向を変えた、本発明の他
の実施例である。[Embodiment IV of the invention] This embodiment
This is another embodiment of the present invention in which the direction in which the restoring force of the protruding electrode acts is changed.
本発明の実施例■である半導体装置の概略構成を第12
図、第13図、第14L7I(半導体チップ側から見た
平面図)の夫々に示す。The schematic structure of the semiconductor device which is the embodiment (1) of the present invention is shown in the 12th
13 and 14L7I (a plan view seen from the semiconductor chip side).
本実施例■の半導体装置は、第12図、第1.3図、@
14図の夫々に示すように構成されている。The semiconductor device of this embodiment (■) is shown in FIGS. 12, 1.3, and @
The configuration is as shown in each of FIGS.
第12図に示す半導体装置は、電極4A、電極5Aの夫
々の配設位置を、半導体チップ5の辺と直交する方向に
ずらし、その方向に作用する復元力Aを有するように構
成されている。The semiconductor device shown in FIG. 12 is configured so that the positions of the electrodes 4A and 5A are shifted in a direction perpendicular to the sides of the semiconductor chip 5, and a restoring force A acts in that direction. .
第13図に示す半導体装置は、電極4A、電極5Aの夫
々の配設位置を、半導体チップ5の辺と平行な方向にず
らし、その方向に作用する復元力Aを有するように構成
されている。The semiconductor device shown in FIG. 13 is configured so that the positions of the electrodes 4A and 5A are shifted in a direction parallel to the sides of the semiconductor chip 5, and a restoring force A acts in that direction. .
第14図に示す半導体装置は、電極4A、電極5Δの夫
々の配設位置を、半導体チップ5の辺に対して45[度
コの角度をなす方向にずらし、その方向に作用する復元
力Aを有するように構成されている。In the semiconductor device shown in FIG. 14, the positions of the electrodes 4A and 5Δ are shifted in a direction forming an angle of 45 degrees with respect to the side of the semiconductor chip 5, and a restoring force A acting in that direction It is configured to have.
いずれの半導体装置においても、復元力Aの作用する方
向は、半導体チップ5の中心点P工に向う方向と直接一
致していないが、所定の復元力Aを合成すると、半導体
チップ5の中心点P、に向う方向と一致している。つま
り、夫々の半導体装置は、前記実施例【と同様に、半導
体チップ5の中心点P1と搭載基板4の中心点P2とを
一致させる方向に復元力Aが作用するように構成されて
いる。In any of the semiconductor devices, the direction in which the restoring force A acts does not directly match the direction toward the center point P of the semiconductor chip 5, but when predetermined restoring forces A are combined, the direction in which the restoring force A acts is It coincides with the direction toward P. That is, each semiconductor device is configured so that the restoring force A acts in the direction of aligning the center point P1 of the semiconductor chip 5 with the center point P2 of the mounting substrate 4, similarly to the above embodiment.
以上、本発明を実施例に基づき具体的に説明したが、本
発明は、前記実施例に限定されるものではなく、その要
旨を逸脱しない範囲において種々変更可能であることは
言うまでもない。Although the present invention has been specifically described above based on Examples, it goes without saying that the present invention is not limited to the above-mentioned Examples and can be modified in various ways without departing from the gist thereof.
例えば、本発明は、前記実施例■と実施例IIIとを組
合わせてもよい。For example, the present invention may combine the above-mentioned embodiment (2) and embodiment (III).
また、本発明は、前記突起電極6を半田材料以外の材料
で溝底してもよい。Further, in the present invention, the groove bottom of the protruding electrode 6 may be made of a material other than solder material.
また5本発明は、前記突起電極6の断面形状をイ1円形
状で構成してもよい。Further, in the present invention, the protruding electrode 6 may have a circular cross-sectional shape.
また、本発明は1発光素子若しくは受光素子を有する半
導体チップと光信号伝達経路を有する搭載基板とで構成
される半導体装置に限定されず、特に、半導体チップと
搭載基板との電気的な接続と高精度の位置合せが要求さ
れる半導体装置に適用することができる。このように構
成される半導体装置は、半導体チップの実装密度を高め
ることができる。Further, the present invention is not limited to a semiconductor device that includes a semiconductor chip having one light-emitting element or a light-receiving element and a mounting board having an optical signal transmission path, but is particularly applicable to electrical connections between the semiconductor chip and the mounting board. It can be applied to semiconductor devices that require highly accurate alignment. A semiconductor device configured in this manner can increase the packaging density of semiconductor chips.
以上、説明したように、本発明によれば、以下に述べる
ような効果を得ることができる。As described above, according to the present invention, the following effects can be obtained.
半導体チップの第1電極と搭載基板の第2電極との間に
突起電極を介在させ、前記半導体チップを搭載基板に搭
載する半導体装置において、前記半導体チップの第1電
極の配設位置を、前記突起電極のリフロー工程後に生じ
る復元力が、前記半導体チップの中心点と搭載基板の中
心点とが実質的に一致する方向に作用するように、前記
搭載基板の第2電極の配設位置に対してずらしたことに
より、リフロ一工程で生じる外力によって、半導体チッ
プの中心点と搭載基板の中心点とがずれを生じても、油
記突8電極の復元力が夫々の中心点を実質的に一致する
ように作用するので、両者を電気的に接続すると共に、
高精度の位置合せをすることができる。In a semiconductor device in which a protruding electrode is interposed between a first electrode of a semiconductor chip and a second electrode of a mounting substrate, and the semiconductor chip is mounted on the mounting substrate, the arrangement position of the first electrode of the semiconductor chip is set as described above. The position of the second electrode on the mounting board is adjusted so that the restoring force generated after the reflow process of the protruding electrode acts in a direction in which the center point of the semiconductor chip and the center point of the mounting board substantially coincide. Even if the center point of the semiconductor chip and the center point of the mounting board are misaligned due to external force generated during the reflow process, the restoring force of the eight oil-shaped electrodes will maintain the respective center points. Since they act to match, they are electrically connected, and
High-precision alignment can be performed.
第1図は、本発明の実施例Iである半導体装置の概a8
構成を示す平面図。
第2図は、第1図の■−■線で切った断面図。
第3図は、第2図に示す半導体装置の要部拡大断面図、
第4図は、第2図に示す半導体装置の模写図。
第5図は、第1図乃至第4回の夫々に示す半導体装置に
おいて、電極の配設位置のずれ量と突起電極の復元力と
の関係を示す図、
第6図は9本発明の実施例■である半導体装置の411
III8構成を示す平面図。
第7図は、第6図の■−■線で切った断面図、第8図及
び第9図は、実施例■の効果を説明するための半導体装
置の要部断面図、
第10図は、本発明の実施例■である半導体装置の概略
構成を示す平面図、
第11図は、第10図のXI−X[線で切った断面図、
第12図乃至第14図は1本発明の実施例!■である半
導体装置の概略構成を示す平面図。
第15図及び第16図は、従来の技術を説明するだめの
半導体装置の要部断面図である。
図中、4・・搭載基板、5・・半導体チップ、6・・突
起電極、4A、4A、、4A、、5A、5Aよ。
5A、・・電極、Pl、P2・中心点、α、α1.α2
゜δ・・・ずれ量、F・外力である。FIG. 1 shows an outline a8 of a semiconductor device which is Embodiment I of the present invention.
A plan view showing the configuration. FIG. 2 is a sectional view taken along the line ■-■ in FIG. 1. 3 is an enlarged cross-sectional view of a main part of the semiconductor device shown in FIG. 2, and FIG. 4 is a replica of the semiconductor device shown in FIG. 2. FIG. 5 is a diagram showing the relationship between the amount of deviation in the arrangement position of the electrode and the restoring force of the protruding electrode in the semiconductor devices shown in each of FIGS. 1 to 4, and FIG. Example 411 of semiconductor device (■)
FIG. 3 is a plan view showing the III8 configuration. FIG. 7 is a cross-sectional view taken along the line ■-■ in FIG. 6, FIGS. 8 and 9 are cross-sectional views of main parts of a semiconductor device for explaining the effects of Example (■), and FIG. , FIG. 11 is a sectional view taken along the line XI-X in FIG. 10, FIGS. Example! FIG. 2 is a plan view showing a schematic configuration of a semiconductor device; FIGS. 15 and 16 are sectional views of essential parts of a semiconductor device for explaining the conventional technology. In the figure, 4...mounting board, 5...semiconductor chip, 6...protruding electrodes, 4A, 4A, 4A, 5A, 5A. 5A, electrode, Pl, P2, center point, α, α1. α2
゜δ is the amount of deviation, F is the external force.
Claims (7)
の間に突起電極を介在させ、前記半導体チップを搭載基
板に搭載する半導体装置において、前記半導体チップの
第1電極の配設位置を、前記突起電極のリフロー工程後
に生じる復元力が、前記半導体チップの中心点と搭載基
板の中心点とが実質的に一致する方向に作用するように
、前記搭載基板の第2電極の配設位置に対してずらした
ことを特徴とする半導体装置。(1) In a semiconductor device in which a protruding electrode is interposed between a first electrode of a semiconductor chip and a second electrode of a mounting substrate, and the semiconductor chip is mounted on the mounting substrate, the arrangement position of the first electrode of the semiconductor chip The second electrode of the mounting substrate is arranged so that the restoring force generated after the reflow process of the protruding electrode acts in a direction in which the center point of the semiconductor chip and the center point of the mounting substrate substantially coincide. A semiconductor device characterized by being shifted in position.
位置に対して、半導体チップの中心点方向にずらしたこ
とを特徴とする特許請求の範囲第1項に記載の半導体装
置。(2) The semiconductor according to claim 1, wherein the first electrode is arranged at a position shifted toward the center of the semiconductor chip with respect to the second electrode. Device.
位置に対して、半導体チップの中心点方向にずらしたこ
とを特徴とする特許請求の範囲第1項に記載の半導体装
置。(3) The semiconductor according to claim 1, wherein the arrangement position of the second electrode is shifted toward the center point of the semiconductor chip with respect to the arrangement position of the first electrode. Device.
を、前記突起電極を介在させた全ての接続部分又は一部
の接続部分において、ずらしたことを特徴とする特許請
求の範囲第1項乃至第3項に記載の夫々の半導体装置。(4) A patent claim characterized in that the arrangement position of the first electrode and the arrangement position of the second electrode are shifted in all or some connection parts with the protruding electrode interposed therebetween. Each of the semiconductor devices according to the ranges 1 to 3 above.
同等若しくは第2電極の面積と異なることを特徴とする
特許請求の範囲第1項乃至第4項に記載の夫々の半導体
装置。(5) Each of the semiconductors according to claims 1 to 4, wherein the area of the first electrode is approximately equal to or different from the area of the second electrode. Device.
のずれ量は、前記半導体チップの中心点に近づくにつれ
て小さく構成されていることを特徴とする特許請求の範
囲第1項乃至第5項に記載の夫々の半導体装置。(6) The amount of deviation between the arrangement position of the first electrode and the arrangement position of the second electrode is configured to become smaller as it approaches the center point of the semiconductor chip. Each of the semiconductor devices described in Items 1 to 5.
子が構成され、前記搭載基板には、前記半導体チップの
発光素子からの光信号を入力する、若しくは受光素子に
光信号を出力する光信号伝達経路が構成されていること
を特徴とする特許請求の範囲第1項乃至第6項に記載の
夫々の半導体装置。(7) The semiconductor chip is configured with a light emitting element or a light receiving element, and the mounting board is provided with optical signal transmission for inputting an optical signal from the light emitting element of the semiconductor chip or outputting an optical signal to the light receiving element. 7. Each of the semiconductor devices according to claim 1, wherein a path is formed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61125108A JPH0616521B2 (en) | 1986-05-29 | 1986-05-29 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61125108A JPH0616521B2 (en) | 1986-05-29 | 1986-05-29 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS62281343A true JPS62281343A (en) | 1987-12-07 |
JPH0616521B2 JPH0616521B2 (en) | 1994-03-02 |
Family
ID=14902046
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61125108A Expired - Lifetime JPH0616521B2 (en) | 1986-05-29 | 1986-05-29 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0616521B2 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06132353A (en) * | 1992-04-06 | 1994-05-13 | Mega Chips:Kk | Semiconductor device |
JP2008028284A (en) * | 2006-07-25 | 2008-02-07 | Matsushita Electric Ind Co Ltd | Semiconductor mounting construction |
JP2009224471A (en) * | 2008-03-14 | 2009-10-01 | Nec Corp | Electronic component and method for manufacturing the same |
JP2012156374A (en) * | 2011-01-27 | 2012-08-16 | Fujitsu Ltd | Connection structure of substrate, substrate set, photosensor array device and method of connecting substrate |
JP2013225749A (en) * | 2012-04-20 | 2013-10-31 | Kyocera Corp | Piezoelectric device and module component |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4518664B2 (en) * | 2000-12-13 | 2010-08-04 | 京セラ株式会社 | Wiring board mounting structure and semiconductor device |
JP5761671B2 (en) * | 2012-01-23 | 2015-08-12 | 京セラサーキットソリューションズ株式会社 | Assembly of multi-cavity wiring board and assembly method of multi-cavity wiring board |
US10217718B1 (en) | 2017-10-13 | 2019-02-26 | Denselight Semiconductors Pte. Ltd. | Method for wafer-level semiconductor die attachment |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57112039A (en) * | 1980-12-29 | 1982-07-12 | Fujitsu Ltd | Manufacture of semiconductor device |
JPS62170633U (en) * | 1986-04-21 | 1987-10-29 |
-
1986
- 1986-05-29 JP JP61125108A patent/JPH0616521B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57112039A (en) * | 1980-12-29 | 1982-07-12 | Fujitsu Ltd | Manufacture of semiconductor device |
JPS62170633U (en) * | 1986-04-21 | 1987-10-29 |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06132353A (en) * | 1992-04-06 | 1994-05-13 | Mega Chips:Kk | Semiconductor device |
JP2008028284A (en) * | 2006-07-25 | 2008-02-07 | Matsushita Electric Ind Co Ltd | Semiconductor mounting construction |
JP2009224471A (en) * | 2008-03-14 | 2009-10-01 | Nec Corp | Electronic component and method for manufacturing the same |
US20110269306A1 (en) * | 2008-03-14 | 2011-11-03 | Kenji Fukuda | Solder bump, electronic component and method for manufacturing the electronic component |
US8607446B2 (en) * | 2008-03-14 | 2013-12-17 | Nec Corporation | Method of manufacturing an electronic component |
JP2012156374A (en) * | 2011-01-27 | 2012-08-16 | Fujitsu Ltd | Connection structure of substrate, substrate set, photosensor array device and method of connecting substrate |
JP2013225749A (en) * | 2012-04-20 | 2013-10-31 | Kyocera Corp | Piezoelectric device and module component |
Also Published As
Publication number | Publication date |
---|---|
JPH0616521B2 (en) | 1994-03-02 |
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