JPS6227413B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram controlled data processing device.

A microprogram-controlled data processing device that has multiple microprogram execution levels with different priorities generally has hardware/firmware resources that are commonly used by the microprograms at each execution level. It has hardware/firmware resources that are used exclusively by If an interrupt with a higher priority level occurs while a microprogram at a certain level is being executed, the execution level of the microprogram is switched to the level that caused the interrupt, and in response, the hardware/ The firmware resources are also switched to the resources of the corresponding execution level.

For example, arithmetic units, microinstruction analysis decoders,
Sequencers, etc. are common hardware/firmware resources, but firmware work registers, indicator registers, accumulators,
Microinstruction registers and the like are hardware/firmware resources dedicated to each level, and these are switched to the registers, accumulators, etc. of the corresponding level according to the execution level, as described above. The reason for this kind of control is that special consideration is given to the allocation of hardware/firmware resources when the execution of a high-priority microprogram that was interrupted midway is finished and control is returned to the original level. This is to avoid having to do so.

However, this has the drawback that as the number of execution levels of microprograms increases, hardware/firmware resources are multiplexed and costs increase.

In addition, in low-cost, small-scale data processing equipment, hardware/firmware resources cannot be multiplexed due to cost constraints, so this is countered by minimizing the number of microprogram execution levels; Nowadays, as operations within devices become more complex, they have the disadvantage of not being able to provide sufficient processing power.

SUMMARY OF THE INVENTION An object of the present invention is to provide a microprogram-controlled data processing device that eliminates the above-mentioned conventional drawbacks.

The data processing device of the present invention is a microprogram-controlled data processing device having a plurality of interrupt levels with different priorities and a plurality of microprogram execution levels corresponding to the interrupt levels. a specific hardware/firmware resource commonly used by a plurality of microprogram execution levels, and a method for storing the contents of the specific hardware/firmware resource in a high-speed register by the specific plurality of microprogram execution levels. an indicator means that can be set and reset according to the specific plurality of microprogram execution levels; determining the set/reset state of the indicator means when a corresponding interrupt occurs, and in response, saving the contents of the specific hardware/firmware resource to the high speed register by the storage means; and control means for determining whether or not.

Next, the present invention will be explained in detail with reference to the drawings.

The figure is a block diagram showing an embodiment of the microprogram-controlled data processing device of the present invention. This embodiment includes a microprogram storage memory 1, a microinstruction register 2, a microinstruction analysis decoder 3, a microinstruction address register 4, a return address stack 5, an interrupt control circuit 6, and a level 1
and level 2 firmware work register 7a, level 3 firmware work register 7b, level 1 and level 2 accumulator 8a, level 3 accumulator 8b, arithmetic unit 9, level 1 and level 2 indicator 1
0a', a level 3 indicator 10b, a high-speed memory 11 for firmware work, and a status indicating flip-flop 12 (hereinafter referred to as FF12).

In this embodiment, in order to simplify the explanation, the execution levels of the microprogram are assumed to be three levels (level 1, level 2, and level 3), which is a relatively small number of levels. firmware working register 7, accumulator 8 and indicator register 1 of hardware/firmware resources that should be
There are only two sets of 0, one used in common at level 1 and level 2, and one used exclusively at level 3, and the former are reference numbers 7a, 8a and 1, respectively.
0a, and the latter by 7b, 8b and 10b, respectively.

Now, each microinstruction of the microprogram stored in the microprogram storage memory 1 is read from the address specified by the microinstruction address register 4 and stored in the microinstruction register 2. This microinstruction is decoded by the microinstruction analysis decoder 3, and specified processing is executed according to the decoding result. Thus,
The address register 4 specifies the addresses of microinstructions to be executed one after another, reads them into the register 2, and continues processing.

Now, a case will be explained in which a level 2 interrupt having a higher priority occurs while a level 1 microprogram is being executed.

This interrupt is supplied to the interrupt control circuit 6 as an interrupt request signal 22. This interrupt control circuit 6 has reference numerals 21, 22 and 23 corresponding to level 1, level 2 and level 3, respectively.
There is an interrupt request signal 21, but since level 1 is currently being executed, the interrupt request signal 21 for level 1 is "1" and the others are "0". When a level 2 interrupt occurs, the interrupt request signal 22 further becomes "1". The control circuit 6 is this 2
Accept two interrupt requests, compare their priorities,
When it is determined that a level 2 interrupt request, which has a higher priority than the level 1 currently being executed, has occurred, a command 40 is generated, the contents of the address register 4 are saved and stored in the return address stack 5, and a predetermined interrupt request is issued. The execution start microinstruction address 43 of the level 2 microprogram execution level currently being executed is set in the register 4. Thus, the program jumps to the start address of the level 2 microprogram, and thereafter executes the level 2 microprogram.

Now, in the first step of this level 2 microprogram, the level 2 processing firmware first determines the state of the FF 12. If this FF12 is set, the level 2 processing firmware saves and stores the contents of the firmware work register 7a, accumulator 8a, and indicator register 10a in the firmware work high-speed memory 11, and then
Executes actual level 2 processing. Hello again,
If the FF 12 has been reset, the above-mentioned save processing is not performed and level 2 processing is directly executed.

In this way, when the execution of the level 2 processing is completed, the level 2 firmware determines the state of the FF 12, and if this is set, stores the above-mentioned saved and stored contents from the firmware work high speed memory 11 in the respective registers 7a. , are returned to the accumulator 8a and register 10a. After that, execute an interrupt return microinstruction, thereby returning the address of the level 1 microinstruction stored in the return address stack 5 to the microinstruction address register 4, and reading this microinstruction to the microinstruction register 2. The level 1 microprogram is restarted from the interrupted part.

Moreover, if FF12 is not set, the register 7a and the accumulator 8a
Then, without restoring the contents of the register 10a, the interrupt return instruction is immediately executed to return to the level 1 microprogram.

In this way, the hardware/firmware resources register 7a, accumulator 8, and register 10a are commonly used between the microprogram execution levels of level 1 and level 2, and when it is not necessary, these common resources are By not saving and restoring the contents of the file, it is possible to save wasted time required for saving and restoring the contents.

Whether saving and restoring is necessary is determined by setting and resetting the FF 12, which is set and reset by a microinstruction in the level 1 program. That is, in the level 1 microprogram, register 7a, accumulator 8a
Alternatively, when register 10a is used, a microinstruction to set FF 12 is executed and set prior to its use. Also, for example, if level 1 firmware is in an idle loop, the contents of these resources have no meaning, so microinstructions can be used to
Reset FF12. Thus, FF12
A high-priority level 2 microprogram that commonly uses this resource receives information about whether the contents of these common resources should not be destroyed by the level 1 microprogram by setting or resetting the resource. tell to. When the level 2 microprogram is informed that the contents of these common resources must not be destroyed, the microprogram immediately saves these contents to the memory 11 and then uses these common resources. After use, the saved contents are returned to the original state using a microprogram, and then the common resources are returned to the level 1 program and this program is controlled to resume from the point where it was interrupted. . In this way, between the microprograms at different levels, the firmware work register 7a, accumulator 8a, and indicator register 10a, which are conventionally exclusive hardware and software resources, are transferred to the level 1 and level 2 microprograms. It is possible to provide a means that is commonly used in programs, and which minimizes the time loss caused by short return.

In this embodiment, level 3 has dedicated hardware/firmware resources such as register 7b, accumulator 8b, and indicator register 10b. When the interrupt signal 23 becomes "1", the interrupt control circuit 6 uses the command 42 to transfer these resources to the register 7a, accumulator 8a, and register 10a, respectively.
and introduce it into the operating circuit. When the level 3 processing is completed, the interrupt control circuit 6 switches these resources again via the command 42, returns them to the original state, and restarts the original level 2 or level 1 program from where it was interrupted. . Of course, in this case, completely different hardware/firmware resources are used, so there is no need to save or restore the contents just by switching them.

As mentioned at the beginning, in this embodiment, for the sake of simplicity, there are only three different priority levels, among which level 1 and level 2.
However, only the above described an example in which firmware working register 7a, accumulator 8a, and indicator register 10a are used in common. Furthermore, for example, to use these resources in common at three different levels, one can do as follows.
In this case, use FF12, FF12-1 for level 1
and FF12-2 for level 2, and when using these resources in microprograms at each level, FF12 at its own level.
Set it before use. For example, when using a common resource in a level 2 microprogram, set FF12-2. In addition, when starting a level 2 or level 3 interrupt program, the FF of the next lower level (that is, level 3
In the case of a level 2 interrupt, FF12-2 is determined, and in the case of a level 2 interrupt, FF12-1) is determined,
Based on this, it may be determined whether or not it is necessary to save and restore the contents of the resource.

Thus, it is clear that the greater the degree of multiplexing, in which the same resource is used multiplexed between many levels, the more effective the present invention becomes.

In addition, FF12 of this embodiment and the FF described above
The FF 12-1, FF 12-2, etc. can also utilize a part of the firmware working high-speed memory 11 without adding any special hardware.

As described above, using the present invention, between multiple microprogram execution levels with different priorities,
Hardware such as various register accumulators that are traditionally used exclusively by each level/
It is possible to provide a means for commonly using firmware resources and minimizing an increase in the overhead required for saving and restoring contents that must be done in return for this common use.

This makes it possible to achieve economical or highly efficient interrupt processing in the microprogram-controlled data processing device.

[Brief explanation of the drawing]

The figure is a block diagram showing one embodiment of the present invention. In the figure, 1...Memory for storing microprograms, 2...Microinstruction register, 3...Microinstruction analysis decoder, 4...Microinstruction address register, 5...Return address stack, 6...Interrupt control circuit , 7a... Level 1 and level 2 firmware work register, 7
b...Farmware work register for level 3, 8a...Accumulator for level 1 and level 2, 8b...Accumulator for level 3, 9
...Arithmetic unit, 10a...Level 1 and Level 2
10b... Indicator for level 3, 11... High speed memory for firmware work, 12... Status indicating flip-flop (FF12).

Claims (1)

[Claims] 1. In a microprogram-controlled data processing device having a plurality of interrupt levels with different priorities and a plurality of corresponding microprogram execution levels, a specific plurality of microprogram execution levels among the microprogram execution levels are common. a specific hardware/firmware resource to be used; storage means for storing the contents of the specific hardware/firmware resource in a high-speed register according to the specific plurality of microprogram execution levels; indicator means that can be set and reset depending on the microprogram execution level; and an interrupt corresponding to one of the plurality of specific microprogram execution levels having a higher priority than the indicator means that occurs while a certain microprogram execution level is being executed. When determining the set/reset state of the indicator means and responsively determining the set/reset state of the indicator means,
A microprogram-controlled information processing device comprising: control means for determining whether or not the contents of firmware resources are to be saved in the high-speed register by the storage means.