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JPS62217326A - Computer capable of storing and switching plural os - Google Patents

Computer capable of storing and switching plural os

Info

Publication number
JPS62217326A
JPS62217326A JP6141086A JP6141086A JPS62217326A JP S62217326 A JPS62217326 A JP S62217326A JP 6141086 A JP6141086 A JP 6141086A JP 6141086 A JP6141086 A JP 6141086A JP S62217326 A JPS62217326 A JP S62217326A
Authority
JP
Japan
Prior art keywords
switching
input
memory area
executed
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6141086A
Other languages
Japanese (ja)
Inventor
Michihiko Negita
禰宜田 迪彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP6141086A priority Critical patent/JPS62217326A/en
Publication of JPS62217326A publication Critical patent/JPS62217326A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/48Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806Task transfer initiation or dispatching
    • G06F9/4843Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To attain the restart of processing of plural OS at a time point when they are discontinued again after they are switched to other OS and executed, by performing the exchange among the memory areas having the same address and therefore discontinuing these OS at an optional time point. CONSTITUTION:The input/output devices 16 and 17 set the corresponding FF out of those of an FF group 18 when the input/output instructions are accepted and then reset them at the time of said input/output instructions are over. A switch means 12 validates a memory area 15 and a status register 21 and stores the hardware information on a program counter, a register, a flag, etc., which are under execution in the register 21 in case a switch request is produced to another OS 2 during execution of an OS 1 out of plural OS. If a switch request is given again to the OS 1 during execution of the OS 2, the program counter, etc., are stored in a status register 20 and then switched to a memory area 15 and the register 21 after all FF of the group 18 are reset.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はコンピュータに関し、特に複数のosを格納し
、指示により切替えて一時には−っωSを実行する方式
に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a computer, and more particularly to a system in which a plurality of OSs are stored and are switched according to instructions to execute -ωS at the same time.

〔従来の技術〕[Conventional technology]

従来、一つのCPUで複数のOSヲ切替て実行する方式
としては次の様な方式があった。
Conventionally, there have been the following methods for switching and executing multiple OSs with one CPU.

(1)  OSを再ロードする方式。(1) Method of reloading the OS.

(2)  メモリ上に複数のオペレーティングシステム
を格納し、それ等の切替を行うスーパバイザプログラム
を有する方式。
(2) A system that stores multiple operating systems in memory and has a supervisor program that switches between them.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の(1)08再ロ一ド方式では、切替に時
間がかかる。又、他のOSに切替た後元のOSに戻った
場合、的のOS全体の情報がないので切替前の状態に戻
れない欠点がおる。又(2)スーパバイザによシ抜数O
Sを切替る方式では、例えば割込ベクトルを解析して現
在実行中のOSへ制御を渡す叫スーパバイザの処理が複
雑となる。又、単独で使用する場合のOSとは、割込ベ
クトル解析部が異なる等OSの構造が異るという欠点が
おる。
In the conventional (1)08 reload method described above, switching takes time. Furthermore, when returning to the original OS after switching to another OS, there is a drawback that it is not possible to return to the state before switching because there is no information about the entire target OS. Also, (2) the number of supervisors is O
In the method of switching S, for example, the processing of a supervisor who analyzes an interrupt vector and passes control to the currently executing OS becomes complicated. Furthermore, there is a drawback that the structure of the OS is different from the OS when used alone, such as the interrupt vector analysis section being different.

本発明の目的は、同一アドレス帯を有するメモリ領域を
切替えることによシ、複数のOSを任意の時点で中断し
、再び中断した時点から処理を再開できる複数OS格納
切替可能コンピュータを提供することにある。
An object of the present invention is to provide a computer capable of storing and switching multiple OSs, which can suspend multiple OSs at any time and resume processing from the point of suspension by switching memory areas having the same address range. It is in.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の複数OS格納切替可能コンピュータの構成は、
同一アドレス帯を有するメモリおよび複数の入出力装置
を備えたコンピュータシステムにおいて、前記メモリの
同一アドレス帯の複数のメモリ領域を切替える切替手段
と、各メモリ領域に対応する実行中のハードウェア情報
を格納する格納手段と、前記入出力装置が入出力動作実
行中である事を記憶するフリップフロップ群とを有し、
格納された前記ハードウェア情報をセットし、前記秒数
のメモリ領域にそれぞれ格納されている複数のOSの一
を実行中に他のOSへの切替要求が手段に格納し、この
時に前記入出力装置の何れがか動作中であれば前記フリ
ップフロップ群のそれぞれ対応する各フリップフロップ
をセットし、前記動作が終了した時前記各フリップフロ
ップをリセットして、前記切換手段にょシ現在実行中の
前記メモリ領域およびこのメモリ領域に対応する前記格
納手段を的記他のOSが格納されているメモリ領域およ
びこのメモリ領域に対応する前記格納手段に切替え、こ
の切替前の前記格納手段に格納されている前記ハードウ
ェア情報をセットして切噴後のOSを実行するようにし
て前記複数のosをその実行中の任意の時点で中断し、
他のosを実行後再び中断されたOSの処理を行なうこ
とを特徴とする。
The configuration of the computer capable of storing multiple OSs and switching according to the present invention is as follows:
In a computer system equipped with a memory having the same address band and a plurality of input/output devices, a switching means for switching a plurality of memory areas in the same address band of the memory, and storing information on the hardware being executed corresponding to each memory area. and a group of flip-flops for storing that the input/output device is performing an input/output operation,
The stored hardware information is set, and while one of the plurality of OSs respectively stored in the memory area for the number of seconds is running, a request for switching to another OS is stored in the means, and at this time, the input/output information is stored in the means. If any of the devices is in operation, each of the flip-flops in the group of flip-flops is set, and when the operation is completed, each flip-flop is reset, and the switching means is set to the flip-flop that is currently being executed. Switching a memory area and the storage means corresponding to this memory area to a memory area in which another OS is stored and the storage means corresponding to this memory area, and storing data in the storage means before this switching. interrupting the plurality of OSs at any point during execution by setting the hardware information and executing the OS after the injection;
The feature is that after executing another OS, the process of the interrupted OS is resumed.

〔実施例〕〔Example〕

次鴫本発明の実施例について図面を参照して説明する。 Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例の構成図である。FIG. 1 is a block diagram of an embodiment of the present invention.

第1図において、本発明の一実施例は複数の入出力装置
16 、17と、一つのCPUIIと、各々に異るOS
を格納するだめの同一アドレス帯を有する複数のメモリ
領域を持つメモリ3oと、各メモリ領域で動作している
OSが他へ切替るとき現在実行中のハードウェア情報を
格納し、再びosに切替えられた場合、格納されたハー
ド、ウェア情報を再セットする手段19〜21と、入出
力装置が入出力動作を実行中であることを示すフリップ
フロップ群I8と、メモリ領域を切替る手段12とを有
している。
In FIG. 1, one embodiment of the present invention includes a plurality of input/output devices 16 and 17, one CPU II, and a different OS for each.
Memory 3o has multiple memory areas with the same address range for storing information, and when the OS running in each memory area switches to another, it stores the currently running hardware information and switches to the OS again. means 19 to 21 for resetting the stored hardware and hardware information, a flip-flop group I8 indicating that the input/output device is performing an input/output operation, and means 12 for switching memory areas. have.

格納手段19〜21は実行中の状態すなわちプログラム
カウンタ、各種レジスタおよび7ラグ岬ツバ−ドウエア
情報を格納するステータスレジスタで、切換手段12に
ょヤ、同一アドレス帯を有するメモリ領域と共に切換え
られるように構成されている。
The storage means 19 to 21 are status registers for storing the running state, that is, the program counter, various registers, and seven-lag hardware information, and are configured to be switched together with the memory area having the same address band as the switching means 12. has been done.

各種入出力装置x6.17は人出方命令受付時に717
ツプ70ツブ群18の内対応するフリップフロップをセ
ットし、その入出力命令が終了すると7リツプ70ツブ
をリセットする。
Various input/output devices x6.17 are 717 when receiving orders for people to leave.
The corresponding flip-flop in the group 18 of 70 chips is set, and when the input/output command is completed, the 7 chips 70 are reset.

切替手段12けメモリ領域15およびステータスレジス
タ21を有効とし、複数OSの1つの081を実行して
いる場合に他のos2への切替要求が発生した場合、現
在実行中のプログラムカラ/り、レジスタおよびフラグ
等のハードウェア情報をステータスレジスタ21に格納
する。コツトき、倒れかの入手力itが動作中であると
ンリッ]\6− プフロップ群18のうち1以上がセットされている。
When the switching means 12 memory area 15 and the status register 21 are enabled and a request to switch to another OS2 occurs when one of the multiple OSs 081 is running, the program color/register currently being executed is and hardware information such as flags are stored in the status register 21. It's good to know that the power to obtain it is in operation]\6- One or more of the flop group 18 is set.

この場合は、入出力命令の終了を待つため、フリップフ
ロップ群18のすべてがリセットされた後に、切替手段
12はメモリ領域14とステータスレジスタ20には、
OS2で以前に実行していたプログラムカウンタ等が格
納されておシ、それを再セットして082を実行する。
In this case, in order to wait for the completion of the input/output command, after all of the flip-flops 18 are reset, the switching means 12 stores the memory area 14 and the status register 20.
The program counter and the like previously executed in OS2 are stored, and they are reset and 082 is executed.

OS2実行中に再びOS1に切替要求が発生した場合、
プログラムカウンタ等をステータスレジスス20に格納
しフリップフロップ群18がすべてリセットされるのを
待って、メモリ領域15及びステータスレジスタ21に
切替る。
If a request to switch to OS1 occurs again while OS2 is running,
The program counter and the like are stored in the status register 20, and after waiting for all the flip-flops 18 to be reset, switching is made to the memory area 15 and the status register 21.

その後、ステータスレジスタ21に格納されているプロ
グラムカウンタ、各種レジスタ及びフラグ等のハードウ
ェア情報を再セットして081を実行すると、OS1は
OS2に切替えられた時点の動作から実行を再開する。
Thereafter, when hardware information such as the program counter, various registers and flags stored in the status register 21 is reset and 081 is executed, the OS1 resumes execution from the operation at the time of switching to the OS2.

この様にして、複数のOSを実行中の任意の時点で中断
し、他のOSを実行彼再び中断されたOSの処理を行う
ことができる。
In this way, it is possible to interrupt the execution of multiple OSs at any time, run another OS, and then resume processing of the interrupted OS.

フリップフロップ群18は入出力装置がDMA(ダイレ
クト・メモリ・アクセス)中にメモリを切替えると、誤
ったメモリ領域にデータが入出力されるのを防ぐ働きを
する。
The flip-flop group 18 functions to prevent data from being input/output to the wrong memory area when the input/output device switches memories during DMA (direct memory access).

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、同一アドレス帯な有する
メモリ領域を切替えることにより複数のOSを任意の時
点で中断し、他のOSに切替え実行した後再び中断した
時点から処理を再開できる効果がある。
As explained above, the present invention has the advantage of being able to suspend multiple OSs at any point in time by switching memory areas in the same address band, switch to another OS, and then resume processing from the point where it was interrupted again. be.

又、入出力がDMA (ダイレクト・メモリ・アクセス
)による実行中に切替えを行うことによる誤動作を防止
できる効果がある。
Moreover, it is possible to prevent malfunctions caused by switching during execution of input/output using DMA (direct memory access).

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す構成図である。 11・・・・・・CPLI、12・・・・・・切替手段
、13.14゜15・・・・・・メモリ領域、16.i
7・・・・・・入出力装置、18・・・・・・フリップ
フロップ群、19,20.21・・・・・・ステータス
レジスタ、30・・・・・・メモリ。 [−
FIG. 1 is a block diagram showing an embodiment of the present invention. 11...CPLI, 12...Switching means, 13.14°15...Memory area, 16. i
7...Input/output device, 18...Flip-flop group, 19, 20.21...Status register, 30...Memory. [-

Claims (1)

【特許請求の範囲】[Claims] 同一アドレス帯を有するメモリおよび複数の入出力装置
を備えたコンピュータシステムにおいて、前記メモリの
同一アドレス帯の複数のメモリ領域を切替える切替手段
と、各メモリ領域に対応する実行中のハードウェア情報
を格納する格納手段と、前記入出力装置が入出力動作実
行中である事を記憶するフリップフロップ群とを有し、
格納された前記ハードウェア情報をセットし、前記複数
のメモリ領域にそれぞれ格納されている複数のOSの一
を実行中に他のOSへの切替要求が発生した場合、現在
実行中の前記ハードウェア情報を前記格納手段に格納し
、この時に前記入出力装置の何れかが動作中であれば前
記フリップフロップ群のそれぞれ対応する各フリップフ
ロップをセットし前記動作が終了した時前記各フリップ
フロップをリセットして、前記切替手段により現在実行
中の前記メモリ領域およびこのメモリ領域に対応する前
記格納手段を前記他のOAが格納されているメモリ領域
およびこのメモリ領域に対応する前記格納手段に切替え
、この切替前の前記格納手段に格納されている前記ハー
ドウェア情報をセットして切替後のOSを実行するよう
にして前記複数のOSをその実行中の任意の時点で中断
し、他のOSを実行後再び中断されたOSの処理を行な
うことを特徴とする複数OS格納切替可能コンピュータ
In a computer system equipped with a memory having the same address band and a plurality of input/output devices, a switching means for switching a plurality of memory areas in the same address band of the memory, and storing information on the hardware being executed corresponding to each memory area. and a group of flip-flops for storing that the input/output device is performing an input/output operation,
When the stored hardware information is set and a request to switch to another OS occurs while one of the plurality of OSs respectively stored in the plurality of memory areas is being executed, the hardware information currently being executed is storing information in the storage means; if any of the input/output devices is in operation at this time, each corresponding flip-flop of the flip-flop group is set; and when the operation is completed, each flip-flop is reset; Then, the switching means switches the memory area currently being executed and the storage means corresponding to this memory area to the memory area in which the other OA is stored and the storage means corresponding to this memory area; The hardware information stored in the storage means before switching is set and the OS after switching is executed, the plurality of OSs are interrupted at any point during execution, and the other OS is executed. A computer capable of storing and switching a plurality of OSs, characterized in that a computer is capable of storing and switching between multiple OSs, and then resumes processing of an OS that has been interrupted.
JP6141086A 1986-03-18 1986-03-18 Computer capable of storing and switching plural os Pending JPS62217326A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6141086A JPS62217326A (en) 1986-03-18 1986-03-18 Computer capable of storing and switching plural os

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6141086A JPS62217326A (en) 1986-03-18 1986-03-18 Computer capable of storing and switching plural os

Publications (1)

Publication Number Publication Date
JPS62217326A true JPS62217326A (en) 1987-09-24

Family

ID=13170323

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6141086A Pending JPS62217326A (en) 1986-03-18 1986-03-18 Computer capable of storing and switching plural os

Country Status (1)

Country Link
JP (1) JPS62217326A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6192421B1 (en) * 1997-05-20 2001-02-20 Alcatel Program-controlled device with reloading possibility for and changeover possibility to a second operating system without program interruption by exchanging two address lines each other

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5769343A (en) * 1980-10-09 1982-04-28 Fujitsu Ltd Paging system of microcomputer
JPS60136833A (en) * 1983-12-26 1985-07-20 Hitachi Ltd Operating system switching method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5769343A (en) * 1980-10-09 1982-04-28 Fujitsu Ltd Paging system of microcomputer
JPS60136833A (en) * 1983-12-26 1985-07-20 Hitachi Ltd Operating system switching method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6192421B1 (en) * 1997-05-20 2001-02-20 Alcatel Program-controlled device with reloading possibility for and changeover possibility to a second operating system without program interruption by exchanging two address lines each other

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