JPS62265743A - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPS62265743A JPS62265743A JP10982086A JP10982086A JPS62265743A JP S62265743 A JPS62265743 A JP S62265743A JP 10982086 A JP10982086 A JP 10982086A JP 10982086 A JP10982086 A JP 10982086A JP S62265743 A JPS62265743 A JP S62265743A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- pattern
- case
- cap
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 claims abstract description 42
- 239000004020 conductor Substances 0.000 claims abstract description 19
- 238000007789 sealing Methods 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 description 9
- 238000005476 soldering Methods 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 238000007598 dipping method Methods 0.000 description 2
- 235000017166 Bambusa arundinacea Nutrition 0.000 description 1
- 235000017491 Bambusa tulda Nutrition 0.000 description 1
- 241001330002 Bambuseae Species 0.000 description 1
- 235000015334 Phyllostachys viridis Nutrition 0.000 description 1
- 239000011425 bamboo Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000013011 mating Effects 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Casings For Electric Apparatus (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は混成集積回路に関し、特に混成集積回路の半田
シール構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid integrated circuit, and more particularly to a solder seal structure for a hybrid integrated circuit.
従来、混成集積回路等の半田シール法としては、第３図
に示すようにケースあるいはキヤ・・ｌプ２１を嵌合す
る際に嵌合部に導体パターン２２を形成し導体パターン
に付着させた半田で嵌合封止する方法が一般的に用いら
れており、半田の封止法としては半田ごて等で半田を溶
融して封止する第１の方法と、前記導体パターンに予価
半田を施し、ケースとキャップを嵌合させ、半田を再溶
融させて封止する第２の方法が一般的に用いられている
。Conventionally, as a solder sealing method for hybrid integrated circuits, etc., when a case or cap 21 is fitted together, a conductive pattern 22 is formed on the mating part and attached to the conductive pattern. A method of fitting and sealing with solder is generally used, and the first method of sealing with solder is to melt the solder with a soldering iron, etc., and the first method is to apply pre-prepared solder to the conductor pattern. A second method is generally used in which the solder is applied, the case and the cap are fitted together, and the solder is remelted for sealing.
〔発明が解決しようとする問題点′］
上述した従来の半田シール方法として、第１の方法は半
田溶融する際半田が内部に飛び敗ってデバイス内部の半
田ショートの原因となったり製造能力不足などの欠点が
あった。[Problems to be Solved by the Invention'] Among the above-mentioned conventional solder sealing methods, the first method is that when the solder melts, the solder flies inside the device, causing a solder short circuit inside the device, or causing insufficient manufacturing capacity. There were drawbacks such as.
また、第２の方法として予備半田後の半田再溶融法は予
備半田３行うキャ・・７７″またはケースの導体パター
ン上に、半田浸しにより半田を形成するがその予備半田
したキャップとケースを嵌合させ、半田を再溶融する方
法は、キャップあるいはケースの機械的ソリが影響し、
第４図に示すように付着する予備半田量が部分的に多少
を生じ、そのため半田不足から気密リークするという欠
点があった。The second method is to re-melt the solder after pre-soldering. Pre-soldering 3 is performed. Solder is formed on the conductor pattern of the cap or case by dipping the pre-soldered cap into the case. The method of remelting the solder is affected by mechanical warping of the cap or case.
As shown in FIG. 4, the amount of preliminary solder that is deposited is small in some areas, which has the disadvantage of airtight leakage due to insufficient solder.
なお、第４図において、３１はキャップ、３２はケース
、３３は半田である。In addition, in FIG. 4, 31 is a cap, 32 is a case, and 33 is solder.
本発明の目的は、半田封止する導体パターン上の半田量
を均一に付着させ、すぐれた気密性と生産性が得られる
混成集積回路を提供することにある。An object of the present invention is to provide a hybrid integrated circuit in which an amount of solder is uniformly deposited on a conductor pattern to be soldered sealed, and excellent airtightness and productivity can be obtained.
本発明の混成集積回路は、ケースあるいはキャップに半
田封止用の導体パターンを有し、該導体パターン上に形
成された半田によりケースを封止する混成集積回路にお
いて、前記ケースあるいはキャップの少なくとも一方の
導体パターンが幅の広い部分と狭い部分により構成され
ていることを特徴としている。A hybrid integrated circuit of the present invention is a hybrid integrated circuit in which a case or a cap has a conductor pattern for solder sealing, and the case is sealed with solder formed on the conductor pattern, at least one of the case or the cap. The conductor pattern is characterized by having a wide part and a narrow part.
なお、この、導体パターンは広い部分と狭い部分を周期
的に形成すればより半田付着量の均一性がはかれる。It should be noted that if the conductor pattern is formed periodically with wide portions and narrow portions, the amount of solder adhesion can be more uniform.
次に本発明の実施例について図面を参照して説明する。 Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の斜視図である。第１図にお
いて、１１はケース又はキャップで、１２はその封止部
に形成された半田封止に用いる導体パターンである。導
体パターン１２は図示されているように幅の広い部分と
狭い部分が周期的に形成されている。なお、この導体パ
ターンはケース又はキャップの一方又は両方に形成する
。FIG. 1 is a perspective view of an embodiment of the present invention. In FIG. 1, 11 is a case or a cap, and 12 is a conductive pattern used for solder sealing formed on the sealing portion. As shown in the figure, the conductor pattern 12 has wide portions and narrow portions formed periodically. Note that this conductive pattern is formed on one or both of the case and the cap.
第２図はキャップ４１．ケース４２の双方に前記した導
体パターンを形成し半田４３を施した乙のの断面図であ
る。図示されているように半田は導体パターンに準じて
凹凸があるが全般的には均一な半田面となる。次に、ケ
ースと半田の半田形成部分を一致させて半田を再溶融さ
せるとリークがない均一な気密封止が完成する。Figure 2 shows the cap 41. It is a cross-sectional view of B in which the conductor pattern described above is formed on both sides of the case 42 and solder 43 is applied. As shown in the figure, the solder has irregularities according to the conductor pattern, but the solder surface is generally uniform. Next, by aligning the solder forming portions of the case and the solder and remelting the solder, a uniform hermetic seal with no leaks is completed.
なお、半田が均一に付着する理由は幅の広い部分と狭い
部分のパターンが周期的に形成されているので半田はパ
ターン幅に比例した厚さに付着する。従って若干のソリ
等の発生があっても一方に片寄ることなく全般的に均一
に形成することができる。均一性をよりよくするにはパ
ターン幅を周期的変化させるのが好ましく、そのパター
ンは第１図のように方形の突起に限定されず、円形の突
起でも、また三角形の突起でら目的を達成することがで
きる。The reason why the solder adheres uniformly is that the pattern of wide and narrow parts is formed periodically, so the solder adheres to a thickness proportional to the pattern width. Therefore, even if a slight warp or the like occurs, it can be formed uniformly overall without being biased to one side. In order to improve uniformity, it is preferable to periodically change the pattern width, and the pattern is not limited to square projections as shown in Figure 1, but circular or triangular projections can also achieve the purpose. can do.
なお、本発明は混成集積回路について説明したが、混成
集積回路に限定されるものでなく、池の電子部品の半田
シールに適用することができる。Although the present invention has been described with respect to a hybrid integrated circuit, it is not limited to hybrid integrated circuits, and can be applied to solder seals for electronic components.
以上説明したように本発明は、キャップあるいはケース
の導体パターンに、突起部をある間隔で形成しであるの
で半田浸し法により形成された半田量が均一になりすぐ
れた気密性と生産性が得られる。As explained above, in the present invention, protrusions are formed at certain intervals on the conductor pattern of the cap or case, so the amount of solder formed by the solder dipping method becomes uniform, and excellent airtightness and productivity can be achieved. It will be done.
第１図は本発明の一実施例の要部の斜視図、第２図は本
発明の一実施例の半田形成部断面図、第３図は従来の混
成集積回路の一例の要部の斜視図、第４図は従来の混成
集積回路の一例の半田形成部の断面図である。
】１・・・キャップあるいはケース、１２・・・導体パ
ターン、２１・・・キャップあるいはケース、２２・・
・導体パターン、３１．４１・・・キャップ、３２゜４
２・・・ケース、３３．４３・・・半田。
に゛・
扁１図
煮Ｚ図
ガ３図
箭４図Fig. 1 is a perspective view of a main part of an embodiment of the present invention, Fig. 2 is a sectional view of a solder forming part of an embodiment of the invention, and Fig. 3 is a perspective view of a main part of an example of a conventional hybrid integrated circuit. 4 are cross-sectional views of a solder forming portion of an example of a conventional hybrid integrated circuit. ]1...Cap or case, 12...Conductor pattern, 21...Cap or case, 22...
・Conductor pattern, 31.41...Cap, 32゜4
2...Case, 33.43...Solder. ni゛・ flat 1 figure boiled Z figure 3 figures bamboo 4 figures
Claims (2)
ーンを有し該導体パターン上に形成された半田によりケ
ースを封止する混成集積回路において、前記ケースある
いはキャップの少なくとも一方の導体パターンが幅の広
い部分と狭い部分により構成されていることを特徴とす
る混成集積回路。(1) In a hybrid integrated circuit in which a case or a cap has a conductor pattern for solder sealing and the case is sealed by solder formed on the conductor pattern, the conductor pattern of at least one of the case or the cap has a width. A hybrid integrated circuit characterized by being composed of a wide part and a narrow part.
る導体パターンである特許請求の範囲第（１）項記載の
混成集積回路。(2) The hybrid integrated circuit according to claim (1), which is a conductor pattern in which wide portions and narrow portions are periodically formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10982086A JPS62265743A (en) | 1986-05-13 | 1986-05-13 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10982086A JPS62265743A (en) | 1986-05-13 | 1986-05-13 | Hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62265743A true JPS62265743A (en) | 1987-11-18 |
Family
ID=14520034
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10982086A Pending JPS62265743A (en) | 1986-05-13 | 1986-05-13 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62265743A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5821455A (en) * | 1993-04-26 | 1998-10-13 | Sumitomo Metal (Smi) Electronics Devices, Inc. | Lid with variable solder layer for sealing semiconductor package, package having the lid and method for producing the lid |
| WO2020004184A1 (en) * | 2018-06-25 | 2020-01-02 | 日本電気硝子株式会社 | Method for manufacturing cover member, cover member, and method for manufacturing electronic component package |
| JP2021064764A (en) * | 2019-10-17 | 2021-04-22 | 日本電気硝子株式会社 | Optical window material, manufacturing method of optical window material, optical member, and manufacturing method of optical member |
-
1986
- 1986-05-13 JP JP10982086A patent/JPS62265743A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5821455A (en) * | 1993-04-26 | 1998-10-13 | Sumitomo Metal (Smi) Electronics Devices, Inc. | Lid with variable solder layer for sealing semiconductor package, package having the lid and method for producing the lid |
| WO2020004184A1 (en) * | 2018-06-25 | 2020-01-02 | 日本電気硝子株式会社 | Method for manufacturing cover member, cover member, and method for manufacturing electronic component package |
| CN112313793A (en) * | 2018-06-25 | 2021-02-02 | 日本电气硝子株式会社 | Method for manufacturing cover member, and method for manufacturing electronic component package |
| JPWO2020004184A1 (en) * | 2018-06-25 | 2021-08-05 | 日本電気硝子株式会社 | Manufacturing method of lid member, manufacturing method of lid member, and electronic component package |
| CN112313793B (en) * | 2018-06-25 | 2024-09-20 | 日本电气硝子株式会社 | Method for manufacturing cover member, and method for manufacturing electronic component package |
| JP2021064764A (en) * | 2019-10-17 | 2021-04-22 | 日本電気硝子株式会社 | Optical window material, manufacturing method of optical window material, optical member, and manufacturing method of optical member |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US3610811A (en) | Printed circuit board with solder resist gas escape ports | |
| JPS62265743A (en) | Hybrid integrated circuit | |
| JPH08162755A (en) | Electric connector | |
| JPS58215062A (en) | Lead frame | |
| JPH06163305A (en) | Chip component | |
| JP3226147B2 (en) | Bonding structure of surface mount components | |
| JP2002374060A (en) | Electronic circuit board | |
| GB2222586A (en) | Joining articles with low melting point glass | |
| JPH01270325A (en) | Mask for potting seal | |
| JPS62160290A (en) | Soldering mask | |
| JPS6020926Y2 (en) | Plate-shaped through-hole ceramic capacitor | |
| JPH03220792A (en) | Mounting structure of pga-type integrated circuit | |
| JPS587655Y2 (en) | Parts mounting hole structure | |
| JPS6035230Y2 (en) | Plate-shaped through-hole ceramic capacitor | |
| JPH03242901A (en) | Chip type resistor and manufacture thereof | |
| JPH073145U (en) | Electronic components for surface mounting | |
| JPH0362599A (en) | Method of mounting integrated circuit package for surface mounting | |
| JPH04199898A (en) | Formation of through-hole | |
| JPH08222823A (en) | Through hole wiring board | |
| JPH0927675A (en) | Diode soldering structure | |
| JPH0732224B2 (en) | Semiconductor device | |
| JPH01202850A (en) | Semiconductor device | |
| JPH06224675A (en) | Production of electronic parts | |
| JPH0147911B2 (en) | ||
| JPH01218092A (en) | Manufacture of printed wiring board |