JPS62254403A - Manufacture of chip device - Google Patents
Manufacture of chip deviceInfo
- Publication number
- JPS62254403A JPS62254403A JP61096876A JP9687686A JPS62254403A JP S62254403 A JPS62254403 A JP S62254403A JP 61096876 A JP61096876 A JP 61096876A JP 9687686 A JP9687686 A JP 9687686A JP S62254403 A JPS62254403 A JP S62254403A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- protrusions
- electrode
- chip
- protrusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Apparatuses And Processes For Manufacturing Resistors (AREA)
- Non-Adjustable Resistors (AREA)
- Thermistors And Varistors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は発熱型チップ状素子例えば正特性サーミスタ(
PTC) 、負特性サーミスタ(NTC)、CTR、バ
リスタ等の製造方法に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to heat-generating chip-like elements such as positive temperature coefficient thermistors (
The present invention relates to methods of manufacturing PTC), negative characteristic thermistors (NTC), CTRs, varistors, and the like.
回路素子の小型化により各種素子はチップ化の方向にあ
り、例えば回路保護に使われる電流制限用PTCについ
て述べると、従来平板状PTCをそのままプリント基板
等へ取付けるときはPTCの電極の厚みが数μmしかな
いため、密着固定時にバラツキがあったり、しかも熱絶
縁間隔が小さいため熱放散特性が大巾に動き回路保護が
不安定で保護電流の設定が困難であった。Due to the miniaturization of circuit elements, various elements are becoming chips. For example, when talking about current limiting PTC used for circuit protection, when conventional flat PTC is attached to a printed circuit board etc., the thickness of the PTC electrode is Since the thickness is only μm, there are variations when they are tightly fixed, and furthermore, because the thermal insulation interval is small, the heat dissipation characteristics vary widely, making circuit protection unstable and making it difficult to set the protection current.
本発明はあらかじめ設定された熱絶縁間隔をプリント基
板等取付面との間に設けることにより回路保護電流を正
確に設定できると共にチップ素子の基板上へのマウント
作業を容易にするような形状の素子を量産できる製造方
法に関するものである。The present invention provides an element having a shape that allows accurate setting of circuit protection current by providing a preset thermal insulation interval between the mounting surface of a printed circuit board, etc., and facilitates mounting work of the chip element on the board. This relates to a manufacturing method that allows for mass production.
本発明の第1の方法は、第1図に示すような形状、すな
わち、平板状体1の表裏左右端部に対称的に突部2,2
を形成し、表側の一方端部および裏側の他方端部の突部
2,2の一部に左右外側に向う切欠部3.3を設けてな
り、これを素子素体で一部プレス成形し、これを焼成磁
器化し、この素子外表面全体に薄膜電極を形成し、素子
の上下面および突部と直交する面を研削して咳面の電極
薄膜を除去してチップ状素子を製造するものである。The first method of the present invention is to create a shape as shown in FIG.
A notch 3.3 is provided in a part of the protrusions 2, 2 at one end of the front side and the other end of the back side, and this is partially press-molded with the element body. This is made into fired porcelain, a thin film electrode is formed on the entire outer surface of the element, and the upper and lower surfaces of the element and surfaces orthogonal to the protrusions are ground to remove the electrode thin film on the surface to produce a chip-shaped element. It is.
本発明の第2の方法は、第3図に示すような形状、すな
わち、平板状体1の表裏左右端部に対称的に突部2.2
を形成し、表側の一方端部および裏側の他方端部の突部
2に等間隔に左右外側に向う切欠部3,3を設けてなり
、これを素子素体で一部プレス成形し、これを焼成磁器
化し、この素子外表面全体に薄膜電極を形成し、素子の
上下面を研削して咳面の電極薄膜を除去し、表裏各突部
に設けられた切欠部が中心位置を占めるように平行にカ
ッティングすることにより多量の同一形状のチップ素子
を製造することができる。The second method of the present invention has a shape as shown in FIG.
The projecting portion 2 at one end of the front side and the other end of the back side is provided with notches 3, 3 facing left and right outward at equal intervals, and a portion of this is press-molded with the element body. A thin film electrode was formed on the entire outer surface of the element, and the upper and lower surfaces of the element were ground to remove the electrode thin film on the coughing surface, so that the notches provided on the front and back protrusions occupied the center position. A large number of chip elements having the same shape can be manufactured by cutting parallel to the .
チップ状素子を第1図に示すような形状のものを素子素
体で一部プレス成形によって成形し、これを焼成し、全
体表面に薄膜電極を形成し、素子の上下面および突部と
直交する面を研削して電極薄膜を除去すると共に上下面
および突部と直交する面の平行度をだすことができ形状
の統一されたものが製作されるのでマウント作業も容易
となる。A chip-like element having the shape shown in Fig. 1 is formed by press molding a part of the element body, and is fired, and a thin film electrode is formed on the entire surface, and the electrode is perpendicular to the upper and lower surfaces of the element and the protrusions. The electrode thin film is removed by grinding the surface to be removed, and the upper and lower surfaces and the surface orthogonal to the protrusion can be made parallel, and a product with a uniform shape can be manufactured, making mounting work easier.
また本発明の第2の方法ではカッティング操作だけで同
一形状のチップ素子が多量に生産され材料の無駄も少な
いものである。Furthermore, in the second method of the present invention, chip elements of the same shape can be produced in large quantities by just a cutting operation, and there is little waste of material.
本発明の第1の方法は、第1図に示すような形状、すな
わち、平板状体lの表裏左右端部に対称的に突部2,2
を形成し、表側の一方端部の突部2および裏側の他方端
部の突部2の一部に左右外側に向う切欠部3,3を設け
てなり、これを素子素体で一部プレス成形し、これを焼
成磁器化し、この素子に対してNi無電解、Ni無電解
+電気メッキ、Ni無電解十Ag焼付メッキ、スパッタ
リング、溶射などの手段で素子外表面全体に薄膜電極を
形成し、素子の上下面および突部と直交する面を平面研
削盤または平面ランプ盤で研削して不要な電極薄膜を除
去すると共に上下、および突部と直交する面の平行平面
度を出して製作される。The first method of the present invention is to create a shape as shown in FIG.
The protrusion 2 at one end of the front side and the protrusion 2 at the other end of the back side are provided with notches 3, 3 facing left and right outward, and are partially pressed with the element body. This is molded and fired into porcelain, and a thin film electrode is formed on the entire outer surface of the element by means such as Ni electroless plating, Ni electroless + electroplating, Ni electroless + Ag baking plating, sputtering, thermal spraying, etc. , the upper and lower surfaces of the element and the surfaces perpendicular to the protrusions are ground using a surface grinder or a flat ramp machine to remove unnecessary electrode thin films, and the upper and lower surfaces and surfaces perpendicular to the protrusions are made parallel and flat. Ru.
本発明の第2の方法は、第3図に示すような形状、すな
わち、平板状体1の表裏左右端部に対称的に突部2.2
を形成し、表側の一方端部の突部2および裏側の他方端
部の突部2に等間隔に左右外側に向う切欠部3,3を設
けてなり、これを素子素体で一部プレス成形し、これを
焼成しく磁器化し、この素子に対してNi無電解、Ni
無電解十電気メッキ、旧態電解+へg焼付メッキ、スパ
ッタリング、溶射などの手段で素子外表面全体に薄膜電
極を形成し、素子の上下面を平面研削盤または平面ラッ
プ盤で研削して不要な電極薄膜を除去すると共に上下面
の平行平面度を出し、表裏各突部2に設けられた切欠部
3が中心位置を占めるように平行にカッティングする。The second method of the present invention has a shape as shown in FIG.
The protrusion 2 on one end of the front side and the protrusion 2 on the other end of the back side are provided with notches 3, 3 facing left and right outward at equal intervals, and are partially pressed with the element body. This is molded and fired to make porcelain, and this element is coated with Ni electroless, Ni
A thin film electrode is formed on the entire outer surface of the element by means such as electroless electroplating, old-style electrolytic + baking plating, sputtering, and thermal spraying, and the upper and lower surfaces of the element are ground with a surface grinder or surface lapping machine to remove unnecessary materials. While removing the electrode thin film, the upper and lower surfaces are made parallel and flat, and cut in parallel so that the notches 3 provided on each of the front and back protrusions 2 occupy the center position.
かくして多数の同一形状のチップ素子が製作されるもの
である。なおこの場合、平面研削とカッティング操作を
前後逆に操作してもよい。In this way, a large number of chip elements having the same shape are manufactured. In this case, the surface grinding and cutting operations may be performed in the reverse order.
また、表側突部および裏側突部に等間隔に設けられる切
欠部の間隔のピッチの位相を適当にずらすと第2図に示
すように切欠部が突部2の端部に設けたものが多数製作
されることとなる。In addition, if the pitch of the notches provided at equal intervals on the front side protrusion and the back side protrusion is shifted appropriately, many of the notches are provided at the end of the protrusion 2 as shown in Fig. 2. It will be manufactured.
以上述べたように、発熱型素子において、公絶縁間隔と
電気的絶縁度を最適設定したチップ素子を安価に多量生
産することができるものである。As described above, it is possible to inexpensively mass-produce chip elements in which the public insulation interval and the degree of electrical insulation are optimally set in heat-generating elements.
またチップ素子のプリント基板等への取付作業が容易な
ように、素子の上下面はどちらでもよいように、さらに
ff1llftバランスがよくとれたものを製作できる
ものである。Furthermore, in order to facilitate the work of attaching the chip element to a printed circuit board or the like, it is possible to manufacture a device with a well-balanced ff1llft so that the element can be mounted on either the upper or lower surface.
第1図〜第3図は本発明の実施例を示し、第1図は本発
明第1方法で製作されたチップ状素子の斜面図、第2図
は第1図の変形例を示す平面図、第3図は本発明第2方
法の説明概略図である。
1・・・平板状体、2・・・突部、3・・・切欠部。1 to 3 show embodiments of the present invention, FIG. 1 is a perspective view of a chip-like element manufactured by the first method of the present invention, and FIG. 2 is a plan view showing a modification of FIG. 1. , FIG. 3 is a schematic diagram illustrating the second method of the present invention. 1... Flat plate-shaped body, 2... Projection, 3... Notch.
Claims (2)
、表側の一方端部および裏側の他方端部の突部の一部に
左右外側に向う切欠部を設けてなり、これを素子素体で
一体プレス成形し、これを焼成磁器化し、この素子外表
面全体に薄膜電極を形成し、素子の上下面および突部と
直交する面を研削して該面の電極薄膜を除去することを
特徴とするチップ状素子の製造方法。(1) Protrusions are formed symmetrically on the front and back left and right ends of the flat plate-like body, and a notch facing left and right outward is provided in a part of the protrusion at one end on the front side and the other end on the back side, This is integrally press-molded with the element body, which is made into fired porcelain.A thin film electrode is formed on the entire outer surface of the element, and the upper and lower surfaces of the element and the surface orthogonal to the protrusion are ground to remove the electrode thin film on the surface. A method for manufacturing a chip-like element, characterized by removing the element.
、表側の一方端部および裏側の他方端部の突部に等間隔
に左右外側に向う切欠部を設けてなり、これを素子素体
で一体プレス成形し、これを焼成磁器化し、この素子外
表面全体に薄膜電極を形成し、素子の上下面を研削して
該面の電極薄膜を除去し、表裏各突部に設けられた切欠
部が中心位置を占めるように平行にカッティングするこ
とを特徴とするチップ状素子の製造方法。(2) Protrusions are formed symmetrically on the left and right ends of the front and back of the flat plate-like body, and cutouts facing outward to the left and right are provided at equal intervals in the protrusions at one end on the front side and the other end on the back side, This is integrally press-molded with the element body, which is then fired into porcelain.A thin film electrode is formed on the entire outer surface of the element, and the upper and lower surfaces of the element are ground to remove the electrode thin film on these surfaces. A method for producing a chip-like element, characterized in that cutting is carried out in parallel so that the notch provided in the part occupies the center position.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61096876A JPS62254403A (en) | 1986-04-28 | 1986-04-28 | Manufacture of chip device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61096876A JPS62254403A (en) | 1986-04-28 | 1986-04-28 | Manufacture of chip device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62254403A true JPS62254403A (en) | 1987-11-06 |
Family
ID=14176619
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61096876A Pending JPS62254403A (en) | 1986-04-28 | 1986-04-28 | Manufacture of chip device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62254403A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009515367A (en) * | 2005-11-09 | 2009-04-09 | 謝 清雄 | Manufacturing method of surface mount type precision resistor |
-
1986
- 1986-04-28 JP JP61096876A patent/JPS62254403A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009515367A (en) * | 2005-11-09 | 2009-04-09 | 謝 清雄 | Manufacturing method of surface mount type precision resistor |
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