JPS62254402A - Chip device - Google Patents
Chip deviceInfo
- Publication number
- JPS62254402A JPS62254402A JP61096875A JP9687586A JPS62254402A JP S62254402 A JPS62254402 A JP S62254402A JP 61096875 A JP61096875 A JP 61096875A JP 9687586 A JP9687586 A JP 9687586A JP S62254402 A JPS62254402 A JP S62254402A
- Authority
- JP
- Japan
- Prior art keywords
- protrusion
- chip
- protrusions
- flat plate
- front side
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009413 insulation Methods 0.000 claims description 7
- 238000010292 electrical insulation Methods 0.000 claims description 3
- 238000000465 moulding Methods 0.000 description 3
- 239000010409 thin film Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009125 cardiac resynchronization therapy Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000007751 thermal spraying Methods 0.000 description 1
Landscapes
- Details Of Resistors (AREA)
- Non-Adjustable Resistors (AREA)
- Thermistors And Varistors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は発熱型チップ状素子例えば正特性サーミスタ（
ＰＴＣ） 、負特性サーミスタ（ＮＴＣ）、ＣＲＴ、バ
リスタ等を対象とし、その千ノブ形状に関するものであ
る。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to heat-generating chip-like elements such as positive temperature coefficient thermistors (
This article deals with the 1000-knob shape of PTC), negative characteristic thermistors (NTC), CRTs, varistors, etc.
回路素子の小型化により各種素子はチップ化の方向にあ
り、例えば回路保護に使われる電流制限用ＰＴＣについ
て述べると従来平板状ＰＴＣをそのままプリント基板等
へ取付けるときはＰＴＣの電極の厚みが数μｍしかない
ため、密着固定時にバラツキがあったり、しかも熱絶縁
間隔が小さいため熱放散特性が大巾に動き回路保護が不
安定で保護電流の設定が困難であった。Due to the miniaturization of circuit elements, various elements are becoming chips. For example, when talking about current limiting PTC used for circuit protection, when conventionally flat PTC is attached to a printed circuit board etc., the thickness of the PTC electrode is several μm. Because of this, there were variations when they were closely fixed, and furthermore, because the thermal insulation spacing was small, the heat dissipation characteristics fluctuated widely, making circuit protection unstable and making it difficult to set the protective current.
〔発明が解決しようとする問題点３
本発明はあらかじめ設定された熱絶縁間隔をプリント基
板等取付面との間に設けることにより回路保護電流を正
確に設定できると共にチップ素子の基板上へのマウント
作業を容易にした形状を堤供しようとするものである。[Problem to be Solved by the Invention 3] The present invention provides a predetermined thermal insulation interval between the mounting surface of the printed circuit board, etc., thereby making it possible to accurately set the circuit protection current, and to mount the chip element on the board. The aim is to provide a shape that makes work easier.
第１図に示すように、平板状体ｌの表裏左右端部に対称
的に突部２．２を形成し、表側の一方端部の突部２およ
び裏側の他方端部の突部２の一部に左右外側に向う切欠
部３．３を設けてなり、これを一体成形で構成したもの
である。As shown in FIG. 1, protrusions 2.2 are formed symmetrically on the left and right ends of the front and back of the flat plate-like body l, and the protrusions 2.2 are formed at one end on the front side and the protrusions 2 at the other end on the back side. A notch portion 3.3 facing left and right outside is provided in a part, and this is constructed by integral molding.
チップ状素子を第１図に示すような形状としたから、こ
れをプリント基板等に取付けたとき、平板状体１と基板
面との間に熱絶縁空間が形成され、発熱型素子の場合安
定した作動が期待され、また素子形状が縦横中心軸線の
中心点Ｐを基準とした点対称になっているので素子を基
板上にマウントする場合、表裏どちら側でも固着面とす
ることができ、しかも重量的にもバランスしているから
、マウント作業が容易である。Since the chip-like element is shaped as shown in Fig. 1, when it is attached to a printed circuit board, etc., a thermally insulating space is formed between the flat plate-like body 1 and the board surface, and in the case of a heat-generating element, it is stable. In addition, since the element shape is point symmetrical with respect to the center point P of the vertical and horizontal central axes, when mounting the element on a substrate, either the front or back side can be used as the fixing surface. The weight is well balanced, so mounting is easy.
第１図〜第１図は本発明の一実施例を示すもので、第１
図の本発明チップ状素子の斜面図において、平板状体ｌ
の表裏左右端部に対称的に突部２．２を形成し、表側の
一方端部の突部２および裏側の他方端部の突部２の一部
に左右外側に向う切欠部３．３を設けてなり、これを一
体的にプレス成形により構成する。突部２はプリント基
板等の取付面と、素子の平板状体１との間の空気絶縁間
隔を形成するものであるから、その高さは素子の熱絶縁
度の大小によって決定され、またその巾は素子の電気的
絶縁度の大小によって決定されるものである。1 to 1 show one embodiment of the present invention.
In the oblique view of the chip-like element of the present invention shown in the figure, the flat plate l
protrusions 2.2 are formed symmetrically on the left and right ends of the front and back, and notches 3.3 facing left and right outward are formed in part of the protrusion 2 at one end of the front side and the protrusion 2 at the other end of the back side. are provided, which are integrally formed by press molding. Since the protrusion 2 forms an air insulation gap between the mounting surface of the printed circuit board or the like and the flat plate-like body 1 of the element, its height is determined by the degree of thermal insulation of the element, and its height is determined by the degree of thermal insulation of the element. The width is determined by the degree of electrical insulation of the element.
なお、突部２、切欠部３はチップ状素子体の縦横中心軸
線の中心点Ｐに対して点対称に形成されている。第５図
は本発明のチップ状素子をプリント基板４に取付けた状
態を示し、半田付５によっ各電極が連結されると共にチ
ップ状素子も固着される。第６図は、切欠部３を突部２
の端部に設けた本発明の変形例を示す、第７図は平板状
体ｌの外縁外周を突部で囲繞した本発明の変形例を示す
。Note that the protrusion 2 and the notch 3 are formed point-symmetrically with respect to the center point P of the vertical and horizontal central axes of the chip-like element body. FIG. 5 shows a state in which the chip-like element of the present invention is attached to a printed circuit board 4, and each electrode is connected by soldering 5, and the chip-like element is also fixed. Figure 6 shows the notch 3 and the protrusion 2.
FIG. 7 shows a modification of the invention in which the outer periphery of the flat plate-like body l is surrounded by protrusions.
そして、これらチップ状素子は、各種配合物からなる素
子素体を一部プレス成形で形成し、これを焼成磁化して
構成される。さらに、電極形成のために、Ｎｉ無電解、
Ｎｉ無電解十電気メッキ、Ｎｉ無電解＋Ａｇ焼付メッキ
、スパッタリング、溶射などの手段で素子外表面全体に
薄膜電極が形成される。その後素子の上下面および縦長
方向左右側面を平面研削盤、平面ランプ盤で研削して不
要な電８ｉ薄膜を除去すると共に上下、左右面の平行平
面度がだされている。These chip-like elements are constructed by forming a part of an element body made of various compounds by press molding, and firing and magnetizing the element body. Furthermore, for electrode formation, Ni electroless,
A thin film electrode is formed on the entire outer surface of the element by means such as Ni electroless electroplating, Ni electroless + Ag baking plating, sputtering, and thermal spraying. Thereafter, the upper and lower surfaces of the element, as well as the left and right side surfaces in the vertical direction, are ground using a surface grinder and a flat lamp disk to remove unnecessary electric 8i thin films and to obtain parallel flatness on the upper, lower, left and right surfaces.
〔発明の効果〕 。〔Effect of the invention〕 .
以上述べたように、発熱型素子において突部の高さは熱
絶縁間隔として、また突部の巾は電気的絶縁度として回
路設計上最適に決定され、切欠部は上下面電極と、左右
端部壁の取出電極との連結部を構成するものである。ま
た素子全体が点対称形状となっているので、重量バラン
スがよく、マウント作業が容易となるという効果がある
。As mentioned above, in a heat-generating element, the height of the protrusion is optimally determined based on the thermal insulation spacing, the width of the protrusion is optimally determined based on the degree of electrical insulation, and the notch is formed between the upper and lower electrodes and the left and right ends. This constitutes a connection part between the part wall and the extraction electrode. Furthermore, since the entire element has a point-symmetric shape, it has the advantage of good weight balance and easy mounting work.
第１図〜第７図は本発明の一実施例を示し、第１図は斜
面図、第２図は表側平面図、第３図は第２図Ａ−Ａ縦断
面図、第１図は裏側平面図、第５図は取付状態説明図、
第６図は他の実施例の表側平面図、第７図はさらに他の
実施例の表側平面図である。1 to 7 show one embodiment of the present invention, FIG. 1 is a perspective view, FIG. 2 is a front side plan view, FIG. 3 is a vertical sectional view taken along the line A-A in FIG. Back side plan view, Figure 5 is an explanatory diagram of the installation state,
FIG. 6 is a front side plan view of another embodiment, and FIG. 7 is a front side plan view of still another embodiment.
Claims (1)
表側の一方端部の突部および裏側の他方端部の突部の一
部に左右外側に向う切欠部を設けてなり、これを一体成
形で構成したことを特徴とするチップ状素子。 ２、前記突部の高さを素子の取付面との間の空気絶縁間
隔としたことを特徴とする特許請求の範囲第１項記載の
チップ状素子。 ３、前記突部の巾を素子の電気的絶縁間隔としたことを
特徴とする特許請求の範囲第１項または第２項記載のチ
ップ状素子。[Claims] 1. Protrusions are formed symmetrically on the left and right ends of the front and back of the flat plate-shaped body,
What is claimed is: 1. A chip-like element characterized in that a protrusion on one end of the front side and a part of the protrusion on the other end of the back side are provided with notches facing left and right outward, and these are integrally molded. 2. The chip-like element according to claim 1, wherein the height of the protrusion is set to an air insulation distance between the protrusion and the mounting surface of the element. 3. The chip-like element according to claim 1 or 2, wherein the width of the protrusion is set to the electrical insulation interval of the element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61096875A JPS62254402A (en) | 1986-04-28 | 1986-04-28 | Chip device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61096875A JPS62254402A (en) | 1986-04-28 | 1986-04-28 | Chip device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62254402A true JPS62254402A (en) | 1987-11-06 |
Family
ID=14176594
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61096875A Pending JPS62254402A (en) | 1986-04-28 | 1986-04-28 | Chip device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62254402A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5877672A (en) * | 1996-08-08 | 1999-03-02 | Asmo Co., Ltd | Resistor and resistor manufacturing method |
-
1986
- 1986-04-28 JP JP61096875A patent/JPS62254402A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5877672A (en) * | 1996-08-08 | 1999-03-02 | Asmo Co., Ltd | Resistor and resistor manufacturing method |
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