JPS6225343A - Digital signal recording device - Google Patents

Abstract

PURPOSE:To read control codes out of a memory according to an input signal as an address and to control a recording part by writing a recording start control code and a stop control code in memory cells which have the input signal values of recording start conditions and stop condition as addresses. CONSTITUTION:For example, recording is started when the input signal from a digital signal input line 103 is (00000110) in binary notation and stopped when (00100000), (00100001), or (11001111). In this case, the start control code (10) and stop control code (11) are written in cells which has said numerals as addresses in the memory of a control memory part 4 and other numerals are written in other address. The signal inputted from the digital signal input line 103 is supplied to the control memory part 4 as well as a data recording part 5 and a control code is read out of the memory by using the value as an address to control the data recording part 5 through a recording operation signal line 102.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to logic tracers for recording digital signal values.

[Conventional technology]

Conventionally, this type of logic tracer starts or stops tracing when the value of the signal to be traced matches a preset value, and therefore requires a register to store the set value and a comparison circuit. The trace is started or stopped by comparing the register (+(j) and the trace target signal (fi) in a comparison circuit and detecting a match.

[Problem that the invention seeks to solve]

-F In the conventional logic tracer mentioned above, in order to be able to set multiple values, it is necessary to have multiple sets of registers and comparison circuits for storing the set values.
Therefore, there is a drawback that increasing the number of set values makes the device expensive.

[Means for solving problems]

The present invention converts recording start conditions and stop conditions of digital signal values into memory addresses using digital signals as address inputs and control codes representing the start and stop of the recording operation, and writes the data into the memory.

After the writing of the control code is completed, recording is performed by reading the memory contents at the address represented by the value of the digital signal to be recorded, and decoding it to generate a signal to control the start and stop of the recording operation. This allows multiple conditions to be set without increasing the number of registers and comparators that hold start and stop conditions.

That is, the digital signal recording device of the present invention is as follows.

A data recording unit that records the values of multiple digital signals input from the outside and starts and stops recording according to recording operation control signals is connected to a bus signal line for transmitting and receiving address information and data. a control unit including a microprocessor, and having means for converting the recording start condition and stop F condition into an address value and a control code each time they are set, and outputting them to a bus signal line; an operation panel connected to the bus signal line and comprising a plurality of switches for setting recording start conditions and stop conditions of the i-record data recording unit in the control unit; and an operation panel connected to the bus signal line and connected to the microprocessor. a program memory section storing a control program executed by the controller; and a memory having the same number of address bits as the number of bits of the digital signal, connected to the bus signal, and receiving address information and control codes from the control section. A control code is written to the address indicated by the address information in the memory in accordance with a control code writing request from the control unit, and after the writing is completed, the control code stored at the address indicated by the value of the digital signal is written. It has a control memory section that reads out the code, decodes it, and outputs it as the recording operation control signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the digital signal recording device of the present invention.

The control unit 1 includes a microprocessor and controls the entire apparatus. The program memory section 2 is a memory in which a control program executed by the microprocessor in the control section 1 is stored. The operation panel 3 includes a plurality of switches for setting start conditions and stop conditions for recording digital signal values. The data recording section 5 records the value of the digital signal input through the digital signal input line 103, and starts and stops the recording operation according to the signal on the recording operation control signal line 102. The control memory section 4 generates signals instructing the data recording section 5 to start and stop the recording operation, and sends them to the recording operation control signal line 102. Program memory section 2.
The operation panel 3 and the control memory section 4 are connected to the bus signal line 101
It is connected to the control unit l by. Bus signal line 101
transfers address information output by the microprocessor in the control unit 1 to the program memory unit 2, operation panel 3, and control memory unit 4, and transfers address information output from the microprocessor in the control unit 1 to the program memory unit 2, operation panel 3, control memory unit 4, and control unit This is a signal line used to transfer data between the internal microprocessor and the internal microprocessor.

FIG. 2 is a block diagram showing a detailed configuration of the control memory section 4 of FIG. 1. In FIG. 2, for ease of explanation, the signal line 103 of the digital signal input line 103 in FIG.
Assume that the tree, ie, the digital signal input, is 8 bits.

The memory 13 is a memo 1) that can store 7T1 words when the number of signals on the digital signal input line 103 is set to 0, and based on the above assumption, it has a storage capacity of 258 words and can be written using the write control signal line 109. When a signal is input, the input data is written to the input data line 107 using the address line 105, and when a read signal is input manually using the read control signal line 110, it is input using the address line 105. The data stored at the specified address is output to output data *108. The multiplexer 12 selects one of the digital signal value input through the digital signal input line +03 and the address value input through the address line 104 to the address selection signal line 1.
06 is selected according to the address selection signal inputted by 06, and outputted to the address line 105 as address information of the memory 13. The decoder 14 decodes the output data sent from the memory 13 via the output data line 108 and outputs a recording operation control signal to the recording operation control line 102. The control code receiving circuit 11 is controlled by the microprocessor in the control unit 1 shown in FIG. When receiving the address information and control code sent through 01, the received address information is sent to the address line 104, and the multiplexer 2 is configured to select the address information on the address line 104, L:. The memory 13 is
writes the control code, and when the write operation of the memory 13 is completed, an address selection signal is sent to the address selection signal line 10B so as to cause the multiplexer 12 to select the digital signal value on the digital signal input &1103. The control code received by the control code receiving circuit 11 is a 2-bit code as shown in Table 1, and therefore each word in the memory 13 is a 2-bit code. )2 specifies the start of the recording operation, the control code (11)2 specifies the stop of the recording operation, and the control codes (00)? and (01)2 are meaningless codes.

Table 1 Next, the control performed by the microprocessor in the control unit 1 will be explained. Microphone a;/a in control unit 1
The processor controls the entire digital signal recording apparatus shown in FIG. 1 by reading and executing the control program stored in the zrogram memory unit 2 via the bus signal line +01 I7. In order to prepare for recording operation, the recording start conditions and stop conditions specified by the microblower 5 in the control unit 1 and the switches provided on the operation panel 3 are set to 7.
Read through Beth Shin's line lot. Here, it is assumed that the recording start condition is (00000110) 2 7t, that is, the time when the value of the signal input through the digital signal input line 103 becomes (00000110) 2 is the recording start point. It is. Similarly, the recording stop conditions are (00100000)2, (0010000
Assume that three commands, 1) 2 O and (11001111) 2, are specified. In other words, recording is stopped when any one of the three conditions is met. The microprocessor in the control unit 1 converts these read conditions into address information and a control code as described below, and sends them to the control memory unit 4 via the bus signal line lot.

Address Inomi Uni” (00100001)2 (+1)2(1
1001111)7. (11) 2 (Other than the above) (00) 2 The control memory unit 4 that has received the address information and the control code writes the control code into the memory 13. After that, connect the digital signal input line +03
The control code of the memory 13 addressed by the input signal f1/7 is read out, and the control code is decoded by the decoder 14. When the signal value input through the digital signal input line 103 becomes (00000110)2. , (10)2 are read out, so the decoder 14 sends a signal to the recording operation control signal line 102 instructing the start of the recording operation. The data recording section 5 starts recording in response to this recording operation start signal. Similarly, the signal value input through the digital signal input line 103 is (0
0100000)2, (00100001)2 and (1100Hllh), (11)
Since the control code z is read out, the decoder 14 generates a signal instructing to stop the recording operation, and the data recording section 5
stops recording.

〔Effect of the invention〕

As explained above, the present invention converts the start and stop conditions for recording digital signal values into a digital signal, a memory address for inputting the address, and a control code representing the start and stop of the recording operation, and writes them into the memory and controls the data. After the writing of the code is completed, the memory contents at the address represented by the value of the digital signal to be recorded are read out and further decoded to generate signals that control the start and stop of the recording operation, thereby starting recording. This has the advantage that a plurality of conditions can be set without increasing the number of registers and comparators that hold conditions and stop conditions.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the digital signal recording device of the present invention, and FIG. 2 is a detailed configuration diagram of the control memory unit 4 shown in FIG. ■...Control unit, 2...Program memory unit, 3...Operation panel, 4...Control memory unit,
5... Data recording unit, 11... Control code receiving circuit, 12... Multiplexer, 13... Memory, 14... Decoder, 101... Bus signal line, +02... Recording operation control Signal line. 103...Digital signal input line, 104.105...Address line, 106...Address selection signal line, 107...Input data line, 108...Output data line, 109...Write control Signal line, 110...read control signal line. Patent applicant: NEC Corporation Otsu, 2nd agent Patent attorney: Susumu Uchihara 5. °.ゝ, +2 Figure 1

Claims (1)

[Claims] A data recording unit that records the values of a plurality of externally input digital signals and starts and stops recording according to a recording operation control signal, and a bus for transmitting and receiving address information and data. a control unit including a microprocessor connected to the signal line, and having means for converting the recording start and stop conditions into address information and a control code and outputting them to the bus signal line each time the recording start and stop conditions are set; an operation panel connected to the bus signal line, comprising a plurality of switches for setting recording start conditions and stop conditions of the data recording unit in the control unit; and an operation panel connected to the bus signal line and executed by the microprocessor. a program memory section storing a control program to be executed; and a memory having the same number of address bits as the number of bits of the digital signal; A code is written to the address indicated by the address information in the memory, and after the writing is completed, the control code stored at the address indicated by the value of the digital signal is read out, decoded, and output as the recording operation control signal. A digital signal recording device having a control memory section.