JPS62252155A - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPS62252155A JPS62252155A JP9447286A JP9447286A JPS62252155A JP S62252155 A JPS62252155 A JP S62252155A JP 9447286 A JP9447286 A JP 9447286A JP 9447286 A JP9447286 A JP 9447286A JP S62252155 A JPS62252155 A JP S62252155A
- Authority
- JP
- Japan
- Prior art keywords
- cap
- integrated circuit
- hybrid integrated
- semiconductor chip
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 26
- 229920002050 silicone resin Polymers 0.000 claims abstract description 13
- 229920001296 polysiloxane Polymers 0.000 claims description 12
- 239000000758 substrate Substances 0.000 abstract description 8
- 229920005989 resin Polymers 0.000 abstract description 5
- 239000011347 resin Substances 0.000 abstract description 5
- 239000000853 adhesive Substances 0.000 abstract description 4
- 230000001070 adhesive effect Effects 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052710 silicon Inorganic materials 0.000 abstract 2
- 239000010703 silicon Substances 0.000 abstract 2
- 239000011148 porous material Substances 0.000 abstract 1
- 238000007789 sealing Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 238000002844 melting Methods 0.000 description 4
- 230000008018 melting Effects 0.000 description 4
- 229910052718 tin Inorganic materials 0.000 description 4
- 230000003872 anastomosis Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910001252 Pd alloy Inorganic materials 0.000 description 1
- 241001474791 Proboscis Species 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 239000011133 lead Substances 0.000 description 1
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
Landscapes
- Chemical & Material Sciences (AREA)
- Dispersion Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は混成集積回路に係９、とくに半導体チップの実
装な好適な混成集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid integrated circuit, and particularly to a hybrid integrated circuit suitable for mounting semiconductor chips.
従来、混成集積回路に半導体チップを実装する方法とし
ては、たとえば特公昭６０−４７７４６号に記載されて
いる如く、基板上に形成された銀−パラジウム合金よシ
なる接合用厚膜導体に純錫はんだを用いて金めつき、ま
たは錫、銀、銅、鉛などのはんだ用の錫と相互拡散しや
すい金属ある°いは錫の融点を下げる金属のめっきを施
したコバールキャップをはんだ接合したのち、ＩＣチッ
プを気密封止を行なう方法が提案されている。Conventionally, as a method for mounting a semiconductor chip on a hybrid integrated circuit, as described in Japanese Patent Publication No. 60-47746, a thick film conductor for bonding made of a silver-palladium alloy formed on a substrate is coated with pure tin. After soldering a Kovar cap with gold plating or plating with a metal such as tin, silver, copper, or lead that easily interdiffuses with tin for soldering, or a metal that lowers the melting point of tin. , a method of hermetically sealing an IC chip has been proposed.
またたとえば実開昭５ｑ−１ａ６ｑｓａ号に記載される
如く、混成集積回路基板上に設けたパワー半導体素子お
よび他の回路素子を封止蓋を用いて封止する吻合に前記
封止蓋上面に隣接した設けた２個の穴と、前記封止蓋と
、前記基板間の空間内に前記−万の穴を弁して注入した
シリコンレジン層と前記２イ囮の穴をふさぐ遮蔽板とを
設けたものが提案されている。Furthermore, as described in Utility Model Application Publication No. 5Q-1A6QSA, for example, in an anastomosis in which a power semiconductor element and other circuit elements provided on a hybrid integrated circuit board are sealed using a sealing lid, an anastomosis is provided adjacent to the upper surface of the sealing lid. the two holes provided, the sealing lid, a silicone resin layer injected into the space between the substrates to close the two decoy holes, and a shielding plate that closes the two decoy holes. Something has been proposed.
゛前記従来技術のうち、前者の気密封止の方法は技術的
に困難なことが多い。例えば、低融点ガラスを対土用接
着材料とした吻合、低融点ガラスの融点は、４５０〜５
００℃程度であシ、この温度に耐えられる部品でないと
同時に、混成集積回路上に実装できないという問題があ
る。また、封止用材料として金−錫はんだを使用した場
合は、封止部の面積が大きくなると、封止不良の割シ合
いが大きくなるという問題がある。従って、多糧の部品
、例えば半導体チップ、コンデンサ、抵抗体等が混載さ
れる混成集積回路においては、気密封止の方法は、技術
的に困難なことが多く、混成集積回路が鳥栖になるとい
う問題があった◇−万、従来技術のうち１．後者のシリ
コーンレジンで半導体チップをコートする方法は、レジ
ンの硬化温度を１５０℃程度に抑えられるので、他の熱
に対し弱いｉ載部品との混載が可能であるという利点が
める。しかし、選択したレジンの種類により、耐湿信頼
匿、１Ｍ度サイクル信頼度に差があり、一般に、気密封
止の方法に比較し、信頼度が劣るという問題がめった。Among the above-mentioned conventional techniques, the former hermetic sealing method is often technically difficult. For example, in an anastomosis using low melting point glass as adhesive material for soil, the melting point of low melting point glass is 450 to 5
There is a problem that the temperature is about 00° C., and the component cannot withstand this temperature, and at the same time, it cannot be mounted on a hybrid integrated circuit. Further, when gold-tin solder is used as the sealing material, there is a problem that as the area of the sealing portion increases, the percentage of sealing failures increases. Therefore, in hybrid integrated circuits in which a variety of components such as semiconductor chips, capacitors, resistors, etc. are mixed together, it is often technically difficult to hermetically seal them. There was a problem ◇ - 1 of the conventional technologies. The latter method of coating semiconductor chips with silicone resin has the advantage that the curing temperature of the resin can be suppressed to about 150° C., so that it can be mounted together with other i-mounted components that are sensitive to heat. However, depending on the type of resin selected, there are differences in moisture resistance reliability and 1M degree cycle reliability, and there is often a problem that the reliability is generally inferior to that of hermetic sealing methods.
その解決手段として、半導体チップをコートする材料と
して、シリコーン・グルを床用する方法が提案された０
（文献ニアイエムシ（ＩＭＣ）１９８４東京大会論文「
シーリング・メカニズム・オプ・シリコン・ジエリｅエ
ンキャッシュレーション赤ウィズ・ハイ拳すライアビリ
テイ（Ｓｅａｌｉｎｇ Ｍｅｃｈａｎｉｓｍ ｏｆ ５
ｉｌｉｃｏｎｅＪｅｌｙ Ｅｎｃａｐｓｕｌａｔｉｏｎ
ｗｉｔｈ Ｈｌｇｈ Ｒｅｌｉａｂｉｌｉｔｙ月参照
）
しかるに前記の文献には安価に混成集積回路を製造可能
な構成については記載されていない。As a solution to this problem, a method was proposed to use silicone glue as a material to coat semiconductor chips.
(Reference Nii MC (IMC) 1984 Tokyo Conference Paper "
Sealing Mechanism of 5
iliconeJely Encapsulation
However, the above-mentioned document does not describe a configuration that allows the production of hybrid integrated circuits at low cost.
本発明の目的は前記従来技術の問題点を解決し、各易な
製造工程にて安価にかつ耐湿性および温度サイクルの信
頼度の同上を可能にした混成集積回路を提供することに
おる。SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art, and to provide a hybrid integrated circuit that can be manufactured easily, at low cost, and with the same moisture resistance and temperature cycle reliability.
前記の目的は混成集積回路基板上に半導体チップなどを
搭載した混成集積回路に２いて、前記混成集積ｌＰＪ路
上に少なくとも半導体チップを覆うキャップを設け、こ
のキャップに２個の穴とこれらの穴間に凸部を設け、か
つ前記半導体チップをキャップ内にてシリコン・ゲルに
よシ覆い、かつ混成果槓旦路基板上のキャップを営めた
全面にシリコーン樹脂を覆うように構成することによシ
達成される。The above purpose is to provide a hybrid integrated circuit in which a semiconductor chip or the like is mounted on a hybrid integrated circuit board, to provide a cap covering at least the semiconductor chip on the hybrid integrated circuit board, and to provide two holes in the cap and a hole between these holes. A convex portion is provided on the cap, the semiconductor chip is covered with silicone gel in the cap, and the entire surface of the cap on the hybrid substrate is covered with silicone resin. achieved.
混成集積回路基板上に形成した半導体チップおよび他の
回路素子を中ヤッグにて覆うことＫよシ外力から半導体
チップを保護することができる。By covering the semiconductor chip and other circuit elements formed on the hybrid integrated circuit board with the inner jacket, the semiconductor chip can be protected from external forces.
また半導体チップをキャップ内にてシリコーン・ゲルで
機うことによシ半導体チップの表面を保護し、これによ
って耐湿性を同上することができる。Furthermore, by enclosing the semiconductor chip in the cap with silicone gel, the surface of the semiconductor chip can be protected, thereby improving moisture resistance.
前記キャップには２個の比較的小さな穴を形成し、−刀
の穴はシリコーン樹脂の注入用でるり、他方の穴はシリ
コーン餉脂を注入したさいのキャップ内の空気を外部に
放出するものである。またキャップの大間の凸部はシリ
コーン樹脂を充填した嘔いに空隙を形成し、この空隙に
よシ混成集積回路の周囲の温度が上昇し、シリコーン樹
脂が熱膨張したさいの逃は吻とな９、これによって温度
ブイタルの信頼性を同上することができるｏ嘔らに混成
来槓−路糞板上の全面をシリコーン樹脂で後うことによ
プキャップの小穴の保＠２よび混成集積回路全体の保護
となシ、これによって信頼性を向上することができる。Two relatively small holes are formed in the cap, - the knife hole is for injecting the silicone resin, and the other hole is for releasing the air inside the cap to the outside when the silicone resin is injected. It is. In addition, the convex part of the cap forms a gap in the cavity filled with silicone resin, and when the temperature around the hybrid integrated circuit rises due to this gap and the silicone resin thermally expands, the proboscis becomes the escape point. 9. This improves the reliability of the temperature control.In addition, the entire surface of the hybrid integrated circuit board is coated with silicone resin to protect the small holes in the cap and the entire hybrid integrated circuit. protection, thereby improving reliability.
以下、本発明の実施例を示す第１図乃至第５図について
説明する。第１図は本発明の一実施例を示す混成集積回
路の斜視図、第２図は半導体チップをボンディングした
状態を示す平面図、第３図（ａ）は第１図に示す混成集
積回路の平面図、第３図（１））は第５図（ａ）のＩ−
Ｉ矢視断面正面因である。1 to 5 showing embodiments of the present invention will be described below. 1 is a perspective view of a hybrid integrated circuit showing an embodiment of the present invention, FIG. 2 is a plan view showing a state in which semiconductor chips are bonded, and FIG. 3(a) is a perspective view of a hybrid integrated circuit shown in FIG. 1. The plan view, Fig. 3 (1)) is I- in Fig. 5 (a).
This is the front cause of the section viewed from the I arrow.
図示の如く混成集積回路基板１上に半導体チップ５をホ
ンディングしたのち、キャップＳを混成集積回路基板１
上に做着剤６を用いて接着する。After bonding the semiconductor chip 5 onto the hybrid integrated circuit board 1 as shown in the figure, the cap S is attached to the hybrid integrated circuit board 1.
Adhesion is made using adhesive 6 on top.
ついでキャップ３上にあけられた２個の小穴４ａ、４ｂ
のうち１万の小穴４ａから内部にシリコーン・グル７を
注入して半導体チップ５を完全に被覆する０そのさいキ
ャップ３の中央部にあらかじめ形成され九凸ｓ８は空１
ｉ８ａとする。Next, two small holes 4a and 4b are made on the cap 3.
Among them, silicone glue 7 is injected into the interior through 10,000 small holes 4a to completely cover the semiconductor chip 5. At that time, the nine convex s8 formed in advance in the center of the cap 3 are empty 1.
Let's call it i8a.
ついで、シリコーン・ゲル７を温度１５００程度に加熱
して硬化したのち、キャップ３を含む混成集積Ｉｇｌ略
基取１上の全面をシリコーン樹脂２で血布またはディッ
プし、温度１２５℃程度に加熱してシリコーン樹脂２を
硬化する。Next, after the silicone gel 7 is heated to a temperature of about 1500° C. and cured, the entire surface of the base 1 of the hybrid assembly including the cap 3 is coated or dipped with silicone resin 2, and heated to a temperature of about 125° C. to harden the silicone resin 2.
なお、端子９の取付けは半導体チップ５のボンティング
前でもキャップ３を混成集積回路基板１上に接着したあ
とでもよい。またキャップ３の材質は混成集積回路基板
１の線樹脂張係数に近いものがよい、さらにキャップ３
の接着程度はシリコーン・グル７を注入したときに、シ
リコーン・ゲル７がしみ出さない程度のものでよい。Note that the terminals 9 may be attached before bonding the semiconductor chip 5 or after bonding the cap 3 onto the hybrid integrated circuit board 1. The material of the cap 3 should preferably be close to the tensile coefficient of the wire resin of the hybrid integrated circuit board 1;
The degree of adhesion may be such that the silicone gel 7 does not ooze out when the silicone gel 7 is injected.
したがって本発明によれば、混成集積（９）賂基板上の
半導体チップ５がシリコーン・ゲル７で覆われているの
で、耐湿性および温度サイクルの信頼度を同上すること
ができる。Therefore, according to the invention, since the semiconductor chip 5 on the hybrid integrated (9) substrate is covered with silicone gel 7, the same moisture resistance and temperature cycle reliability can be achieved.
また簡単な構成、容易な製造工程にて製作可能であるの
で、安価な製造原価にて製作することができる。Furthermore, since it has a simple configuration and can be manufactured through an easy manufacturing process, it can be manufactured at low manufacturing cost.
つぎに第４図は本発明の他の一実施例を示す混成集積回
路の平面図である。Next, FIG. 4 is a plan view of a hybrid integrated circuit showing another embodiment of the present invention.
同図においては、混成集積回路基板１１上に半導体チッ
プ（図示せず）の他にチップコンデンサ１０を搭載した
場合を示すもので、この場合はチップコンデンサ１０を
キャップ１３の外方位置に設置されている。The figure shows a case where a chip capacitor 10 is mounted on a hybrid integrated circuit board 11 in addition to a semiconductor chip (not shown); in this case, the chip capacitor 10 is mounted outside the cap 13. ing.
しかるにこれに限定されるものでなく、チップコンチン
？１０をキャップ１３内に設置することも可能である◇
なお、図示の１４はキャップ１３に形成された２個の小
穴、１９は端子である〇したがってこの場合においても
前記第１の実施例と同一効果を期待することができる。However, it is not limited to this, but is it chip contin? 10 can also be installed inside the cap 13◇
Note that 14 in the drawings are two small holes formed in the cap 13, and 19 is a terminal. Therefore, in this case as well, the same effect as in the first embodiment can be expected.
以上述べたる如く、本発明によれは、混成集積回路基板
上の半纏体チップがシリコーン・ゲルで後わｎているの
で、耐湿性および温度サイクルの信頼度を同上すること
ができる。As described above, according to the present invention, since the semi-integrated chip on the hybrid integrated circuit board is coated with silicone gel, moisture resistance and temperature cycle reliability can be improved.
筐た簡単な傳成、容易な製造工程にて製作可能であるの
で、安価な製造原価にて製作することができる。Since the housing can be manufactured using a simple design and an easy manufacturing process, it can be manufactured at a low manufacturing cost.
第１図は本発明の一実施例を示す混成集積回路の斜視図
、第２図は半導体チップをボンディングした状態を示す
平面図、第３図（ａ）は第１図に示す混成集積回路の平
面図、第３図（ｂ）は第５図（ａ）のニーＩ矢視断面正
面図、第４図は本発明の他の一実施例を示す混成集積回
路の平面図である。
１．１１・・・混成集積回路基板、２・・・シリコーン
ｍ脂、５．１５−・・キャップ、４ ａ、 ４ ｂ、
１４−小穴、５・・・半導体チップ、６・・・接着
剤、７・・・シリコーン・ゲル、８・・・凸部、８ａ・
・・空隙、９．１４・・・熾子〇
、ど−1 is a perspective view of a hybrid integrated circuit showing an embodiment of the present invention, FIG. 2 is a plan view showing a state in which semiconductor chips are bonded, and FIG. 3(a) is a perspective view of a hybrid integrated circuit shown in FIG. 1. 3(b) is a sectional front view taken along the knee I arrow in FIG. 5(a), and FIG. 4 is a plan view of a hybrid integrated circuit showing another embodiment of the present invention. 1.11...Mixed integrated circuit board, 2...Silicone M resin, 5.15-...Cap, 4 a, 4 b,
14-Small hole, 5... Semiconductor chip, 6... Adhesive, 7... Silicone gel, 8... Convex part, 8a.
...Void, 9.14...Shiko〇, Do-
Claims (1)
混成集積回路において、前記混成集積回路上に少なくと
も半導体チップを覆うキャップを設け、このキャップに
比較的小さな形状の少なくとも２個の小穴と、これらの
小穴間に凸部を設け、前記半導体チップをキャップ内に
てシリコーン・ゲルにて覆いかつ混成集積回路基板上の
前記キャップを含めた全面をシリコーン樹脂にて覆うご
とく構成したことを特徴とする混成集積回路。1. In a hybrid integrated circuit in which a semiconductor chip or the like is mounted on a hybrid integrated circuit board, a cap is provided on the hybrid integrated circuit to cover at least the semiconductor chip, and this cap has at least two small holes having a relatively small shape, and these small holes. A hybrid integrated circuit characterized in that a convex portion is provided between the caps, the semiconductor chip is covered with silicone gel within the cap, and the entire surface of the hybrid integrated circuit board including the cap is covered with silicone resin. circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9447286A JPS62252155A (en) | 1986-04-25 | 1986-04-25 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9447286A JPS62252155A (en) | 1986-04-25 | 1986-04-25 | Hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62252155A true JPS62252155A (en) | 1987-11-02 |
Family
ID=14111222
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9447286A Pending JPS62252155A (en) | 1986-04-25 | 1986-04-25 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62252155A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6731001B2 (en) | 2000-08-10 | 2004-05-04 | Denso Corporation | Semiconductor device including bonded wire based to electronic part and method for manufacturing the same |
| EP1729554A2 (en) | 2005-05-31 | 2006-12-06 | Fujitsu Limited | Soldering method, electronic part, and part-exchanging method |
-
1986
- 1986-04-25 JP JP9447286A patent/JPS62252155A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6731001B2 (en) | 2000-08-10 | 2004-05-04 | Denso Corporation | Semiconductor device including bonded wire based to electronic part and method for manufacturing the same |
| EP1729554A2 (en) | 2005-05-31 | 2006-12-06 | Fujitsu Limited | Soldering method, electronic part, and part-exchanging method |
| EP1729554A3 (en) * | 2005-05-31 | 2007-08-01 | Fujitsu Limited | Soldering method, electronic part, and part-exchanging method |
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