JPH0317220B2 - - Google Patents
Info
- Publication number
- JPH0317220B2 JPH0317220B2 JP59011174A JP1117484A JPH0317220B2 JP H0317220 B2 JPH0317220 B2 JP H0317220B2 JP 59011174 A JP59011174 A JP 59011174A JP 1117484 A JP1117484 A JP 1117484A JP H0317220 B2 JPH0317220 B2 JP H0317220B2
- Authority
- JP
- Japan
- Prior art keywords
- metal
- resin
- main surface
- hole
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910052751 metal Inorganic materials 0.000 claims description 34
- 239000002184 metal Substances 0.000 claims description 34
- 239000004065 semiconductor Substances 0.000 claims description 25
- 229920005989 resin Polymers 0.000 claims description 23
- 239000011347 resin Substances 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 11
- 238000007789 sealing Methods 0.000 claims description 9
- 239000002131 composite material Substances 0.000 claims 4
- 239000004020 conductor Substances 0.000 claims 2
- 229910044991 metal oxide Inorganic materials 0.000 claims 2
- 150000004706 metal oxides Chemical class 0.000 claims 2
- 230000000149 penetrating effect Effects 0.000 claims 1
- 230000002093 peripheral effect Effects 0.000 claims 1
- 229920003002 synthetic resin Polymers 0.000 description 8
- 239000000057 synthetic resin Substances 0.000 description 8
- 239000011521 glass Substances 0.000 description 6
- 239000003822 epoxy resin Substances 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000004382 potting Methods 0.000 description 2
- 229920002050 silicone resin Polymers 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Dispersion Chemistry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
本発明は、いわゆるチツプオンボードと称する
半導体装置の構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a so-called chip-on-board semiconductor device.
従来合成樹脂積層板を基板とし、その両面又は
片面に金層層を設け、かかる金属層を所要のパタ
ーンに形成したものに半導体素子を搭載し、ボン
デイング樹脂封止したものである。このチツプオ
ンボードと称する半導体装置においては、半導体
素子の周囲は樹脂でおおわれている。ところで樹
脂材料は少ないながらも水分を透過させ、かかる
樹脂が半導体素子表面に直接触れている為半導体
素子表面が汚染され、腐食される場合があり、半
導体装置としての耐湿性に難点があり、その信頼
性レベルは必ずしも高いものではなかつた。 Conventionally, a synthetic resin laminate is used as a substrate, a gold layer is provided on both or one side of the substrate, and a semiconductor element is mounted on the metal layer formed in a desired pattern and sealed with bonding resin. In this semiconductor device called chip-on-board, the periphery of the semiconductor element is covered with resin. By the way, resin materials allow moisture to permeate, although the amount is small, and since the resin is in direct contact with the surface of the semiconductor element, the surface of the semiconductor element may be contaminated and corroded, making it difficult to resist moisture as a semiconductor device. The reliability level was not necessarily high.
本発明は上記状況に鑑みチツプオンボードの耐
湿性レベルの向上を目的としてなされたものであ
つて、かかる発明の要旨は樹脂封止された樹脂材
料のうえに一定の表面処理を施した金属層を設け
ることにある。 The present invention has been made in view of the above circumstances with the aim of improving the moisture resistance level of chip-on-boards. The purpose is to establish
これは、耐湿性にかかる水分の侵入経路とし
て、チツプオンボードの基材であるガラス・エポ
キシ、ガラスポリイミド、ガラストリアジン等の
合成樹脂材料からのものと、樹脂封止したエポキ
シ樹脂やシリコーン樹脂からのものが考えられ、
その経路の長さを比較してみると、前者よりも後
者の場合の方が短く、耐湿性を大きく左右してお
り、その経路を金属層で遮断してしまうのであ
る。 This is because moisture can enter through synthetic resin materials such as glass epoxy, glass polyimide, and glass triazine, which are the base materials for the chip-on-board, and from epoxy resins and silicone resins that are sealed with resin. can be considered,
Comparing the lengths of the paths, the latter is shorter than the former, which greatly affects moisture resistance, and the path is blocked by the metal layer.
以下、実施例に基づき本発明を詳細に説明す
る。第１図は本発明の第一の実施例を示す断面図
である。合成樹脂基板１にはガラスエポキシ樹
脂、ガラスポリイミド樹脂、ガラストリアジン樹
脂を用いる。半導体素子２を固着すべきキヤビテ
イ部にには金属層３が設けられている。この金属
層３は合成樹脂基板の製造工程において、メツキ
によつても、成形した金属部材によつてもよい。
この金属層の機能は合成樹脂基板１からの水分の
侵入を防止する為であり、金属キヤツプ４と相俟
つて耐湿性の向上に寄与するものである。半導体
素子２は封止用樹脂５で覆われており、その上に
金属キヤツプ４がかぶつている。封止用樹脂とし
てはエポキシ樹脂、シリコーン樹脂があるが、樹
脂の種類は限定されない。封止用樹脂はポツテン
グ等の手段を用いて充填しても、また、エポキシ
樹脂等のトランスフア成形によつて充填してもよ
い。金属キヤツプ４と封止用樹脂５との密着性を
向上させる為に、金属キヤツプの表面には該金属
の酸化物を形成させておく。例えば金属としてア
ルミニウムを選択すればアルマイト処理によりア
ルミナ被膜を、銅を選択すれば酸化銅の被膜を形
成させる。これら被膜の形成については通常の表
面処理技術を利用することができる。そして、封
止用樹脂５と金属キヤツプをポツテングの場合に
は未硬化状態で封止用樹脂５上に金属キヤツプ４
を搭載し、必要に応じてクリツプ等の治工具を用
いて機械力を加えて所定の温度の恒温槽に放置す
る。使用温度時間は使用する封止樹脂の性質に依
存し熱硬化型樹脂の場合150℃〜200℃、１時間〜
15時間程度である。トランスフア成形の場合には
同系統の樹脂の未硬化状態のものを接着剤として
利用し、他はポツテングの場合と同様である。以
上、この様な構造であればキヤビテイ内への水分
の侵入はキヤツプと基体の境界部が最大の経路と
なるので、半導体装置としてその耐湿性を著しく
向上させることができる。 Hereinafter, the present invention will be explained in detail based on Examples. FIG. 1 is a sectional view showing a first embodiment of the present invention. The synthetic resin substrate 1 is made of glass epoxy resin, glass polyimide resin, or glass triazine resin. A metal layer 3 is provided in the cavity portion to which the semiconductor element 2 is to be fixed. This metal layer 3 may be formed by plating or by a molded metal member in the process of manufacturing the synthetic resin substrate.
The function of this metal layer is to prevent moisture from entering from the synthetic resin substrate 1, and together with the metal cap 4, it contributes to improving moisture resistance. The semiconductor element 2 is covered with a sealing resin 5, and a metal cap 4 is placed over it. Epoxy resins and silicone resins are available as sealing resins, but the type of resin is not limited. The sealing resin may be filled using means such as potting, or may be filled by transfer molding of epoxy resin or the like. In order to improve the adhesion between the metal cap 4 and the sealing resin 5, an oxide of the metal is formed on the surface of the metal cap. For example, if aluminum is selected as the metal, an alumite treatment will form an alumina film, and if copper is selected, a copper oxide film will be formed. Conventional surface treatment techniques can be used to form these films. When the sealing resin 5 and the metal cap are potted, the metal cap 4 is placed on the sealing resin 5 in an uncured state.
The device is then placed in a constant temperature bath at a predetermined temperature, applying mechanical force using jigs such as clips as necessary. The operating temperature and time depend on the properties of the sealing resin used; in the case of thermosetting resin, it is 150℃~200℃, 1 hour~
It takes about 15 hours. In the case of transfer molding, an uncured resin of the same type is used as an adhesive, and other aspects are the same as in the case of potting. As described above, with such a structure, the maximum route for moisture to enter the cavity is through the boundary between the cap and the base, so that the moisture resistance of the semiconductor device can be significantly improved.
半導体素子２を固着すべきキヤビテイ部の構造
に関しては、第２図の様な構造も有効である。即
ち、かかる部分直下の合成樹脂基板材に銅等の熱
伝導率の良好な金属１０を埋め込んでおくと、半
導体装置として低熱抵抗値を有するものとなる。
それを半導体素子２が下向きとなる様に合成樹脂
基板を設けられたスルーホール穴に外部リード１
１を半田付する等取付ければプラグイン形態の半
導体装置となる。そして金属板７の上にはヒート
シンクを設ければさらに放熱の効果が上る。半導
体装置としての外形形態としては、外部リードの
取り付けていないいわゆるリードレスチツプキヤ
リアタイプでも、外部リードを取付けて、デユア
ルインライン、シングルインライン、プラグイン
の夫々のタイプのものを作ることができる。 Regarding the structure of the cavity portion to which the semiconductor element 2 is to be fixed, a structure as shown in FIG. 2 is also effective. That is, if a metal 10 having good thermal conductivity, such as copper, is embedded in the synthetic resin substrate directly under such a portion, the semiconductor device will have a low thermal resistance value.
External lead 1 is inserted into the through-hole hole provided with the synthetic resin board so that semiconductor element 2 faces downward.
1 is attached by soldering or the like, it becomes a plug-in type semiconductor device. If a heat sink is provided on the metal plate 7, the heat dissipation effect will be further improved. As for the external form of the semiconductor device, even if it is a so-called leadless chip carrier type in which no external leads are attached, external leads can be attached to make dual-in-line, single-in-line, and plug-in types.
第１図は本発明の第１の実施例を示す横断面
図、第２図は本発明の第２の実施例を示す横断面
図である。
ここに、１……合成樹脂基板、２……半導体素
子、３……金属層、４……金属キヤツプ、５……
封止用樹脂、６……樹脂枠、７……金属板、８…
…配線層、９……スルーホール穴、１０……金
属、１１……外部リードである。
FIG. 1 is a cross-sectional view showing a first embodiment of the invention, and FIG. 2 is a cross-sectional view showing a second embodiment of the invention. Here, 1...Synthetic resin substrate, 2...Semiconductor element, 3...Metal layer, 4...Metal cap, 5...
Sealing resin, 6...Resin frame, 7...Metal plate, 8...
...Wiring layer, 9...Through hole, 10...Metal, 11...External lead.
Claims (1)
体装置であつて、前記合成基板の一主面より他主
面に向つて凹部を形成し、前記凹部の底面および
側面を金属層で被覆し、前記凹部下の前記他主面
の部分からその周囲部に延在して該他主面を金属
板で被覆し、前記凹部内の前記金属層上に半導体
素子を搭載し、前記半導体素子を含む前記凹部な
らびにその周囲の前記一主面を樹脂で封止し、表
面に金属酸化被膜を形成した金属キヤツプにより
前記樹脂を、該金属酸化被膜を該樹脂に密着させ
て、覆つたことを特徴とする半導体装置。 ２ 電気導体配線を有する合成基板を用いた半導
体装置であつて、前記合成基板の一主面から他主
面に貫通する貫通孔が設けられ、前記他主面に前
記貫通孔を閉塞する金属板が被着され、前記金属
板上の前記貫通孔内に金属が埋め込まれ、前記貫
通孔内の前記金属上から該貫通孔の露呈する側面
を被覆しかつ該貫通孔の周辺の前記一主面上に延
在する金属層が設けられ、前記貫通孔内の前記金
属上の前記金属層上に半導体素子が搭載され、前
記半導体素子および前記金属膜を封止する樹脂が
設けられ、前記樹脂を金属キヤツプで覆つたこと
を特徴とする半導体装置。[Scope of Claims] 1. A semiconductor device using a composite substrate having electrical conductor wiring, wherein a recess is formed from one main surface of the composite substrate toward the other main surface, and the bottom and side surfaces of the recess are made of metal. covering the other main surface with a metal plate extending from a portion of the other main surface under the recess to a peripheral portion thereof, and mounting a semiconductor element on the metal layer in the recess, The concave portion containing the semiconductor element and the main surface around the concave portion are sealed with a resin, and the resin is covered with a metal cap having a metal oxide film formed on the surface, and the metal oxide film is brought into close contact with the resin. A semiconductor device characterized by: 2. A semiconductor device using a composite substrate having electrical conductor wiring, wherein a through hole penetrating from one main surface of the composite substrate to the other main surface is provided, and a metal plate that closes the through hole on the other main surface. is deposited, and a metal is embedded in the through hole on the metal plate, covering the exposed side surface of the through hole from above the metal in the through hole, and the one principal surface around the through hole. A metal layer extending above is provided, a semiconductor element is mounted on the metal layer on the metal in the through hole, a resin is provided for sealing the semiconductor element and the metal film, and a resin is provided to seal the semiconductor element and the metal film. A semiconductor device characterized by being covered with a metal cap.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59011174A JPS60154543A (en) | 1984-01-24 | 1984-01-24 | Semiconductor device using synthetic resin substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59011174A JPS60154543A (en) | 1984-01-24 | 1984-01-24 | Semiconductor device using synthetic resin substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60154543A JPS60154543A (en) | 1985-08-14 |
| JPH0317220B2 true JPH0317220B2 (en) | 1991-03-07 |
Family
ID=11770689
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59011174A Granted JPS60154543A (en) | 1984-01-24 | 1984-01-24 | Semiconductor device using synthetic resin substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60154543A (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62217645A (en) * | 1986-03-19 | 1987-09-25 | Fujitsu Ltd | Manufacture of semiconductor device |
| JP2554059Y2 (en) * | 1988-02-18 | 1997-11-12 | シャープ株式会社 | Semiconductor device mounting structure |
| US5173766A (en) * | 1990-06-25 | 1992-12-22 | Lsi Logic Corporation | Semiconductor device package and method of making such a package |
| US5455456A (en) * | 1993-09-15 | 1995-10-03 | Lsi Logic Corporation | Integrated circuit package lid |
| US5798909A (en) * | 1995-02-15 | 1998-08-25 | International Business Machines Corporation | Single-tiered organic chip carriers for wire bond-type chips |
| KR100206894B1 (en) * | 1996-03-11 | 1999-07-01 | 구본준 | Bga package |
| EP0948047A3 (en) * | 1998-03-20 | 1999-12-22 | Caesar Technology Inc. | Electronic component cooling arrangement |
| JP5673647B2 (en) * | 2012-10-12 | 2015-02-18 | ダイキン工業株式会社 | module |
-
1984
- 1984-01-24 JP JP59011174A patent/JPS60154543A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60154543A (en) | 1985-08-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2642548B2 (en) | Semiconductor device and manufacturing method thereof | |
| KR20090056594A (en) | Semiconductor power module package with temperature sensing element and its manufacturing method | |
| US10643940B2 (en) | Electronic device with die being sunk in substrate | |
| US5814882A (en) | Seal structure for tape carrier package | |
| KR930004247B1 (en) | Resin Sealed Semiconductor Device | |
| JPH0317220B2 (en) | ||
| JP2770947B2 (en) | Resin-sealed semiconductor device and method of manufacturing the same | |
| JPH10135380A (en) | Semiconductor device | |
| EP0186667A1 (en) | Mounting semi-conductor chips. | |
| JPH0420279B2 (en) | ||
| JP2024540770A (en) | Electronic component and method for manufacturing electronic component | |
| KR100220492B1 (en) | Clip lead package | |
| KR100221562B1 (en) | Structure of bga package and method of making same | |
| JP2010267794A (en) | Power module | |
| JPH0334909Y2 (en) | ||
| JP2612468B2 (en) | Substrate for mounting electronic components | |
| JPS6134989A (en) | Substrate for placing electronic part and method of producing same | |
| JP2553665B2 (en) | Semiconductor device | |
| JP2906673B2 (en) | Semiconductor device | |
| KR100279252B1 (en) | Ceramic Package | |
| JPH0922960A (en) | Multichip module device and its manufacture | |
| JPH06216492A (en) | Electronic device | |
| JPH04124860A (en) | Semiconductor package | |
| JPH0758246A (en) | Semiconductor device and manufacturing method thereof | |
| JP2603101B2 (en) | Substrate for mounting electronic components |