JPS6224169A - Semiconductor ic apparatus - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to semiconductor integrated circuit device technology and LSI (
The present invention relates to a technique that is particularly effective when applied to large-scale semiconductor integrated circuit devices (large-scale semiconductor integrated circuit devices), and relates to a technique that is particularly effective when applied to, for example, a semiconductor integrated circuit device that includes a built-in test circuit.

[Background technology]

As the circuits within a semiconductor integrated circuit device become more complex, it becomes difficult to test the semiconductor integrated circuit device.

Therefore, as described in "Nikkei Electronics June 3, 1985 issue" published by Nikkei McGraw-Hill, p. 171 (scan bus method), it is possible to form a circuit that is easy to test from the beginning in a semiconductor integrated circuit device. It's starting to get worse.

For example, as shown in FIG.
In addition to the circuit 1 that performs the original function, there are a plurality of test switching circuits Sl and S that set test conditions for this circuit 1.
2. ... to be built-in. And each switching circuit 81.8
Various test conditions are created by setting combinations of the switching states of 2... using external test pattern written data.

Thereby, the circuit 1 formed in the semiconductor integrated circuit device IC can be tested for each circuit block 11, 12.

In this case, the test original data Cin is input from the test terminals Ptl and Pt2. The input test pattern φ data Cin is decoded by the decoder 2 into an individual control signal C3.

Then, the switching states of the respective temperature switching circuits Sl, S2, . . . are individually set by the decoded control signal Cs. 21° indicates an inverter forming part of the decoder 2.

However, in the semiconductor integrated circuit device described above, the original functional terminals Pfl, Pf2. In addition to . . . , a plurality of test terminals Ptl and Pt2 are required.

Furthermore, the number of test terminals Ptl and Pt2 increases as the number of test condition combinations increases. Therefore, in order to perform precise tests, the original functional terminals Pfl, Pf2. The inventor has found that a problem arises in that a large number of test terminals P t 1 * Pt 2 + . . . must be provided in addition to .

[Purpose of the invention]

The purpose of this invention is to reduce the number of test terminals while
An object of the present invention is to provide a semiconductor integrated circuit device technology that allows a large number of test condition combinations to be set and allows precise test execution.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief description of typical inventions disclosed in this application is as follows.

That is, by incorporating test pattern data generation means such as a pseudo-random signal generation circuit into a semiconductor integrated circuit device, it is possible to increase the number of combinations of test conditions that can be set with a small number of test terminals. This makes it possible to perform precise tests without increasing the mounting cost of semiconductor integrated circuit devices.
This goal is achieved.

〔Example〕

Hereinafter, typical embodiments of the present invention will be described with reference to the drawings.

In addition, in the drawings, the same reference numerals in degrees Celsius indicate the same or corresponding parts.

FIG. 1 shows an embodiment of a main part of a semiconductor integrated circuit device according to the present invention.

The semiconductor integrated circuit device IC shown in FIG. 1 includes a circuit 1 that performs the original function and a plurality of test switching circuits Sl that set test conditions for the circuit 1.

S2. ...is built-in. Furthermore, K, its switching circuit Sl, S2. ..., a decoder 2, a test pattern data generating means 3, a power-on reset signal generating circuit 4, etc. are also built in. 21 indicates an inverter attached to the decoder 2.

The test pattern own data generating means 3 is constructed using a kind of stepping circuit, and performs stepping operation by a clock CP which is externally applied via the test terminal Ptl. The step contents updated by this step operation are taken out in parallel. The step contents taken out in parallel are inputted to the decoder 2 IIC as test)-putter/data Cin. The decoder 2 decodes the input test pattern data Cin and decodes each switching circuit S1. S2
．． . . . A signal Cs is created to individually control the following. As a result, each switching circuit Sl, S2 . . . . are sequentially variably set, and different test conditions are set for each combination. Then ℃, this makes circuit 10
Function tester circuit blocks 11, 12, . . . can be tested.

The test pattern conflict data generating means 3 is automatically reset to the initial state by the power-on reset signal generating circuit 4 immediately after the power for operation of the semiconductor integrated circuit device IC is turned on.

FIG. 2 shows a specific example of the test pattern-data generating means 2. As shown in FIG.

The test pattern data generating means 3 can be constructed using a pseudo-random signal generating circuit (PN code generating circuit), as shown in FIG. The pseudo-random signal generation circuit shown in the figure includes a plurality of flip 70 tubes SR.
It is a type of step circuit in which I to SR4 are connected in series in multiple stages, and the step output + is taken out from each shift stage.
Q.

-Q is used as the test pattern data Cin. In this case, for example, the fourth shift stage (SR
4) and the step output of the first shift stage (SR1) are summed (exclusive OR) by the logic adder circuit 31, and this sum is applied to the serial shift input Sin of the shift register.
It's a trap to get you back. As a result, pseudo-random signals (PN codes) are obtained in parallel from the step outputs of each shift stage (SRI to 5R4). The pseudo-random signal obtained in this way has a property that the combination of codes is random and the codes therein continuously change bit by bit. Therefore, each circuit block 11, 12. It is very suitable for testing all the functions of...

As described above, in the semiconductor integrated circuit device IC described above,
Since the test pattern data Cin for variably setting various test conditions is generated inside the semiconductor integrated circuit device C4n, a test terminal for supplying the test pattern data Cin is not necessary. As the test terminal, only the terminal Pt1 for introducing the clock CPt for operating the test pattern data generating means 2 is sufficient. As a result, it is possible to increase the number of combinations of test conditions that can be set in stages with a small number of test terminals, and it is possible to perform precise tests without increasing the mounting cost of semiconductor integrated circuit devices. become able to.

〔effect〕

[13 For example, by incorporating test-pattern data generation means such as a pseudo-random signal generation circuit into a semiconductor integrated circuit device, it is possible to increase the number of combinations of test conditions that can be set with a small number of test terminals. This makes it possible to perform precise tests without increasing the mounting cost of semiconductor integrated circuit devices.
This effect can be obtained.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the above test
The pattern data generating means 2 may be a conventional multi-digit binary counter or a shift register.

[Application field]

Although the invention made by the present inventor is applied to a semiconductor integrated circuit device, which is the background field of application, it is not limited to this, and can also be applied to, for example, a hybrid mackerel integrated circuit device. Applicable.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a part of a circuit in a semiconductor integrated circuit device to which this invention is applied, FIG. 2 is a diagram showing an example of the configuration of a test pattern data generation means, and FIG. 3 is a diagram showing a configuration example of a test pattern data generation means. 1 is a diagram showing a part of a circuit in a semiconductor integrated circuit device that has been studied; FIG. IC...Semiconductor integrated circuit device, l...Circuit that performs the original function of the semiconductor integrated circuit device, 11.12...Circuit block, 2...Decoder, 3...Test pattern-7' -Event generation means, cIn...Test pattern fist data. Agent Patent Attorney Katsutoshi Ogawa ゛・-' Figure 1 Figure 2 Figure C1

Claims (1)

[Claims] 1. A semiconductor integrated circuit device incorporating a plurality of test switching circuits for setting test conditions, the test pattern data generation for individually controlling the setting state of each test switching circuit. A semiconductor integrated circuit device characterized by having a built-in means. 2. The semiconductor integrated circuit device according to claim 1, wherein the test pattern data generating means is constituted by a stepping circuit. 3. The semiconductor integrated circuit device according to claim 1, wherein the test pattern data generating means is constituted by a pseudo-random signal generating circuit.