JP5077806B2 - Memory test equipment - Google Patents

Description

  The present invention relates to a memory test apparatus that uses a memory as a device under test (hereinafter referred to as a DUT (Device Under Test)), and relates to a memory test apparatus that can test a memory having a DBI (Data Bus Inversion) function. .

  In recent years, the speed of memory has increased, and the transfer rate of input / output data has increased to several Gbps. When input / output data is several Gbps, power consumption becomes a problem.

  Generally, semiconductors with a CMOS (Complementary Metal Oxide Semiconductor) structure have input / output data of “0” (low level) to “1” (high level), or “1” (high level) to “0” (low level). The internal power consumption increases by changing to.

  Therefore, a DBI method that suppresses the rate of change of input / output data and reduces power consumption has been studied. The DBI method is a method in which, in the write data and the read data, the data of the previous cycle and the current data are compared with each other and the data is inverted when the number of changed bits is more than half (hereinafter referred to as inversion control). is there.

  Prior art documents related to the conventional memory test apparatus include the following.

JP 2004-348892 A

  FIG. 8 is a block diagram showing the configuration of such a conventional memory test apparatus. The DUT 80 is a device under test. The sequence control unit 1 outputs a program counter signal.

  The instruction memory 2 receives a program counter signal and outputs data called an instruction stored at an address indicated by the program counter signal.

  The address generation unit 3 receives an instruction from the instruction memory 2 and calculates and outputs an address signal of the DUT 80 according to the instruction. The data generation unit 4 receives an instruction from the instruction memory 2 and calculates and outputs a data signal of the DUT 80 in accordance with the instruction.

  The control signal generator 5 receives an instruction from the instruction memory 2 and outputs a control signal of the DUT 80, that is, a chip select, a write enable, a read enable, and the like according to the instruction.

  The address generating unit 3, the data generating unit 4, and the control signal generating unit 5 constitute a generating unit 50.

  The pin output selection unit 6 is provided for each pin of the memory test apparatus, and receives instructions from the instruction memory 2. Then, according to this instruction, one bit is selected and output from the address signal from the address generator 3, the data signal from the data generator 4, or the control signal from the control signal generator 5 (hereinafter referred to as this). The selected 1-bit signal is called a pattern signal).

  The sequence control unit 1, instruction memory 2, pin output selection unit 6 and generation unit 50 constitute a pattern generator 60.

  The waveform shaping unit 7 receives the pattern signal from the pin output selection unit 6 and outputs a signal to the DUT 80. The expected value determination unit 8 receives the pattern signal from the pin output selection unit 6 and the output signal from the DUT 80.

  The waveform shaping unit 7 and the expected value determination unit 8 are provided for each pin and constitute a pin electronics 61. The pattern generator 60 and the pin electronics 61 constitute a memory test apparatus 70.

  The operation of the conventional example shown in FIG. 8 will be described. First, before starting the test, data corresponding to instructions such as NOP (No Operation) and JUMP is loaded into the instruction memory. When the test is started, various settings of the pattern generator 60 and the pin electronics 61 are performed according to the test program.

  Then, a program counter signal is output from the sequence control unit and input to the instruction memory 2. The instruction memory 2 outputs the instruction stored at the address indicated by the program counter signal.

  In accordance with this instruction, the address generator 3 calculates an address to be applied to the DUT 80, and the data generator 4 calculates data to be applied to the DUT 80. At the same time, the control signal generator 5 generates chip select, write enable, read enable, and the like.

  In the test program, the correspondence between tester pins and DUT 80 pins is defined in advance. The pin output selection unit 6 distributes the address signal, the data signal, and the control signal to the corresponding pin electronics 61 according to this definition.

  The waveform shaping unit 7 shapes the waveform of the pattern signal based on the voltage level, waveform format, edge timing, etc. set by the test program, and outputs the waveform signal to the DUT 80. The waveform format means NRZ (Non Return to Zero), RZ (Return to Zero), or the like.

  The expected value determination unit 8 compares the pattern signal with the output signal of the DUT 80 at the timing specified by the test program when reading data from the DUT 80. The determination result is internally processed by the memory test apparatus 70.

  As a result, the pin output selection unit 6 receives the address signal output from the address generation unit 3, the data signal output from the data generation unit 4, and the control signal output from the control signal generation unit 5 according to the instruction from the instruction memory 2. One bit is selected from the above, and the waveform shaping unit 7 outputs to the DUT 80, or the expected value determination unit 8 compares and determines the data signal and the output signal from the DUT 80, so that the DUT 80 has no pattern data in advance. Since the pattern to be applied can be generated according to the test program, it becomes possible to test a device such as a large-capacity memory.

  FIG. 9 is a block diagram showing the configuration of the (A) data input circuit and (B) data output circuit of the memory having the DBI function.

  In FIG. 9A, write data (DQ) is input to the flip-flop 9, and an inverted signal (DBI) transmitted together with the write data is input to the flip-flop 10. The exclusive OR circuit 11 receives the output of the flip-flop 9 and the output of the flip-flop 10, and the flip-flop 12 receives the output of the exclusive OR circuit 11. Then, the output of the flip-flop 12 is written in the memory cell of the memory as write data.

  Actually, the write data has a plurality of bit widths, and the flip-flop 9 also has a plurality in accordance with the bit width of the write data. Further, the exclusive OR circuit 11 also performs exclusive OR for each bit, and the number of flip-flops 12 is increased in accordance with the bit width of the write data.

  In FIG. 9B, the comparison / determination unit 13 receives the read data read from the memory cell of the memory and the read data output one cycle before, that is, the output of the flip-flop 15, respectively. The sum circuit 14 receives the read data read from the memory cell of the memory and the output of the comparison determination unit 13.

  The output of the exclusive OR circuit 14 is input to the flip-flop 15, and the output of the flip-flop 15 is output as read data (DQ). The output of the comparison / determination unit 13 is input to the flip-flop 16, and the output of the flip-flop 16 is output as an inverted signal (DBI).

  The flip-flop 9, the flip-flop 10, the exclusive OR circuit 11, the flip-flop 12, the comparison / determination unit 13, the exclusive OR circuit 14, the flip-flop 15, and the flip-flop 16 constitute a memory 90.

  Similarly to the data input circuit (A), the read data read from the memory cell input to the comparison determination unit 13 and the read data output one cycle before have a plurality of bit widths and are exclusive. The OR circuit 14 also performs exclusive OR for each bit. There are a plurality of flip-flops 15 in accordance with the bit width of the read data.

  The operation of the memory having the DBI function shown in FIG. 9 will be described. At the time of writing, a memory controller (not shown) having a DBI function compares the write data output one cycle before with the write data currently being output, and whether the number of changed bits is more than half of the bit width. Determine whether.

  If the number of changed bits is greater than half the bit width, the memory controller inverts and outputs the write data currently being output and outputs the inverted signal “1”.

  In the (A) data input circuit of the memory 90, the bit-inverted write data is input to the DQ terminal, and the inverted signal is input to the DBI terminal. Since the inverted signal “1” is input to one input terminal of the exclusive OR circuit 11, the write data is bit-inverted and written to the memory cell via the flip-flop 12.

  On the other hand, if the number of changed bits is not more than half of the bit width, the memory controller outputs the write data that is currently output without performing bit inversion and also outputs the inverted signal “0”.

  Since the inverted signal “0” is input to one input terminal of the exclusive OR circuit 11 of the memory 90, the write data is written into the memory cell via the flip-flop 12 without being bit-inverted.

  Next, the operation at the time of reading will be described. The comparison / determination unit 13 performs bit comparison between the read data output one cycle before and the read data to be output at present, and determines whether the number of changed bits is more than half of the bit width.

  If the changed number of bits is greater than half the bit width, the comparison / determination unit 13 outputs “1”, and the exclusive OR circuit 14 inverts the read data. Then, the read data that has been bit-inverted through the flip-flop 15 and the inverted signal “1” are output through the flip-flop 16.

  The memory controller receives the read data and the inverted signal, and the inverted signal is “1”, so the read data is bit-inverted and used for processing.

  On the other hand, when the number of changed bits is not more than half of the bit width, the comparison / determination unit 13 outputs “0”, and the exclusive OR circuit 14 does not bit-invert the read data. Then, read data is output via the flip-flop 15 and an inverted signal “0” is output via the flip-flop 16.

  The memory controller receives the read data and the inverted signal, and since the inverted signal is “0”, the read data is used as it is without being bit-inverted.

  As a result, when writing, the memory controller having the DBI function compares the write data output one cycle before with the write data currently being output, and if the number of changed bits is more than half of the bit width, The write data to be output is bit-inverted and output, and the inverted signal “1” is output. At the time of reading, the read data output by the memory 90 one cycle before is compared with the read data currently output, and changes If the number of bits is more than half of the bit width, the read data to be currently output is bit-inverted and output, and the inverted signal “1” is output, whereby the data input to the memory 90 and the memory 90 Since the level change of data output from the memory is reduced, the power consumption of the memory 90 is reduced Obtain it becomes possible.

However, since the conventional example shown in FIG. 8 does not have a DBI function, the data signal applied to the DUT 80 cannot be inverted and there is a problem that a memory having the DBI function cannot be tested. .
Therefore, the problem to be solved by the present invention is to realize a memory test apparatus capable of testing a memory having a DBI function.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
In a memory test apparatus that selects an address signal from an address generation unit, a data signal from a data generation unit, and a control signal from a control signal generation unit by a pin output selection unit,
Provided between the data generation unit and the pin output selection unit, the data signal is time-series divided into a set of two input data, and one side input data and 2 Side input data is input at the same time , and the inversion control of whether to invert each of the first side input data and the second side input data is performed. 2-side output data, the 1-side output data and the 2-side output data, a 1-side inversion signal and a 2-side inversion signal indicating whether the 1-side input data and the 2-side input data are inverted , respectively A DBI generation unit for outputting
This DBI generator is
1-side input data and 2-side output data output 1 cycle before are bit-compared, and based on the comparison result, the 1-side input data is inverted and 1-side output data and 1-side inverted signal are output. A side DBI circuit;
When the one-side input data does not invert, the two-side input data following the one-side input data in time series and the one-side input data are bit-compared, and the two-side input data is inverted based on the comparison result. When the 1-side input data is inverted, the data obtained by bit-inversion of the 1-side input data is bit-compared with the 2-side input data, and the 2-side input data is controlled to be inverted based on the comparison result. A 2-side DBI circuit that outputs 2-side output data and a 2-side inverted signal, and inputs the 2-side output data to the 1-side DBI circuit;
It has.

The invention according to claim 2
In a memory test apparatus that selects an address signal from an address generation unit, a data signal from a data generation unit, and a control signal from a control signal generation unit by a pin output selection unit,
Provided between the data generation unit and the pin output selection unit, the data signal is time-series divided into n sets of input data (n is an integer of 3 or more), and the n sets of inputs 1-side input data through n-side input data are simultaneously input as data, and the inversion control of whether or not to invert each of the 1-side input data through n-side input data is performed, and the data resulting from this inversion control 1 side output data to n side output data, respectively, and 1 side output data to n side output data and 1 side inversion signal to indicate whether each of the 1 side input data to n side input data is inverted. a DBI generator for outputting an n-side inverted signal ;
The DBI generator includes a 1-side DBI circuit to an n-side DBI circuit as n DBI circuits corresponding to the 1-side input data to the n-side input data,
The 1-side DBI circuit performs bit comparison between the 1-side input data and the n-side output data output one cycle before, and controls the inversion of the 1-side input data based on the comparison result. Side inversion signal is output ,
When the 1-side input data is not inverted , the 2-side DBI circuit performs bit comparison between the 2-side input data that follows the 1-side input data in time series and the 1-side input data, and based on the comparison result, the 2 side DBI circuit When the side input data is inverted and when the one side input data is inverted, the bit side inversion of the data obtained by bit-inversion of the one side input data and the two side input data is performed, and the two side input is performed based on the comparison result. Invert data and output 2-side output data and 2-side inverted signal ,
The k-side DBI circuit (k is an integer not smaller than 3 and not larger than n) is the (k−1) -side output data when the k- side input data and the 1-side input data are not inverted when the 1-side input data is not inverted. And the k-side input data is inverted based on the comparison result. When the 1-side input data is inverted, the k-side input data and the 1-side input data are inverted (k -1) bit comparison with side output data and inversion control of the k side input data based on the comparison result to output k side output data and k side inversion signal ;
The n-side output data of the n-side DBI circuit is input to the 1-side DBI circuit .

The present invention has the following effects.
According to the first aspect of the present invention, in the memory test apparatus for selecting the address signal from the address generation unit, the data signal from the data generation unit, and the control signal from the control signal generation unit by the pin output selection unit, the data generation unit And the pin output selection unit, the data signal is time-series divided into two sets of input data, and one set of input data and two sets of input data are input as two sets of input data. Inversion control is performed to determine whether to invert each of the 1-side input data and the 2-side input data that are input at the same time, and the data obtained as a result of the inversion control are respectively output as 1-side output data and 2-side output data. and then, the a 1 side output data and the 2-side output data, the 1-side inverted signal indicating whether to reverse the respective one-side input data and the 2-side input data and Comprising a DBI generator outputting a side inverted signal, the DBI generating unit 1-side input data and the one-side input based on a two-side output data outputted to one cycle before the result of the comparison as well as bit comparison 1-side DBI circuit that controls the inversion of data and outputs 1-side output data and 1-side inverted signal, and when the 1-side input data is not inverted, the 2-side input data that follows the 1-side input data in time series and the 1-side input data is bit-compared and the 2-side input data is inverted based on the comparison result. When the 1-side input data is inverted, the 1-side input data is bit-inverted and the 2-side input data Bit comparison with input data and inversion control of the 2-side input data based on the comparison result to output 2-side output data and 2-side inversion signal, the 2-side output Since a data corresponding to the DBI system can be generated by providing a 2-side DBI circuit that inputs data to the 1-side DBI circuit, it is possible to test a device having a DBI function Become.

According to a second aspect of the present invention, in the memory test apparatus for selecting the address signal from the address generator, the data signal from the data generator, and the control signal from the control signal generator by the pin output selector, the data generator And the pin output selection unit, and the data signal is time-series divided into n sets of input data (n is an integer of 3 or more), and one side is input as the n sets of input data. Input data through n-side input data are simultaneously input , and inversion control is performed to determine whether to invert each of the 1-side input data through n-side input data. and output data to n-side output data, the 1 side and the output data to n-side output data, the 1-side reversing indicating whether obtained by inverting the respective 1-side input data to n-side input data Issue or comprising a DBI generator outputting the n-side inverted signal, the DBI generator, as the n DBI circuits corresponding to each of the 1-side input data to n-side input data, 1-side DBI circuit through n The 1-side DBI circuit compares the 1-side input data with the n-side output data output 1 cycle before and performs inversion control on the 1-side input data based on the comparison result. When the 1-side input data is not inverted , the 2-side DBI circuit outputs the 1-side output data and the 1-side inverted signal. And the second side input data is inverted based on the comparison result. When the first side input data is inverted, the first side input data is bit-inverted with the previous data. And 2-side input data inversion control the 2-side input data based on the comparison result as well as bit comparison, and outputs the 2-side output data and the 2-side inverted signal, k side DBI circuit (k is 3 or more n an integer), when the 1-side input data is not inverted, in the case where the 1-side input data and k-side input data is not inverted and a (k-1) side output data on the result of the comparison as well as bit comparison based the k-side input data inversion control, when the 1-side input data is inverted, the bit comparison between (k-1) side output data when the 1-side input data and the k-side input data is inverted At the same time, the k-side input data is inverted based on the comparison result, the k-side output data and the k-side inverted signal are output, and the n-side output data of the n-side DBI circuit is input to the 1-side DBI circuit. By doing so, data corresponding to the DBI method can be generated, so that a device having a DBI function can be tested.

  Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of a memory test apparatus according to the present invention. Components common to those in FIG. 1 and FIG. 8 is that a DBI generation unit 17 is provided between the data generation unit 4 and the pin output selection unit 6.

  The sequence control unit 1, instruction memory 2, pin output selection unit 6, DBI generation unit 17 and generation unit 50 constitute a pattern generator 62. The pin electronics 61 and the pattern generator 62 constitute a memory test device 71.

  The DBI generation unit 17 receives write data from the data generation unit 4 or read data that is an expected value used by the expected value determination unit 8.

  The operation of the embodiment shown in FIG. 1 will be described with reference to FIG. FIG. 2 is a configuration block diagram of the DBI generation unit 17.

  The comparison determination unit 18 receives the data input from the data generation unit 4 and the data output to the pin output selection unit 6 one cycle before, that is, the output of the flip-flop 20, and the exclusive OR circuit 19 The data input from the generation unit 4 and the output of the comparison determination unit 18 are input.

  The output of the exclusive OR circuit 19 is input to the flip-flop 20, and the output of the flip-flop 20 is output to the pin output selection unit 6 as pattern data to be applied to the DUT 80 or expected value data. The output of the comparison / determination unit 18 is input to the flip-flop 21 and the output of the flip-flop 21 is output as an inverted signal.

  The comparison determination unit 18, the exclusive OR circuit 19, the flip-flop 20, and the flip-flop 21 constitute a DBI generation unit 17.

  The operation of the embodiment shown in FIG. 2 will be described. The comparison determination unit 18 performs bit comparison between the data input from the data generation unit 4 and the data DQ output one cycle before, and determines whether or not the number of changed bits is greater than half the bit width.

  If the changed number of bits is greater than half the bit width, the comparison / determination unit 18 outputs “1”, and the data input from the data generation unit 4 is bit-inverted by the exclusive OR circuit 19. . Then, a bit-inverted data signal is output via the flip-flop 20 and an inverted signal “1” is output via the flip-flop 21.

  On the other hand, when the number of changed bits is not more than half of the bit width, the comparison determination unit 18 outputs “0”, and the data input from the data generation unit 4 by the exclusive OR circuit 19 is not bit-inverted. . Then, a data signal is output via the flip-flop 20 and an inverted signal “0” is output via the flip-flop 21.

  The data signal and the inverted signal output from the DBI generation unit 17 are input to the pin output selection unit 6. According to the instruction from the instruction memory 2, the pin output selection unit 6 selects an address signal from the address generation unit 3, a control signal from the control signal generation unit 5, or a data signal and an inverted signal from the DBI generation unit 17. Select 1 bit and output. Other operations are the same as in the conventional example shown in FIG.

  As a result, the DBI generation unit 17 compares the data input from the data generation unit 4 with the data DQ output one cycle before, and determines whether the changed number of bits is greater than half the bit width and inverts it. The pin output selection unit 6 controls the address signal output from the address generation unit 3, the data signal and the inverted signal after the inversion control output from the DBI generation unit 17, and the control output from the control signal generation unit 5. One bit is selected from the signal, and the waveform shaping unit 7 outputs to the DUT 80, or the expected value determination unit 8 compares and determines the data signal and the output signal from the DUT 80, thereby generating data corresponding to the DBI system. Therefore, it becomes possible to test a device having a DBI function.

  FIG. 3 is a block diagram showing the configuration of another embodiment of the memory test apparatus according to the present invention. The same reference numerals are given to the parts common to FIG. 3 and FIG. 1 is that the data generation unit 22, the DBI generation unit 23, and the pin output selection unit 24 are different.

  The address generator 3, the data generator 22, and the control signal generator 5 constitute a generator 51, and the sequence controller 1, instruction memory 2, DBI generator 23, pin output selector 24, and generator 51 are pattern generators. 63. Further, the pin electronics 61 and the pattern generator 63 constitute a memory test device 72.

  As in FIG. 1, the data generation unit 22 receives an instruction from the instruction memory 2 and calculates and outputs a data signal of the DUT 80 in accordance with the instruction.

  The difference between the data generator 22 and the data generator 4 in FIG. 1 is that the data generator 22 outputs two time-series data signals simultaneously. That is, the data generator 4 outputs “data 1”, “data 2”,... “Data n” and one data signal in time series, whereas the data generator 22 outputs a data output terminal. 2 and simultaneously output two data signals in time series such as “data 1 and data 2”, “data 3 and data 4”,. Dividing time-series data signals into several sets is called time-series division).

  The DBI generation unit 23 receives two data signals from the data generation unit 22 and determines whether or not to invert these data. Then, inversion control is performed, and the data after inversion control is output to the pin output selection unit 6.

  The pin output selection unit 24 is provided for each pin of the memory test apparatus, and receives an instruction from the instruction memory 2. Then, according to this instruction, one bit is selected from the address signal from the address generator 3, the control signal from the control signal generator 5, or the two data signals and the two inverted signals from the DBI generator 23. Output. Other operations are the same as those in the embodiment shown in FIG.

  FIG. 4 is a configuration block diagram of the DBI generation unit 23. In FIG. 4, two data signals output from the data generator 22 are input to the 1 side input data terminal and the 2 side input data terminal, respectively. That is, “data n−1” (n is an even number of 2 or more) is input to the 1 side input data terminal, and “data n” is input to the 2 side input data terminal.

  The 1-side input data terminal is connected to the input terminal of the inverter 25, one input terminal of the comparison determination unit 26, one input terminal of the comparison determination unit 27, and one input terminal of the exclusive OR circuit 29.

  The 2-side input data terminal is connected to one input terminal of the comparison / determination unit 27, one input terminal of the comparison / determination unit 28, one input terminal of the exclusive OR circuit 30, and one input terminal of the exclusive OR circuit 31. Each is connected. The output terminal of the inverter 25 is connected to the other input terminal of the comparison / determination unit 28, and the output terminal of the comparison / determination unit 26 is the other input terminal of the exclusive OR circuit 29, the control terminal of the selector 32, and the control terminal of the selector 33. And the data input terminal of the flip-flop 35.

  The output terminal of the comparison determination unit 27 is connected to the other input terminal of the exclusive OR circuit 30 and one input terminal of the selector 33, and the output terminal of the comparison determination unit 28 is the other input terminal of the exclusive OR circuit 31. The terminal and the other input terminal of the selector 33 are respectively connected.

  The output terminal of the exclusive OR circuit 29 is connected to the data input terminal of the flip-flop 34, and the output terminal of the exclusive OR circuit 30 is connected to one input terminal of the selector 32. The output terminal of the exclusive OR circuit 31 is connected to the other input terminal of the selector 32, and the output terminal of the selector 32 is connected to the input terminal of the flip-flop 36. The output terminal of the selector 33 is connected to the input terminal of the flip-flop 37.

  The output of the flip-flop 34 is output as 1-side output data (1-side DQ), and the output of the flip-flop 35 is output as a 1-side inverted signal (1-side DBI). The output of the flip-flop 36 is connected to the other input terminal of the comparison / determination unit 26 and output as 2-side output data (2-side DQ), and the output of the flip-flop 37 is output as a 2-side inverted signal (2-side DBI). Is done.

  In addition, the same clock signal is input to the clock input terminals of the flip-flops 34 to 37, respectively.

  The comparison determination unit 26, the exclusive OR circuit 29, the flip-flop 34, and the flip-flop 35 constitute a DBI circuit 40. The inverter 25, the comparison determination unit 27, the comparison determination unit 28, the exclusive OR circuit 30, the exclusive logic The sum circuit 31, selector 32, selector 33, flip-flop 36, and flip-flop 37 constitute a DBI circuit 41.

  The operation of the embodiment shown in FIG. 4 will be described. The comparison / determination unit 26 performs bit comparison between the 1-side input data and the 2-side output data output one cycle before, and determines whether or not the number of changed bits is greater than half the bit width.

  If the changed number of bits is greater than half the bit width, the comparison / determination unit 26 outputs “1”. If the changed number of bits is not greater than half the bit width, the comparison / determination unit 26 “0” is output. A signal obtained by delaying the output of the comparison determination unit 26 by one flip-flop 35 is a 1-side inverted signal.

  The exclusive OR circuit 29 inverts and outputs the 1-side input data when the output of the comparison determination unit 26 is “1”, and 1 when the output of the comparison determination unit 26 is “0”. The side input data is output as it is without being inverted. A signal obtained by delaying the output of the exclusive OR circuit 29 by 1 flip-flop by the flip-flop 34 becomes 1-side output data.

  The comparison determination unit 27 generates an inversion signal for the 2-side input data when the 1-side input data is not inverted by the inversion control. That is, the 1-side input data and the 2-side input data are bit-compared, and it is determined whether or not the number of changed bits is more than half the bit width.

  If the changed number of bits is greater than half of the bit width, the comparison / determination unit 27 outputs “1”. If the changed number of bits is not greater than half of the bit width, the comparison / determination unit 27 “0” is output.

  The exclusive OR circuit 30 receives the output of the comparison determination unit 27 and generates output data for the 2-side input data when the 1-side input data is not inverted by the inversion control. That is, the exclusive OR circuit 30 inverts and outputs the 2-side input data when the output of the comparison determination unit 27 is “1”, and outputs when the output of the comparison determination unit 27 is “0”. The 2-side input data is output as it is without being inverted.

  The comparison determination unit 28 generates an inverted signal for the 2-side input data when the 1-side input data is inverted by the inversion control. That is, the inverted data of the 1 side input data and the 2 side input data are bit-compared, and it is determined whether or not the number of changed bits is more than half the bit width.

  If the number of changed bits is greater than half of the bit width, the comparison / determination unit 28 outputs “1”, and if the number of changed bits is not greater than half of the bit width, the comparison / determination unit 28 “0” is output.

  The exclusive OR circuit 31 receives the output of the comparison determination unit 28 and generates output data for the 2-side input data when the 1-side input data is inverted by the inversion control. That is, the exclusive OR circuit 31 inverts and outputs the 2-side input data when the output of the comparison determination unit 28 is “1”, and outputs when the output of the comparison determination unit 28 is “0”. The 2-side input data is output as it is without being inverted.

  The selector 32 selects the output of the exclusive OR circuit 30 when the output of the comparison determination unit 26 is “0”, that is, the output data for the 2-side input data when the 1-side input data is not inverted by the inversion control. When the output of the comparison determination unit 26 is “1”, the output of the exclusive OR circuit 31, that is, the output data for the 2-side input data when the 1-side input data is inverted by the inversion control is selected.

  The selector 33 selects the output of the comparison determination unit 27 when the output of the comparison determination unit 26 is “0”, that is, the inverted signal for the 2-side input data when the 1-side input data is not inverted by the inversion control. When the output of the unit 26 is “1”, the output of the comparison / determination unit 28, that is, the inverted signal for the 2-side input data when the 1-side input data is inverted by the inversion control is selected.

  A signal obtained by delaying the output of the selector 32 by the flip-flop 36 by one clock becomes the 2-side output data (2-side DQ), and a signal obtained by delaying the output of the selector 33 by the flip-flop 37 by 1 clock is the 2-side inverted signal (2 side). DBI).

  The operation of the embodiment shown in FIG. 4 will be described more specifically with reference to FIG. FIG. 5 is a timing chart showing the operation of the DBI generating unit 23, and shows the operation when writing 10 data D1 to D10 (each data width is 8 bits) to the DUT 80.

  The 1-side input data is odd-numbered data of D1, D3, D5, D7, and D9, and the 2-side input data is even-numbered data of D2, D4, D6, D8, and D10. As shown in FIG. 5, the 1-side input data D1 and the 2-side input data D2 are input to the DBI generator 23 at the same timing. Similarly, D3 and D4, D5 and D6, D7 and D8, and D9 and D10 are input at the same timing.

  First, “0x00” is input as data D1 to the one-side input data terminal, and “0xFF” is input as data D2 to the two-side input data terminal. The initial values of the flip-flops 34 to 37 are “0”.

  In the comparison determination unit 26, the data D1 “0x00” is compared with the initial value “0x00” of the 2-side DQ. Level) is output. Further, in the exclusive OR circuit 29, since the output of the comparison determination unit 26 is “0”, the data D1 “0x00” is output without being inverted.

  Further, the comparison / determination unit 27 compares the data D1 “0x00” with the data D2 “0xFF”, and the number of bits that have changed is “8”, which is larger than the half of 4 bits, so “1” (high level) is set. Is output. Furthermore, in the exclusive OR circuit 30, since the output of the comparison determination unit 27 is “1”, the data D2 “0xFF” is inverted and output as “0x00”.

  Similarly, the comparison / determination unit 28 compares the inverted data “0xFF” of the data D1 “0x00” and the data D2 “0xFF”. "Is output. Further, in the exclusive OR circuit 31, since the output of the comparison determination unit 28 is “0”, the data D2 “0xFF” is output without being inverted.

  The selector 32 selects the output of the exclusive OR circuit 30 when the control signal output from the comparison determination unit 26 is “0”, and selects the output of the exclusive OR circuit 31 when the control signal is “1”. To do. Similarly, the selector 33 selects the output of the comparison determination unit 27 when the control signal output from the comparison determination unit 26 is “0”, and selects the output of the comparison determination unit 28 when the control signal is “1”. .

  In the cycle of data D1 / D2, since the output of the comparison determination unit 26 is “0”, the selector 32 selects the output of the exclusive OR circuit 30, and the selector 33 selects the output of the comparison determination unit 27.

  Accordingly, the data D1 “0x00” is output from the 1-side DQ (output of the flip-flop 34), and “0” is output from the 1-side DBI (output of the flip-flop 35). Further, “0x00” that is the inverted data of the data D2 “0xFF” is output from the 2-side DQ (output of the flip-flop 36), and “1” is output from the 2-side DBI (output of the flip-flop 37).

  Next, “0xFF” is input as data D3 to the 1 side input data terminal, and “0x3F” is input as data D4 to the 2 side input data terminal.

  The comparison determination unit 26 compares the data D3 “0xFF” with the 2-side DQ “0x00” and outputs “1” because the number of changing bits is “0” and more than the half of 4 bits. . Furthermore, in the exclusive OR circuit 29, since the output of the comparison determination unit 26 is “1”, the data D3 “0xFF” is inverted and output as “0x00”.

  Further, the comparison / determination unit 27 compares the data D3 “0xFF” with the data D4 “0x3F”, and outputs “0” because the number of changing bits is “2”, which is half of 4 bits or less. Furthermore, in the exclusive OR circuit 30, since the output of the comparison determination unit 27 is “0”, the data D4 “0x3F” is output without being inverted.

  Similarly, the comparison / determination unit 28 compares the inverted data “0x00” of the data D3 “0xFF” with the data D4 “0x3F”, and the number of changing bits is “0”, which is larger than the half of 4 bits. 1 "is output. Furthermore, in the exclusive OR circuit 31, since the output of the comparison determination unit 28 is “1”, the data D4 “0x3F” is inverted and output as “0xC0”.

  In the cycle of data D3 / D4, since the output of the comparison determination unit 26 is “1”, the selector 32 selects the output of the exclusive OR circuit 31, and the selector 33 selects the output of the comparison determination unit 28.

  Accordingly, “0x00” which is the inverted data of the data D3 “0xFF” is output from the 1 side DQ (output of the flip-flop 34), and “1” is output from the 1 side DBI (output of the flip-flop 35). The 2-side DQ (output of the flip-flop 36) outputs “0xC0” which is the inverted data of the data D4 “0x3F”, and the 2-side DBI (output of the flip-flop 37) outputs “1”.

  Next, “0x03” is input as data D5 to the 1 side input data terminal, and “0x3F” is input as data D6 to the 2 side input data terminal.

  The comparison / determination unit 26 compares the data D5 “0x03” with the two-side DQ “0xC0” and outputs “0” because the changing number of bits is “4”, which is half of 4 bits or less. Further, in the exclusive OR circuit 29, since the output of the comparison determination unit 26 is “0”, the data D5 “0x03” is output without being inverted.

  Further, the comparison / determination unit 27 compares the data D5 “0x03” with the data D6 “0x3F” and outputs “0” because the changing number of bits is “4”, which is half of 4 bits or less. Furthermore, in the exclusive OR circuit 30, since the output of the comparison determination unit 27 is “0”, the data D6 “0x3F” is output without being inverted.

  Similarly, the comparison / determination unit 28 compares the inverted data “0xFC” of the data D5 “0x03” and the data D6 “0x3F”. Since the number of changing bits is “4”, which is half of 4 bits or less, “0 "Is output. Further, in the exclusive OR circuit 31, since the output of the comparison determination unit 28 is “0”, the data D6 “0x3F” is output without being inverted.

  In the cycle of data D5 / D6, since the output of the comparison determination unit 26 is “0”, the selector 32 selects the output of the exclusive OR circuit 30, and the selector 33 selects the output of the comparison determination unit 27.

  Accordingly, the data D5 “0x03” is output from the 1-side DQ (output of the flip-flop 34), and “0” is output from the 1-side DBI (output of the flip-flop 35). Further, the data D6 “0x3F” is output from the 2-side DQ (output of the flip-flop 36), and “0” is output from the 2-side DBI (output of the flip-flop 37).

  Next, “0xC0” is input as data D7 to the 1 side input data terminal, and “0x0C” is input as data D8 to the 2 side input data terminal.

  The comparison determination unit 26 compares the data D7 “0xC0” with the “0x3F” of the 2-side DQ output and outputs “1” because the number of changing bits is “8”, which is more than half of 4 bits. . Furthermore, in the exclusive OR circuit 29, since the output of the comparison determination unit 26 is “1”, the data D7 “0xC0” is inverted and output as “0x3F”.

  Further, the comparison / determination unit 27 compares the data D7 “0xC0” and the data D8 “0x0C” and outputs “0” because the number of changing bits is “4”, which is a half of 4 bits or less. Further, in the exclusive OR circuit 30, since the output of the comparison determination unit 27 is “0”, the data D8 “0x0C” is output without being inverted.

  Similarly, the comparison / determination unit 28 compares the inverted data “0x3F” of the data D7 “0xC0” with the data D8 “0x0C”. "Is output. Further, in the exclusive OR circuit 31, since the output of the comparison determination unit 28 is “0”, the data D8 “0x0C” is output without being inverted.

  In the cycle of data D7 / D8, since the output of the comparison determination unit 26 is “1”, the selector 32 selects the output of the exclusive OR circuit 31, and the selector 33 selects the output of the comparison determination unit 28.

  Accordingly, “0x3F” which is the inverted data of the data D7 “0xC0” is output from the 1 side DQ (output of the flip-flop 34), and “1” is output from the 1 side DBI (output of the flip-flop 35). Further, the data D8 “0x0C” is output from the 2-side DQ (output of the flip-flop 36), and “0” is output from the 2-side DBI (output of the flip-flop 37).

  Finally, “0xFF” is input as data D9 to the 1 side input data terminal, and “0xFF” is input as data D10 to the 2 side input data terminal.

  The comparison / determination unit 26 compares the data D9 “0xFF” with the 2-side DQ output “0x0C” and outputs “1” because the number of changing bits is “6”, which is more than half of 4 bits. . Furthermore, in the exclusive OR circuit 29, since the output of the comparison determination unit 26 is “1”, the data D9 “0xFF” is inverted and output as “0x00”.

  Further, the comparison / determination unit 27 compares the data D9 “0xFF” with the data D10 “0xFF” and outputs “0” because the number of changing bits is “0”, which is less than 4 bits, which is a half. Furthermore, in the exclusive OR circuit 30, since the output of the comparison determination unit 27 is “0”, the data D10 “0xFF” is output without being inverted.

  Similarly, the comparison / determination unit 28 compares the inverted data “0x00” of the data D9 “0xFF” with the data D10 “0xFF”, and the number of changing bits is “8”, which is larger than the half 4 bits. 1 "is output. Furthermore, in the exclusive OR circuit 31, since the output of the comparison determination unit 28 is “1”, the data D10 “0xFF” is inverted and output as “0x00”.

  In the cycle of data D9 / D10, since the output of the comparison determination unit 26 is “1”, the selector 32 selects the output of the exclusive OR circuit 31, and the selector 33 selects the output of the comparison determination unit 28.

  Accordingly, “0x00” that is the inverted data of the data D9 “0xFF” is output from the 1 side DQ (output of the flip-flop 34), and “1” is output from the 1 side DBI (output of the flip-flop 35). Further, “0x00” that is the inverted data of the data D10 “0xFF” is output from the 2-side DQ (output of the flip-flop 36), and “1” is output from the 2-side DBI (output of the flip-flop 37).

  As a result, two sets of time-series data are generated from the data generation unit 22, that is, one-side input data and two-side input data are generated, and one DBI circuit 40 of the DBI generation unit 23 generates one-side input data. And the DQ output of the other DBI circuit 41 are compared and determined to perform inversion control, and the other DBI circuit 41 of the DBI generating unit 23 outputs the 1-side input data and the 2-side input data, or the 1-side input data. Inversion control is performed by comparing and determining the inverted data and the 2-side input data, and either one of the two inverted control data is selected and output by the DBI output of the DBI circuit 40, whereby the DBI method is achieved. Since corresponding data can be generated, it becomes possible to test a device having a DBI function.

  FIG. 6 is a configuration block diagram of another DBI generation unit. In FIG. 6, data is input from the data generation unit to the 1 side input data terminal, 2 side input data terminal, 3 side input data terminal, and 4 side input data terminal. The 1 side input data terminal is connected to the input terminal of the inverter 101, one input terminal of the comparison determination unit 102 and the data input terminal of the flip-flop 106, respectively, and the 2 side input data terminal is the other input terminal of the comparison determination unit 102, The comparison determination unit 103 is connected to one input terminal, one input terminal of the exclusive OR circuit 104, and one input terminal of the exclusive OR circuit 105.

  The 3-side input data terminal is connected to the data input terminal of the flip-flop 111, and the 4-side input data terminal is connected to the data input terminal of the flip-flop 112. The output terminal of the inverter 101 is connected to the other input terminal of the comparison determination unit 103, and the output terminal of the comparison determination unit 102 is connected to the other input terminal of the exclusive OR circuit 104 and the data input terminal of the flip-flop 108, respectively. The

  The output terminal of the comparison determination unit 103 is connected to the other input terminal of the exclusive OR circuit 105 and the data input terminal of the flip-flop 110, and the output terminal of the exclusive OR circuit 104 is connected to the data input terminal of the flip-flop 107. Connected. The output terminal of the exclusive OR circuit 105 is connected to the data input terminal of the flip-flop 109, and the output terminal of the flip-flop 106 is connected to the data input terminal of the flip-flop 117.

  The output terminal of the flip-flop 107 is connected to one input terminal of the comparison / determination unit 113 and the data input terminal of the flip-flop 118, and the output terminal of the flip-flop 108 is connected to the data input terminal of the flip-flop 119. The output terminal of the flip-flop 109 is connected to one input terminal of the comparison / determination unit 114 and the data input terminal of the flip-flop 120, and the output terminal of the flip-flop 110 is connected to the data input terminal of the flip-flop 121.

  The output terminal of the flip-flop 111 is the other input terminal of the comparison determination unit 113, the other input terminal of the comparison determination unit 114, one input terminal of the exclusive OR circuit 115, and one input terminal of the exclusive OR circuit 116. And the output terminal of the flip-flop 112 is connected to the data input terminal of the flip-flop 126. The output terminal of the comparison determination unit 113 is connected to the other input terminal of the exclusive OR circuit 115 and the data input terminal of the flip-flop 123, and the output terminal of the comparison determination unit 114 is the other input of the exclusive OR circuit 116. And the data input terminal of the flip-flop 125.

  The output terminal of the exclusive OR circuit 115 is connected to the data input terminal of the flip-flop 122, and the output terminal of the exclusive OR circuit 116 is connected to the data input terminal of the flip-flop 124. The output terminal of the flip-flop 117 is connected to the data input terminal of the flip-flop 131, and the output terminal of the flip-flop 118 is connected to the data input terminal of the flip-flop 132.

  The output terminal of the flip-flop 119 is connected to the data input terminal of the flip-flop 133, and the output terminal of the flip-flop 120 is connected to the data input terminal of the flip-flop 134. The output terminal of the flip-flop 121 is connected to the data input terminal of the flip-flop 135, and the output terminal of the flip-flop 122 is connected to one input terminal of the comparison determination unit 127 and the data input terminal of the flip-flop 136.

  The output terminal of the flip-flop 123 is connected to the data input terminal of the flip-flop 137, and the output terminal of the flip-flop 124 is connected to one input terminal of the comparison determination unit 128 and the data input terminal of the flip-flop 138. The output terminal of the flip-flop 125 is connected to the data input terminal of the flip-flop 139. The output terminal of the flip-flop 126 is the other input terminal of the comparison determination unit 127, the other input terminal of the comparison determination unit 128, and an exclusive OR circuit. 129 and one input terminal of the exclusive OR circuit 130, respectively.

  The output terminal of the comparison determination unit 127 is connected to the other input terminal of the exclusive OR circuit 129 and the data input terminal of the flip-flop 141, and the output terminal of the comparison determination unit 128 is the other input of the exclusive OR circuit 130. And the data input terminal of the flip-flop 143. The output terminal of the exclusive OR circuit 129 is connected to the data input terminal of the flip-flop 140, and the output terminal of the exclusive OR circuit 130 is connected to the data input terminal of the flip-flop 142.

  The output terminal of the flip-flop 131 is connected to one input terminal of the comparison / determination unit 144 and one input terminal of the exclusive OR circuit 145, and the output terminal of the flip-flop 132 is connected to one input terminal of the selector 146. The The output terminal of the flip-flop 133 is connected to one input terminal of the selector 147, and the output terminal of the flip-flop 134 is connected to the other input terminal of the selector 146.

  The output terminal of the flip-flop 135 is connected to the other input terminal of the selector 147, and the output terminal of the flip-flop 136 is connected to one input terminal of the selector 148. The output terminal of the flip-flop 137 is connected to one input terminal of the selector 149, and the output terminal of the flip-flop 138 is connected to the other input terminal of the selector 148.

  The output terminal of the flip-flop 139 is connected to the other input terminal of the selector 149, and the output terminal of the flip-flop 140 is connected to one input terminal of the selector 150. The output terminal of the flip-flop 140 is connected to one input terminal of the selector 151, and the output terminal of the flip-flop 142 is connected to the other input terminal of the selector 150.

  The output terminal of the flip-flop 143 is connected to the other input terminal of the selector 151, the output terminal of the comparison determination unit 144 is the other input terminal of the exclusive OR circuit 145, the control terminal of the selector 146, the control terminal of the selector 147, The control terminal of the selector 148, the control terminal of the selector 149, the control terminal of the selector 150, the control terminal of the selector 151, and the data input terminal of the flip-flop 153 are connected.

  The output terminal of the exclusive OR circuit 145 is connected to the data input terminal of the flip-flop 152, and the output terminal of the selector 146 is connected to the data input terminal of the flip-flop 154. The output terminal of the selector 147 is connected to the data input terminal of the flip-flop 155, and the output terminal of the selector 148 is connected to the data input terminal of the flip-flop 156.

  The output terminal of the selector 149 is connected to the data input terminal of the flip-flop 157, and the output terminal of the selector 150 is connected to the data input terminal of the flip-flop 158. The output terminal of the selector 151 is connected to the data input terminal of the flip-flop 159.

  The output of the flip-flop 152 is output as a 1-side DQ, and the output of the flip-flop 153 is output as a 1-side DBI. The output of the flip-flop 154 is output as the 2-side DQ, and the output of the flip-flop 155 is output as the 2-side DBI.

  The output of the flip-flop 156 is output as the 3-side DQ, and the output of the flip-flop 157 is output as the 3-side DBI. The output of the flip-flop 158 is connected to the other input terminal of the comparison / determination unit 144 and output as the 4-side DQ, and the output of the flip-flop 159 is output as the 4-side DBI.

    In addition, the same clock signal is input to the clock input terminals of the flip-flops 106 to 112, 117 to 126, 131 to 143, and 152 to 159, respectively.

  The flip-flop 106, the flip-flop 117, the flip-flop 131, the comparison determination unit 144, the exclusive OR circuit 145, the flip-flop 152, and the flip-flop 153 constitute the DBI circuit 200.

  The inverter 101, the comparison determination units 102 to 103, the exclusive OR circuits 104 to 105, the flip-flops 107 to 110, the flip-flops 118 to 121, the flip-flops 132 to 135, the selectors 146 to 147, and the flip-flops 154 to 155 are DBI circuits. 201 is configured.

  The flip-flop 111, the comparison determination units 113 to 114, the exclusive OR circuits 115 to 116, the flip-flops 122 to 125, the flip-flops 136 to 139, the selectors 148 to 149, and the flip-flops 156 to 157 constitute the DBI circuit 202.

  The flip-flop 112, the flip-flop 126, the comparison determination units 127 to 128, the exclusive OR circuits 129 to 130, the flip-flops 140 to 143, the selectors 150 to 151, and the flip-flops 158 to 159 constitute the DBI circuit 203.

  The operation of the embodiment shown in FIG. 6 will be described. The basic operation is the same as that of the embodiment shown in FIG. 4 except that the input data is time-series divided into a set of four data, and the four data are sequentially processed. is there.

  The comparison determination unit 102 generates an inversion signal for the 2-side input data when the 1-side input data is not inverted by the inversion control. That is, the 1-side input data and the 2-side input data are bit-compared, and it is determined whether or not the number of changed bits is more than half the bit width.

  If the changed number of bits is greater than half the bit width, the comparison / determination unit 102 outputs “1”. If the changed number of bits is not greater than half the bit width, the comparison / determination unit 102 “0” is output.

  The exclusive OR circuit 104 receives the output of the comparison determination unit 102 and generates output data for the 2-side input data when the 1-side input data is not inverted by the inversion control. That is, the exclusive OR circuit 104 inverts and outputs the 2-side input data when the output of the comparison determination unit 102 is “1”, and outputs when the output of the comparison determination unit 102 is “0”. The 2-side input data is output as it is without being inverted.

  The comparison determination unit 103 generates an inverted signal for the 2-side input data when the 1-side input data is inverted by the inversion control. That is, the inverted data of the 1 side input data and the 2 side input data are bit-compared, and it is determined whether or not the number of changed bits is more than half the bit width.

  If the changed number of bits is more than half the bit width, the comparison / determination unit 103 outputs “1”, and if the changed number of bits is not more than half the bit width, the comparison / determination unit 103 “0” is output.

  The exclusive OR circuit 105 receives the output of the comparison determination unit 103 and generates output data for the 2-side input data when the 1-side input data is inverted by the inversion control. That is, the exclusive OR circuit 105 inverts and outputs the 2-side input data when the output of the comparison determination unit 103 is “1”, and outputs when the output of the comparison determination unit 103 is “0”. The 2-side input data is output as it is without being inverted.

  Similarly, the comparison / determination unit 113 generates an inverted signal for the 3-side input data when the 1-side input data is not inverted by the inversion control. The exclusive OR circuit 115 receives the output of the comparison determination unit 113 and generates output data for the 3 side input data when the 1 side input data is not inverted by the inversion control.

  The comparison determination unit 114 generates an inverted signal for the 3 side input data when the 1 side input data is inverted by the inversion control. The exclusive OR circuit 116 receives the output of the comparison determination unit 114 and generates output data for the 3 side input data when the 1 side input data is inverted by the inversion control.

  The comparison determination unit 127 generates an inverted signal for the 4-side input data when the 1-side input data is not inverted by the inversion control. The exclusive OR circuit 129 receives the output of the comparison determination unit 127 and generates output data for the 4-side input data when the 1-side input data is not inverted by the inversion control.

  The comparison determination unit 128 generates an inverted signal for the 4-side input data when the 1-side input data is inverted by the inversion control. The exclusive OR circuit 130 receives the output of the comparison determination unit 128 and generates output data for the 4-side input data when the 1-side input data is inverted by the inversion control.

  The comparison determination unit 144 generates an inverted signal for the 1-side input data based on the 4-side output data (4-side DQ). The exclusive OR circuit 145 receives the output of the comparison determination unit 144 and generates output data for the one-side input data.

  The selector 146 selects the output of the flip-flop 132 when the output of the comparison determination unit 144 is “0”, that is, the output data for the 2-side input data when the 1-side input data is not inverted by the inversion control. When the output of the determination unit 144 is “1”, the output of the flip-flop 134, that is, the output data for the 2-side input data when the 1-side input data is inverted by the inversion control is selected.

  The selector 147 selects the output of the flip-flop 133 when the output of the comparison determination unit 144 is “0”, that is, the inverted signal for the 2-side input data when the 1-side input data is not inverted by the inversion control, and the comparison determination unit When the output of 144 is “1”, the output of the flip-flop 135, that is, the inverted signal for the 2-side input data when the 1-side input data is inverted by the inversion control is selected.

  The selector 148 selects the output of the flip-flop 136 when the output of the comparison determination unit 144 is “0”, that is, the output data for the 3 side input data when the 1 side input data is not inverted by the inversion control. When the output of 144 is “1”, the output of the flip-flop 138, that is, the output data for the 3-side input data when the 1-side input data is inverted by the inversion control is selected.

  The selector 149 selects the output of the flip-flop 137 when the output of the comparison determination unit 144 is “0”, that is, the inversion signal for the 3 side input data when the 1 side input data is not inverted by the inversion control. When the output of 144 is “1”, the output of the flip-flop 139, that is, the inverted signal for the 3-side input data when the 1-side input data is inverted by the inversion control is selected.

  The selector 150 selects the output of the flip-flop 140 when the output of the comparison determination unit 144 is “0”, that is, the output data for the 4-side input data when the 1-side input data is not inverted by the inversion control. When the output of 144 is “1”, the output of the flip-flop 142, that is, the output data for the 4-side input data when the 1-side input data is inverted by the inversion control is selected.

  The selector 151 selects the output of the flip-flop 141 when the output of the comparison determination unit 144 is “0”, that is, the inversion signal for the 4 side input data when the 1 side input data is not inverted by the inversion control, and the comparison determination unit When the output of 144 is “1”, the output of the flip-flop 143, that is, the inverted signal for the 4-side input data when the 1-side input data is inverted by the inversion control is selected.

  As a result, four sets of time-series data are generated from the data generation unit, that is, one-side input data, two-side input data, three-side input data, and four-side input data are generated. DBI circuit 201 generates 2-side DQ and 2-side DBI, DBI circuit 202 generates 3-side DQ and 3-side DBI, and DBI circuit 203 generates 4-side DQ and 4-side DBI. By generating, data corresponding to the DBI method can be generated, so that a device having a DBI function can be tested.

  FIG. 7 is a configuration block diagram of another DBI generation unit, and the same reference numerals are given to portions common to FIG. The difference between the configurations of FIG. 7 and FIG. 4 is that the DBI circuit that generates the 2-side DQ is selected without generating the two 2-side DQs when the 1-side input data is inverted and not inverted. That is, the inversion control of the 2-side input data is performed by the later 2-side inversion signal.

  In FIG. 7, two data signals output from the data generator 22 are input to the 1 side input data terminal and the 2 side input data terminal, respectively, as in the embodiment of FIG. That is, “data n−1” (n is an even number of 2 or more) is input to the 1 side input data terminal, and “data n” is input to the 2 side input data terminal.

  The 2-side input data terminal is connected to one input terminal of the comparison determination unit 27, one input terminal of the comparison determination unit 28, and one input terminal of the exclusive OR circuit 38, respectively. The output terminal of the comparison determination unit 26 is connected to the other input terminal of the exclusive OR circuit 29, the control terminal of the selector 33, and the data input terminal of the flip-flop 35.

  An output terminal of the comparison determination unit 27 is connected to one input terminal of the selector 33, and an output terminal of the comparison determination unit 28 is connected to the other input terminal of the selector 33. The output terminal of the selector 33 is connected to the input terminal of the flip-flop 37 and the other input terminal of the exclusive OR circuit 38. The output terminal of the exclusive OR circuit 38 is connected to the input terminal of the flip-flop 36. The other connections are the same as in the embodiment of FIG.

  The inverter 25, the comparison determination unit 27, the comparison determination unit 28, the selector 33, the flip-flop 36, the flip-flop 37, and the exclusive OR circuit 38 constitute a DBI circuit 42.

  The operation of the embodiment shown in FIG. 7 will be described. Since the operation is almost the same as that of the embodiment shown in FIG. 4, only different portions will be described.

  The exclusive OR circuit 38 receives the output of the selector 33 and generates output data for the 2-side input data. That is, the exclusive OR circuit 38 inverts and outputs the 2-side input data when the output of the selector 33 is “1”, and outputs the 2-side input when the output of the selector 33 is “0”. The data is output as it is without being inverted.

  Then, a signal obtained by delaying the output of the exclusive OR circuit 38 by one flip-flop 36 by the flip-flop 36 becomes the 2-side output data (2-side DQ).

  As a result, two sets of time-series data are generated from the data generation unit 22, that is, one-side input data and two-side input data are generated, and one DBI circuit 40 of the DBI generation unit 23 generates one-side input data. And the DQ output of the other DBI circuit 42 are compared and determined to perform inversion control, and the other DBI circuit 42 of the DBI generating unit 23 outputs the 1 side input data and the 2 side input data, or the 1 side input data. By comparing and determining the inverted data and the 2-side input data, and selecting either one by the DBI output of the DBI circuit 40, the 2-side input data is inverted and output by this selected signal, and the DBI method is achieved. Since corresponding data can be generated, it becomes possible to test a device having a DBI function.

  In the embodiment shown in FIGS. 1 and 3, the pin electronics 61 is composed of the waveform shaping unit 7 and the expected value determination unit 8. However, this is not always necessary, and only the waveform shaping unit 7 is required depending on the pin. It is good.

  In the embodiments shown in FIGS. 4, 6, and 7, flip-flops are arranged in the circuit. However, this is not always necessary, and the number of flip-flops can be set as long as the timing is acceptable. You can reduce them or delete them all.

  Further, in each of the embodiments shown in FIGS. 1 to 7, each comparison / determination unit determines whether or not the number of changed bits is larger than half the bit width, but is not necessarily limited to half the bit width. The number of bits to be determined may be changed as appropriate.

  For example, in the case of a memory having a data width of 8 bits, it may be determined whether or not the number of changed bits is greater than 5 bits, or may be determined based on whether or not the number of changed bits is greater than 3 bits. .

1 is a configuration block diagram showing an embodiment of a memory test apparatus according to the present invention. It is a block diagram of the DBI generating unit. It is a block diagram which shows the other Example of the memory test apparatus which concerns on this invention. It is a block diagram of the DBI generating unit. It is a timing chart which shows operation | movement of a DBI production | generation part. It is a block diagram of the configuration of another DBI generator. It is a block diagram of the configuration of another DBI generator. It is a block diagram showing a conventional memory test apparatus. It is a block diagram of the configuration of a data input circuit and a data output circuit of a memory having a DBI function.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Sequence control part 2 Instruction memory 3 Address generation part 4,22 Data generation part 5 Control signal generation part 6,24 Pin output selection part 7 Waveform shaping part 8 Expected value determination part 9, 10, 12, 15, 16, 20, 21, 34 to 37, 106 to 112, 117 to 126, 131 to 143, 152 to 159 Flip-flop 11, 14, 19, 29 to 31, 38, 104, 105, 115, 116, 129, 130, 145 Exclusive OR circuit 13, 18, 26-28, 102, 103, 113, 114, 127, 128, 144 Comparison determination unit 17, 23 DBI generation unit 25, 101 Inverter 32, 33, 146-151 Selector 40, 41, 42 , 200 to 203 DBI circuit 50, 51 generator 60, 62, 63 pattern generator 61 pins Electronics 70, 71, 72 memory test apparatus 80 DUT
90 memory

Claims (2)

In a memory test apparatus that selects an address signal from an address generation unit, a data signal from a data generation unit, and a control signal from a control signal generation unit by a pin output selection unit,
Provided between the data generation unit and the pin output selection unit, the data signal is time-series divided into a set of two input data, and one side input data and 2 Side input data is input at the same time , and the inversion control of whether to invert each of the first side input data and the second side input data is performed. 2-side output data, the 1-side output data and the 2-side output data, a 1-side inversion signal and a 2-side inversion signal indicating whether the 1-side input data and the 2-side input data are inverted , respectively A DBI generation unit for outputting
This DBI generator is
1-side input data and 2-side output data output 1 cycle before are bit-compared, and based on the comparison result, the 1-side input data is inverted and 1-side output data and 1-side inverted signal are output. A side DBI circuit;
When the one-side input data does not invert, the two-side input data following the one-side input data in time series and the one-side input data are bit-compared, and the two-side input data is inverted based on the comparison result. When the 1-side input data is inverted, the data obtained by bit-inversion of the 1-side input data is bit-compared with the 2-side input data, and the 2-side input data is controlled to be inverted based on the comparison result. A 2-side DBI circuit that outputs 2-side output data and a 2-side inverted signal, and inputs the 2-side output data to the 1-side DBI circuit;
A memory test apparatus. In a memory test apparatus that selects an address signal from an address generation unit, a data signal from a data generation unit, and a control signal from a control signal generation unit by a pin output selection unit,
Provided between the data generation unit and the pin output selection unit, the data signal is time-series divided into n sets of input data (n is an integer of 3 or more), and the n sets of inputs 1-side input data through n-side input data are simultaneously input as data, and the inversion control of whether or not to invert each of the 1-side input data through n-side input data is performed, and the data resulting from this inversion control 1 side output data to n side output data, respectively, and 1 side output data to n side output data and 1 side inversion signal to indicate whether each of the 1 side input data to n side input data is inverted. a DBI generator for outputting an n-side inverted signal ;
The DBI generator includes a 1-side DBI circuit to an n-side DBI circuit as n DBI circuits corresponding to the 1-side input data to the n-side input data,
The 1-side DBI circuit performs bit comparison between the 1-side input data and the n-side output data output one cycle before, and controls the inversion of the 1-side input data based on the comparison result. Side inversion signal is output ,
When the 1-side input data is not inverted , the 2-side DBI circuit performs bit comparison between the 2-side input data that follows the 1-side input data in time series and the 1-side input data, and based on the comparison result, the 2 side DBI circuit When the side input data is inverted and when the one side input data is inverted, the bit side inversion of the data obtained by bit-inversion of the one side input data and the two side input data is performed, and the two side input is performed based on the comparison result. Invert data and output 2-side output data and 2-side inverted signal ,
The k-side DBI circuit (k is an integer not smaller than 3 and not larger than n) is the (k−1) -side output data when the k- side input data and the 1-side input data are not inverted when the 1-side input data is not inverted. And the k-side input data is inverted based on the comparison result. When the 1-side input data is inverted, the k-side input data and the 1-side input data are inverted (k -1) bit comparison with side output data and inversion control of the k side input data based on the comparison result to output k side output data and k side inversion signal ;
An n-side output data of an n-side DBI circuit is inputted to the 1-side DBI circuit .

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