JPS62241310A - Laminated chip inductor - Google Patents
Laminated chip inductorInfo
- Publication number
- JPS62241310A JPS62241310A JP8447886A JP8447886A JPS62241310A JP S62241310 A JPS62241310 A JP S62241310A JP 8447886 A JP8447886 A JP 8447886A JP 8447886 A JP8447886 A JP 8447886A JP S62241310 A JPS62241310 A JP S62241310A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- internal conductor
- electrode
- chip body
- external electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Coils Or Transformers For Communication (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は、内部導体の電極取出部と外部電極との接触面
積が増大するように改良した積層チップインダクタに関
する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a multilayer chip inductor that is improved so that the contact area between an electrode lead-out portion of an internal conductor and an external electrode is increased.
(従来の技術)
従来の積層チップインダクタの一例を第4図に示して説
明する。図例の積層チップインダクタは、はぼ長方体状
をしたセラミックなどからなるチップ本体11このチッ
プ本体lの長さ方向両端に電極取出部2a、2bが露出
するように該チップ本体lの内部に埋設された直線帯状
の内部導体2、および、この内部導体2の電極取出部2
a、2bに電気的に接続されかつチップ本体1の両端面
およびその周辺に被覆された外部電極3.4を具備して
いる。(Prior Art) An example of a conventional multilayer chip inductor is shown in FIG. 4 and will be described. The multilayer chip inductor shown in the figure has a chip body 11 made of ceramic or the like having a rectangular parallelepiped shape. A linear strip-shaped internal conductor 2 embedded in the inner conductor 2, and an electrode extraction portion 2 of this internal conductor 2.
The external electrode 3.4 is electrically connected to the terminals a and 2b and coated on both end surfaces of the chip body 1 and the periphery thereof.
この積層チップ・インダクタは、たとえば、内部導体2
の印刷されたフェライト生シートの上に別のフェライト
生シートを積層し、これを焼成してチップ本体lを形成
し、このチップ本体lの両端に銀ペースト等を焼き付け
て外部電極3,4を形成するなどの方法によって製造さ
れている。This multilayer chip inductor has, for example, an inner conductor 2
Another ferrite raw sheet is laminated on top of the printed ferrite raw sheet, and this is fired to form a chip body l, and external electrodes 3 and 4 are formed by baking silver paste or the like on both ends of this chip body l. It is manufactured by methods such as forming.
なお、このような直線帯状の内部導体2を備えているも
の以外に、たとえば、特開昭55−91103号公報に
開示されているように、内部導体2を螺旋状にしてコイ
ルを形成しているものもある。In addition to the linear band-shaped internal conductor 2, there is also a coil formed by forming the internal conductor 2 into a spiral shape, as disclosed in JP-A-55-91103, for example. There are some.
(発明が解決しようとする問題点)
このような従来の積層チップインダクタにおいては、内
部導体2の本体部分と、電極取出部2a。(Problems to be Solved by the Invention) In such a conventional multilayer chip inductor, the main body portion of the internal conductor 2 and the electrode extraction portion 2a.
2bとが均一な幅になっている。そこで、内部導体2の
幅が°デツプ本体部のそれと比較して小さい場合には、
t[g取出部2a、2bの露出部への外部電極3,4の
接触面積が小さいために、接続状態が不安定になり易い
。2b has a uniform width. Therefore, if the width of the internal conductor 2 is smaller than that of the depth body,
t[g Since the contact area of the external electrodes 3 and 4 to the exposed portions of the extraction portions 2a and 2b is small, the connection state tends to become unstable.
このように接続状態が不安定だと、直流抵抗の増大や断
線を引き起こすおそれがあり、製品としての信頼性の低
下を沼来する。If the connection state is unstable in this way, there is a risk of an increase in DC resistance or a disconnection, which will lead to a decrease in the reliability of the product.
本発明は、上記事情に鑑みてなされたものであって、内
部導体と外部電極との接触面積を増大し、曲記両各の接
続状態を安定にして、その信頼性の向上を図ることがで
きる積層チップインダクタを提供することを目的とする
。The present invention has been made in view of the above circumstances, and it is possible to increase the contact area between the internal conductor and the external electrode, stabilize the connection state between the two, and improve the reliability. The purpose is to provide a multilayer chip inductor that can
(問題点を解決するための手段)
本発明に係る積層チップインダクタは、その内部導体の
電極取出部が本体部の幅よりも大きくなっていて、チッ
プ本体からの露出面積が大きくなっている構成にした。(Means for Solving the Problems) The multilayer chip inductor according to the present invention has a configuration in which the electrode lead-out portion of the internal conductor is larger than the width of the main body, and the exposed area from the chip main body is large. I made it.
(作用)
内部導体の電極取出部の露出面積が大きいから、外部電
極との接触面積か増大する。(Function) Since the exposed area of the electrode extraction portion of the internal conductor is large, the contact area with the external electrode increases.
(実施例)
以下、図面を参照して本発明の各実施例について説明す
る。(Example) Hereinafter, each example of the present invention will be described with reference to the drawings.
実施例1
第1図に示す積層チップインダクタにおいて、符号10
は、例えばセラミックからなる絶縁性のチップ本体であ
る。チップ本体IOはほぼ長方体状に形成されている。Example 1 In the multilayer chip inductor shown in FIG.
is an insulating chip body made of ceramic, for example. The chip body IO is formed into a substantially rectangular parallelepiped shape.
チップ本体IOの内部には、直線帯状の内部導体20が
埋設されている。内部導体20の両端には、はぼT字状
の電極取出部21.22が形成されている。電極取出部
21.22の側面はチップ本体IOの長さ方向両端面に
それぞれ露出されている。本実施例においては、電極取
出部21.22の長さ方向がチップ本体IOの端面の幅
方向に平行になっている。A linear strip-shaped internal conductor 20 is buried inside the chip body IO. T-shaped electrode extraction portions 21 and 22 are formed at both ends of the internal conductor 20. The side surfaces of the electrode extraction portions 21 and 22 are exposed at both longitudinal end surfaces of the chip body IO, respectively. In this embodiment, the length direction of the electrode extraction portions 21.22 is parallel to the width direction of the end surface of the chip body IO.
そして、チップ本体10の長さ方向両端およびその周辺
には、例えば銀ペーストなどからなる一対の外部電極3
0.31が被覆されている。外部電極30.31は、内
部導体20の電極取出部21.22と電気的に接続され
ている。A pair of external electrodes 3 made of, for example, silver paste are provided at both lengthwise ends of the chip body 10 and around the edges.
0.31 is coated. The external electrode 30.31 is electrically connected to the electrode extraction portion 21.22 of the internal conductor 20.
実施例2−
第2図に示す積層チップインダクタは、内部導体20の
電極取出部21a、22aがチップ本体10の端面幅と
同一になっている点が前記実施例1と異なる。このため
、電極取出部21a、22aの肉厚分だけデツプ本体I
Oの両側面に露出しており、この点からも外部電極30
.31との接触面積が実施例1よりも増大しているので
ある。Example 2 - The multilayer chip inductor shown in FIG. 2 differs from Example 1 in that the electrode lead-out portions 21a and 22a of the internal conductor 20 have the same width as the end face of the chip body 10. For this reason, the depth body I
It is exposed on both sides of O, and from this point also the external electrode 30
.. 31 is larger than that in the first embodiment.
及襄乱灸
第3図に示す積層チップインダクタは、その電極取出部
21a、22bが実施例2と同様にチップ本体10の端
面幅と同一である上、さらにチップ本体lOの両側面に
回り込む折曲片23b、24bを備えている点が、実施
例2と異なる。このようにすると、実施例2よりもさら
に外部電極30.31との接触面積を増大できる効果が
ある。In the multilayer chip inductor shown in FIG. 3, the electrode lead-out portions 21a and 22b have the same width as the end face of the chip body 10 as in the second embodiment, and also have folding parts that wrap around both sides of the chip body 10. This embodiment differs from the second embodiment in that it includes curved pieces 23b and 24b. This has the effect of increasing the contact area with the external electrodes 30, 31 even more than in the second embodiment.
なお、本発明は、各実施例1.2および3のそれぞれに
示す内部導体20の電極取出部21,22.21a、2
2a、21b、22bに限定されないことは勿論、また
内部導体20が直線状のもの以外、例えば螺旋状のもの
でも適用できることは言うまでもない。Note that the present invention provides the electrode extraction portions 21, 22, 21a, 2 of the internal conductor 20 shown in each of Examples 1.2 and 3.
2a, 21b, and 22b, and it goes without saying that the inner conductor 20 may be in a shape other than a straight line, for example, in a spiral shape.
(発明の効果)
本発明においては、内部導体の電極取出部がチップ本体
から大きく露出しているから、外部TL極との接触面積
が従来よりも増大することになる。(Effects of the Invention) In the present invention, since the electrode extraction portion of the internal conductor is largely exposed from the chip body, the contact area with the external TL pole is increased compared to the conventional case.
これにより、本発明では電極取出部と外部電極との両者
の接触状態が安定になるから、直流抵抗が不要に増大す
ることがなくなるとともに、断線のおそれがなくなりそ
の結果として信頼性の向上が図れるという効果を奏する
。As a result, in the present invention, the contact state between both the electrode extraction part and the external electrode is stabilized, so that DC resistance does not increase unnecessarily, and there is no risk of wire breakage, resulting in improved reliability. This effect is achieved.
第1図ないし第3図は本発明の各実施例に係り、第1図
は実施例1の斜視図、第2図は実施例2の斜視図、第3
図は実施例3の斜視図である。
第4図は従来例の斜視図である。
IOはチップ本体、20は内部導体、21,22.21
a、22a、21b、22bは電極取出部、30.31
は外部電極。1 to 3 relate to each embodiment of the present invention, FIG. 1 is a perspective view of Embodiment 1, FIG. 2 is a perspective view of Embodiment 2, and FIG.
The figure is a perspective view of Example 3. FIG. 4 is a perspective view of a conventional example. IO is the chip body, 20 is the internal conductor, 21, 22.21
a, 22a, 21b, 22b are electrode extraction parts, 30.31
is an external electrode.
Claims (1)
部が該チップ本体の両端に露出された内部導体、および 前記チップ本体の両端およびその周辺に被覆されかつ前
記内部導体の電極取出部に電気的に接続された一対の外
部電極を備えた積層チップインダクタであって、 前記内部導体は、その本体部よりも電極取出部が幅広と
なっていて、電極取出部が前記チップ本体から大きく露
出していることを特徴とする積層チップインダクタ。(1) A chip body, an internal conductor buried inside the chip body and having electrode lead-out portions at both ends exposed at both ends of the chip body, and an internal conductor covered at both ends of the chip body and the periphery thereof. A multilayer chip inductor comprising a pair of external electrodes electrically connected to an electrode lead-out part of the inner conductor, wherein the electrode lead-out part of the internal conductor is wider than the main body part, and the electrode lead-out part is wider than the main body part. A multilayer chip inductor characterized by being largely exposed from the chip body.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8447886A JPS62241310A (en) | 1986-04-11 | 1986-04-11 | Laminated chip inductor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8447886A JPS62241310A (en) | 1986-04-11 | 1986-04-11 | Laminated chip inductor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS62241310A true JPS62241310A (en) | 1987-10-22 |
JPH0519968B2 JPH0519968B2 (en) | 1993-03-18 |
Family
ID=13831748
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8447886A Granted JPS62241310A (en) | 1986-04-11 | 1986-04-11 | Laminated chip inductor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62241310A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0855727A (en) * | 1994-08-12 | 1996-02-27 | Taiyo Yuden Co Ltd | Laminated electronic parts |
JP2011003761A (en) * | 2009-06-19 | 2011-01-06 | Yoshizumi Fukui | Winding integrated type molded coil, and method of manufacturing winding integrated type molded coil |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5591804A (en) * | 1978-12-29 | 1980-07-11 | Tdk Corp | Chip type inductor |
-
1986
- 1986-04-11 JP JP8447886A patent/JPS62241310A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5591804A (en) * | 1978-12-29 | 1980-07-11 | Tdk Corp | Chip type inductor |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0855727A (en) * | 1994-08-12 | 1996-02-27 | Taiyo Yuden Co Ltd | Laminated electronic parts |
JP2011003761A (en) * | 2009-06-19 | 2011-01-06 | Yoshizumi Fukui | Winding integrated type molded coil, and method of manufacturing winding integrated type molded coil |
JP4685952B2 (en) * | 2009-06-19 | 2011-05-18 | 義純 福井 | Winding integrated mold coil and method for manufacturing winding integrated mold coil |
Also Published As
Publication number | Publication date |
---|---|
JPH0519968B2 (en) | 1993-03-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |