JPS62237541A - Two-dimensional address generator - Google Patents

Abstract

PURPOSE:To shorten the interval of data accessing to a memory by generating two-dimensional addresses with use of two independent address counters. CONSTITUTION:When a memory access start instruction is outputted, an initial value is set up in a row address initial value register 5 and a column address initial value register 6 and a memory access word length is set up in a word length counter 8. Then, an address counter is enabled to count and driven in accordance with 4-row direction access or column direction access under the control by a mode register so as to increase or decrease its contents in accordance with count-up or count-down mode. The word length counter 8 also counts up its contents every generation of one address. When the counter 8 ends the counting corresponding to the generated addresses and a carry is inputted to a mode register 7, the generation of addresses is stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an address generation device for a data memory section in a signal processing device 1 that handles two-dimensional data such as one-image data, for example, a general-purpose image processing processor.

[Conventional technology]

Conventionally, the address of a memory device is determined by the central processing unit (hereinafter referred to as CPU).
It was calculated and generated by a general-purpose arithmetic unit such as Unit and Kanopu. FIG. 2 shows an example of a conventional address generation circuit. (9) is an address calculation circuit, which is included in a part of the CPU mentioned above. ALU: Arithmetic logic operation circuit.

It consists of registers, etc. 1 is a register that latches the address generated from the address calculation circuit (9), and 2 is a memory address manually input to the memory device.

Actually, according to the program, the address calculation circuit (9
), addresses are successively calculated, and the addresses thus generated are successively input to the memory via the address register α■. Normally, address calculation in a CPU or the like involves an arithmetic circuit such as an ALU, and thus requires a lock equal to the number of basic clocks. Therefore, even when several addresses are to be generated consecutively, it is impossible to generate them consecutively every basic clock, but only every few clocks.

[Problem that the invention seeks to solve]

In conventional address generators such as those mentioned above, as mentioned above, a basic clock is used to generate addresses.

It takes several clocks. The time required to generate an address is especially long in the case of an address for two-dimensional data such as two images. FIG. 3 is a diagram showing general addressing of image data of 4 points x 4 points, and the numbers indicate addresses. As you can see from this diagram, the addresses of adjacent horizontal data are consecutive, but the addresses of adjacent vertical data are discontinuous, and when accessing data consecutively in the vertical direction, horizontal Compared to the case of direction, it takes a long time to calculate the address. In image data processing, arithmetic operations are often performed in the vicinity of an image, and data access is often continuous vertically or horizontally. Therefore, it is necessary for two-dimensional data processing such as image processing. Address calculation takes a lot of time, so it is necessary to speed up the calculation section.

The problem is that the total processing time 1r,i is limited by the address calculation time, resulting in a -C limit.

This invention was made to solve these problems. It generates addresses for two-dimensional data such as one image at high speed, shortens the interval between data accesses to memory, and reduces overall processing time. The purpose is to shorten the

[Means for solving problems]

The address generator according to the present invention has two independent address counters for generating two-dimensional addresses, an address initial value register that can be set independently, and a carry money input for the word length counter and address counter. It is controlled by a mode register that controls modes such as start and stop of the counter, and enables high-speed two-dimensional data access.

[Effect]

In this invention, an independent two-dimensional address counter continuously generates two-dimensional data addresses, a column address (hereinafter referred to as ROW address) and a row address (hereinafter referred to as COLUMN address), separately for each basic clock. This enables high-speed access to memory data at arbitrary consecutive addresses from any point in the two-dimensional data.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention. tl, lFi, ROW memory address input to memory, (2) is COL 0MN memory address.

[1), at +21, ROW, COLUM
Although the types of N and addresses are divided into two-dimensional images, in actual hardware they are equivalent and may be handled in the same way. (3) is a ROW address counter that generates a ROW memory address, and similarly (4) is a COLU
COLUMN address counter for generating MN address, +51. (6+ respectively determine the initial value of the ROW address counter + 31. COLUMN address counter (4). ROW address initial value register, CO
This is the LUMN address initial value v register. +71 Fi
, the ROW address counter (3) and COLUMN
Start of address counter (4).

Mode register that controls mode ftj13 such as stop.

(8) counts the number of addresses generated and controls the mode register. It is a word length counter.

As mentioned above, the address counter consists of two independent address counters, ROW address counter (31, C
Since it is generated by the OL[3MN address counter (4), consecutive addresses can be output for each basic clock according to the operation of each counter. The addresses are arranged in increasing numbers, or.

The output will be continued in the direction in which the number decreases. The initial values of the two address counters are stored in two address initial value registers, namely, ROW address initial value register +51. COLUMN address initial value register (6)
Set by. That is, the two-dimensional coordinates of the memory at which access is to be started are set by the two address initial values 1/register. Count up, count/down, start, stop of the two address counters,
Mode control such as access direction is performed using the mode register (7),
and word length counter (8). The memory access procedure is as follows. Along with the memory access start command, the values of the two address initial value registers are sent to the two address counters, and the memory access word length is sent to the word length counter (8).
Load into. Next, the address counter is enabled to count, and the output of the address counter starts to increase or decrease depending on the mode of count-up or count-down. The word length counter also increments by 1 each time one address is generated. Address generation is started as described above, and when the word length counter (8) finishes counting the number of address generation words and a carry is input to the mode register (7), address generation is stopped. The direction of memory access, ie ROW direction or COLUMN direction, is also controlled by the mode control register (7).

In the case of access in the ROW direction, the address is moved in the ROW direction, and the address in the COLUMN direction is IROW.
It remains fixed until access ends. COLUMN
The address counter (4) is the ROW address counter (
The carry in 3) will cause a one-count amp or countdown. The logic is set so that the carry is output when the address counter value reaches the maximum address value. In the case of reverse access in the COLUMN direction, the ROW address counter +31. C.O.
The operation is exactly the same as the access in the ROW direction, only the operation of the LUMN address counter (4) is reversed.

〔Effect of the invention〕

As explained above, by providing a two-dimensional independent address counter, this invention enables two-dimensional addresses to be generated at high speed, which enables memory access in two dimensions, that is, in both the ROW direction and the COLUMN direction. The speed can be increased, and a two-dimensional data processing device 9, such as an image processing device, can be realized as a whole.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
The figure is a block diagram showing an example of a conventional address generation device, and FIG. 3 is a diagram showing general addressing of image data of 4 points x 4 points. In the figure, (1) is a ROW memory address, (2) is a C0LUbtN address, and (3) is a ROW address counter. (4) is COLUMN address counter, (5) is RO
W address initial (m register, (6) is COLUMN address initial value register, (7) is mode register, (
81 is a word length counter, (9) is an address calculation circuit, Ql is an address register, and circle is a memory address.

Claims (1)

[Claims] Two address counters, ROW address counter, and COLU to generate memory addresses two-dimensionally independently.
Controls loading of the count enable initial value of the MN address counter, each independent address initial value register that determines the initial values of the two address counters, the ROW address initial value register, the COLUMN address initial value register, and the two address counters. A two-dimensional address generation device comprising: a mode register for generating an address, a word length counter for counting the number of address generation words, that is, the number of data input/output words for the memory, and controlling start and stop of the two address counters.