JP2976418B2 - Pattern matching processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern matching process.
The device has a pattern matching calculation function
The present invention relates to a pattern matching processing system using a V-RAM (video RAM) device .

[0002]

2. Description of the Related Art When performing turn matching processing of two data, the amount of data processing that can be performed in one pattern matching is at most about 32 bits. Even if this processing is performed by software by a CPU such as a personal computer, Even if it is performed by hardware, the number of processing bits is also performed in units of about 32 bits.

[0003]

As described above, in the conventional pattern matching processing system, since the amount of bits that can be processed at a time is at most about 32 bits, it is extremely difficult to perform pattern matching processing on a large amount of data. It has the disadvantage of requiring a lot of time. Further, when the number of processing bits is increased, the circuit scale is increased in proportion to the number of bits, which is not practical in hardware and has a disadvantage that it is impractical.

[0004]

SUMMARY OF THE INVENTION An object of the present invention is to provide a pattern matching processing apparatus which can perform a large amount of pattern matching processing at once at a high speed by using a V-RAM device which can internally process a large amount of data at high speed. It is.

[0006]

A pattern matching processing device according to the present invention provides a memory cell array, a plurality of ports including registers for inputting and outputting data from and to the memory cell array, and selecting one of the ports in response to a port selection command. And a transfer gate that controls data transfer between the memory cell array, the port section, and the arithmetic circuit in accordance with an external input / output selection command. And stores first and second read data from the memory cell array in separate port portions, respectively, and inputs the first and second read data stored in the port portions to the arithmetic circuit, A matching operation is performed, and the pattern matching operation result data is derived to the outside through one port unit. A V-RAM device, counter means for counting the matching state of the pattern matching result data, and a memory of the V-RAM apparatus for controlling the arithmetic operation of the V-RAM apparatus to store the matching state by the counter means. And control means for controlling to store the data at a predetermined address of the cell array.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a V-RAM device according to an embodiment of the present invention. The memory cell array 1 has a V-RA
This is the basic memory of the M device. In this example, it is 4096 × 40
It is assumed that a 96-bit RAM is used. This RAM1
Is specified by the row decoder 2 and the column decoder 3
Is to be performed.

This V-RAM device is provided with an arithmetic circuit 4 in addition to the RAM 1, so that a 4096-bit parallel operation can be performed at high speed. The arithmetic function of the arithmetic circuit 4 is as shown in FIG. 2, and in FIG.
S2 indicates a set of each input bit to be operated, and generates a destination logic output of 16 items (No. 0 to No. 15) at high speed in accordance with an external 4-bit (0 to 3) operation select signal. . In addition, a bit shift function is provided, and a shift amount and a shift direction can be specified.

Further, an input / output port 6A for the RAM 1
6D are provided, and these ports 6A to 6D have a serial register configuration having a width of 4096 bits.

RAM 1, arithmetic circuit 4, port 6
A transfer gate 5 is provided between A to 6D, and the transfer gate 5 selectively controls an input / output relationship between the RAM 1, the arithmetic circuit 4, and the port units 6A to 6D.

In order to select one of the four port sections 6A to 6D, a port select signal is supplied from the outside, and the connection with the transfer gate 5 is alternatively selected according to the port select signal. The selector 7 that operates according to the port select signal determines which output of the port sections 6A to 6D is to be input to the arithmetic circuit 4.

An example of a pattern matching processing system using such a V-RAM device will be described with reference to the block diagram of FIG. The V-RAM 10 stores the V shown in FIG.
A RAM device, and the CPU 11 controls the entire pattern matching process. Under the control of the CPU 11, the pattern matching controller 13 actually controls the operation of the V-RAM 10.

The serial / parallel conversion circuit 12 responds to the clock by using the port 6 of the V-RAM 10 (ports 6A to 6D shown in FIG. 1).
) Is serial-to-parallel converted and supplied to the counter 14. The counter 14 counts the total number of bits “1” of the input data. The count result indicates the degree of matching of the pattern matching. The count result (matching result) via the data bus 15 is V. -Stored in a predetermined area in the RAM 10. still,
Reference numeral 16 denotes an address bus.

FIG. 4 shows an example of a memory map in the V-RAM 10. Input data to be subjected to pattern matching, dictionary data (# 1 to #n), and a matching result (#
1 to #n) are respectively stored or can be stored.

In the pattern matching process, first, input data is read out, transferred to a port section 6A which is one of ports in the V-RAM 10, and held. Next, for the pattern matching controller 13, the V-RAM
When a command is issued to perform matching of dictionary data # 1 to #n in the matching controller 13, the matching controller 13
The dictionary data # 1 in the AM 10 is transferred to the port 6B, which is one of the ports.

The arithmetic circuit 4 performs a pattern matching operation using the data of the ports 6A and 6B as inputs S1 and S2. The type of the pattern matching calculation is determined by an instruction from the pattern matching controller 13. At this time, the arithmetic circuit 4 can execute the operation of 4096 bits at a time, and the processing is performed at high speed.

After the pattern matching, the matching result data is input to the serial / parallel conversion unit 12 via the port unit 6A, and is supplied to the counter 14 as serial data in synchronization with the clock. The counter 14 counts the degree of pattern matching, counts the number of bits “1”, and outputs the result to the V-RAM 10.
Is stored in the matching result # 1.

The above operation is sequentially performed on the dictionary data # 2 to #n, and when all the processes are completed, the V-R
If the matching results # 1 to #n stored in the AM 10 are sorted, all the pattern matching processes of the dictionaries # 1 to #n are completed.

In the above embodiment, the number of bits that can be matched at one time is 4096, but the number is not limited to this. The number of ports may be two or more.

[0022]

As described above, according to the present invention, V-RA
Since a multi-bit operation circuit, a transfer circuit (transfer gate) and a plurality of ports for temporarily storing the operation results and the like are provided inside M, multi-bit operations can be performed at once in the V-RAM at high speed. The effect is that it can be executed.

This is particularly effective when a large amount of data needs to be processed at high speed as in the case of a pattern matching process, and is effective only in the V-RAM incorporated in one IC.
Since a large amount of data is exchanged, there is no need to transfer data between ICs. This has the effect of significantly improving the speed and reducing the circuit scale.

[Brief description of the drawings]

FIG. 1 is a block diagram of a V-RAM device according to an embodiment of the present invention.

FIG. 2 is a diagram showing types of operations of the operation circuit of FIG. 1;

FIG. 3 is a block diagram illustrating a pattern matching processing system according to an embodiment of the present invention.

FIG. 4 is a diagram showing an example of a memory map in a V-RAM.

[Explanation of symbols]

 Reference Signs List 1 memory cell array (RAM) 2 row decoder 3 column decoder 4 operation circuit 5 transfer gate 6A to 6D port unit 7 selector 10 V-RAM 11 CPU 12 serial-parallel conversion circuit 13 pattern matching controller 14 counter

Claims (1)

(57) [Claims] 1. A memory cell array, comprising : a memory cell array;
Array consisting of registers for inputting and outputting
Several port sections and the port sections respond to a port selection command.
Selector that selects one by one and pattern matching
An arithmetic circuit having an arithmetic function, the memory cell array,
Transfer of data between the port unit and the arithmetic circuit;
Transfer game controlled according to external input / output selection command
And the first and second signals from the memory cell array.
The read data is stored in separate port sections, and
The first and second read data stored in the
Input to the arithmetic circuit to perform the pattern matching operation.
The pattern matching calculation result data of
V-RAM configured to be led out through one
Device and the matching state of the pattern matching result data
Counter means for counting, and counting while controlling arithmetic operation of the V-RAM device.
The matching status of the V-RAM device is
Control to store at a predetermined address in the memory cell array
A pattern matching processing device comprising: a control unit .