JPS62232620A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To decrease the number of signals for driving an LCD, to make an LSI small in size, and to realize the cost-down caused thereby, by adopting a 1/4 duty binary driving system. CONSTITUTION:Such a liquid crystal display device is driven by 1/4 duty and a binary voltage, and constituted so that a voltage whose effective value is [3/(n+1)]<1/2>, and a voltage whose effective value is [1/(n+1)]<1/2>.E are applied at the time of ON and at the time of OFF, respectively, when an effective value of a driving voltage is E. Also, a ratio of VON/VOFF of the effective value is set to >=1.7, and moreover, a 1/4 duty binary driving system is adopted. In such a way, a boosting circuit is made unnecessary since the device is operated by a single power source, the circuit constitution is simplified, a capacitor for the boosting circuit also is made unnecessary, the number of parts can be decreased, and also, a chip size of an LSI can be made small in size, and the cost-down caused thereby can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a liquid crystal display device used in a display unit of a desktop electronic calculator (hereinafter referred to as a calculator).

[Prior art]

Conventionally, in order to duty drive (Duty Dr, i ve ) a liquid crystal display device (hereinafter referred to as LCD), it is necessary to apply a bias voltage in order to obtain correct effective ON/OFF values. At this time, in addition to the power supply voltage, one or more intermediate level voltages are required, and at least three or more values are required. For example, in the case of a battery-powered calculator, a 1/3 duty (D
uty)・1/3 bias (Bias), or 1/4
Duty/1/3 bias. 1 mentioned above
The /3 duty/1/3 bias is driven by a signal with the waveform shown in FIG. 7, and if E=1.5V, the voN/voFF ratio αc, α=, /T−==
1.73,! : It has become. In addition, a solar-powered calculator (
In the case of the SB calculator (hereinafter referred to as the SB calculator), the voltage from the solar cell, this voltage, and the voltage obtained by doubling this voltage in an external pressure circuit are combined to make a 3-value (1-value intermediate level voltage) 1/3 duty calculator.・It was driven by 1/2 bias.

In the case of a battery-powered calculator, the current is small because the intermediate level voltage is divided by a reader resistor. However, SB calculators handle values where the set current is less than 1/2 to 1/3 of the reader current in battery-powered models, so
A method of obtaining an intermediate level voltage using a leader resistor cannot be adopted. Therefore, the power supply has been formed using an external voltage circuit with two capacitors mounted outside the LSI.

However, the above structure has disadvantages in that the number of components increases due to the step-up circuit, and the circuit configuration becomes complicated.

On the other hand, L
Conventionally, there is a method called a pulse control method to drive a CD on a binary basis, that is, on a duty basis with a single power supply. It was to be done. In the 1/2 duty pulse shown in FIG. 8, the H waveform shown in FIG. 8(a) is high.

is the selected section, h2 is the half-selected section, and H2 shown in (b) of the same figure
In the waveform, h2 is a selected section and hl is a half-selected section. The waveform in which a voltage is applied in each selected section takes an effective value of ON at the common, and conversely, the waveform in which no voltage is applied takes an effective value of OFF.

That is, E = 1.5 V torque, VON = J
T77・E=1.3V, voFp= JEZT-E=0
．． The voltage becomes 75V, and the VON/VOFF ratio α is α=J
D' = 1.73. On the other hand, 1/3 duty pulse y and te shown in FIG. 9 are VoN=1.22V and VoFF=
It becomes 0.87V, and α=1.41. Although it is possible to create a waveform with a 1/4 duty using a similar concept, α becomes a small value of 1.29. The larger α is, the better the contrast of the LCD will be, and calculators usually use a method in which α is 1.73 or more.

By the way, the larger the denominator of the LCD drive duty number, the larger the value, 1/3 than 1/2, and 1/3 than 1/3.
/4 allows the same LCD element to be driven with a smaller number of signals, and if the same display quality is obtained, it is desirable to drive with more duty.

However, in the above conventional structure, when using a pulse-driven liquid crystal display device in a calculator, the limit is 1/2 duty when considering the value of α, and 1/3 duty is a limit for display quality, that is, contrast. I couldn't hire him because of the points.

On the other hand, the 1/3 duty/1/2 Pierne system is most commonly used to drive LCDs in SB calculators, and for example, there are 27 signals in total to drive an 8-digit LCD. On the other hand, a 1/2 duty pulse requires 36 or more, leading to an increase in the chip size of the LSI and an increase in the number of pins in the package, resulting in an increase in costs.

[Purpose of the invention]

The present invention has been made in consideration of the above conventional problems, and by adopting a 1/4 duty binary drive system, it is possible to reduce the number of signals for driving the LCD. The object of the present invention is to provide a liquid crystal display device that can reduce the size of an LSI and reduce costs accordingly.

[Structure of the invention]

In order to achieve the above object, the liquid crystal display device of the present invention is a liquid crystal display device driven with a 1/4 duty and binary voltage, and has a configuration in which the actual driving voltage is applied,
Effective value V. The purpose is to set the N/VOFF ratio to 1.7 or more and to reduce costs.

[Example] An example of the present invention will be described below based on FIGS. 1 to 12.

As shown in FIG. 1, the liquid crystal display device according to the present invention includes:
/4 duty binary drive system. That is, a clock generator 1 shown in FIG. 1(a), a divider 2 that divides the original oscillation frequency to a frequency φf to create a display signal, and a ring counter that creates timing signals hl to h5 shown in FIG. 4(b). 3. At least 11 types of segment shift registers 6a and segment buffers each consisting of a common driver 4, a data address decoder 5a, and a main ROM 5b, which are common signal generating means for creating at least four types of common waveforms H1 to H4. Chi 6b
A segment shift register latch 6 consisting of a segment driver and a segment driver 7 which is a segment signal driver.
It consists of The ring counter 3 is connected to the common driver 4 via the T-flip-flop 8, and further connected to the segment shift register latch 6 via the T-flip-flop 8 and exclusive OR 9. . In addition, ROM5 is the exclusive OR
It is connected to the segment shift register/latch 6 via 9.

In the above configuration, the operation of the present liquid crystal display device will be explained using the time charts of FIGS. 2 and 3. From the clock generator 1, as shown in FIGS. 3(a) and (b), φ, ・
Since the signal of φ2 is output, the output φf of the divider 2 shown in FIG. 2(a) is synchronized with φ2 because it is a frequency division of φ2. Therefore, h shown in FIG. 2(b) to (f)
t xlls and H+ to H4 shown in (h) to (k) in the same figure.
All are also φ2 synchronized. Ring counter 3 is φf
The waveform hl-h5 is created using the clock as the clock. FR shown in the same figure is a signal used to perform frame-by-frame inversion, and is inverted at the falling edge of hl. The signals H1 to H4 are EX-OR signals of h2 to h5 and FR. ROM5 is for generating segment signals, and uses 5 bits of DP and X4 to is 10
9) as the address, and performs the operations shown in the truth table in Table 1 below.

x4~X and DP are signals from a data register (not shown), and their contents, ai/bi, and h1~h
The Q of the ROM 5 output can be obtained by the timing of 5.

For example, as shown in Figure 3, at the timing of hl,
First, the signal al is decoded at φW in FIG. 10D when ai/bi=1 (ai timing) shown in FIG. At this time, if the display content of the first digit (al * J) is, for example, 8, then from Table 1 above, X1n
=8, DP=0. Since ROM5 of al-hl is 0, Q=0. When FR=0, 0 is input to the beginning (left end) of the segment shift register 6a.

The next timing is ai/bi=0(bi), X1n=
8. DPPO2h, so from Table 1, Q=1, and 1 is input to the beginning of the segment shift register 6a at φW, and the segment shift register 6
The contents of a are shifted one bit to the right. Next, if the display content of the second digit is 2, ai/bi=1°X1
n=2. DP=1+hl and Q=O, ai/bi=0,
X1=2. DP=1. Q=O at hI, the following eight digits and symbol digit 8 are decoded, and all 17 bits of the segment shift register 6a are filled.

Next, the signal φT shown in FIG. 2(1) is a signal that appears at the falling edge, and provides timing for transferring the contents of the segment shift register 6a to the segment latch 6b in parallel. h! The 17-bit data decoded in time is transferred to the segment latch 6b when the falling edge of h is the φ1 pulse, and the segment driver 7
It passes through the buffer and is output from the aI-b and xS terminals.

Although the timing after the transfer by φT is h2 time, the content of the display signal output from the terminal is hl. This timing shift caused by the segment shift register 6a and the segment latch 6b is caused by the common driver 4.
, h2 is HI* h3 is H2, ha is I(,,h
It is corrected by setting 5 to H4. At time h2, decoding according to X + n + D P +ai/bi and h2 is performed, input to the segment shift register 6a, and transferred to the segment latch 6b at the falling edge of h2 at φT for display. be done. Thereafter, decoding is performed in the same manner up to the timing h5, and the process returns to the timing ri and ri. This operation is performed in exactly the same way up to the output Q of the ROM5, but after that, the FR signal becomes 1 and the inverted signal of Q is sent to the segment shift register 6.
It will be input to a. Xin and DP in FIG. 3(i) represent the timing of data switching and are synchronized with φ2. The shift pulse of the segment shift register 6a is φW, and siping is performed at the timing of φl. Also, the contents of the display data register, that is, the values of Xin and DP are, for example, 64512.8.
The output waveform of Q (timing of b+) when
Shown in j). Note that the terminal S is used to light up symbol digits other than the Japanese character segment, and can be used within the range of combinations shown in the segment waveform diagram of FIG. 3.

The liquid crystal display device described above has the following features compared to the conventional liquid crystal display device.

(1) The drive waveform of this device is the same as shown in Figure 4, but it is similar to the pulse drive shown in Figure 8 above.
- There is no part added to h2 other than the timing, so that each effective value can be obtained throughout one frame. Furthermore, despite the 1/4 duty, the timing is 5 bits, as shown in Figure 4(a).
The part represented by T plays an important role as a correction interval for obtaining a correct effective value.

(2) From FIG. 4, the effective value of the drive waveform is voN=1-7'-E=1.16V, assuming E=1.5.

Vopp=7"7"-E=0.67v, ss diagram.

This value is about 10% smaller than that of pulse driving.

If this is taken into consideration when selecting the LCD's VTH, the zero-order
”ON/Vopp ratio atti, ct = J'r
= 1.73, which is 1.7 which is equivalent to the above pulse drive.
3 is guaranteed.

(3) Since the duty is 1/4, the number of drive signals is 21 for an 8-digit calculator, which is 15 fewer than the 1/2 duty pulse, and is less than 60%. As a result, the number of pads on an LSI chip can be reduced to
This makes it possible to reduce the size of the equipment to which it is applied. Further, by reducing the number of pins of the package, it is possible to reduce the cost of the LSI. moreover,? The common driver 4 shown in FIG. JS1 has a greatly simplified configuration compared to, for example, the conventional 1/4 duty/1/3 bias common wave generation circuit shown in FIG.

(4) The 1/4 duty binary drive system of this device is further modified in the following 9th order to correspond to the Japanese character pattern. As can be seen from the waveforms shown in Figure 4, in this method, all of the 16 possible patterns of ON/OFF combinations for H1 to H1 do not exist, and any one of H1 to H4 is ON. the other three are OFF
There are only 12 patterns, excluding the four patterns.

On the other hand, when the Japanese character segment represents 0 to 9 (including ・), the ON/OFF combination pattern is 7A11
In the conventional 1/4 duty segment wiring method shown in the figure, there are only 911 types shown in Tables 4 and 5 below. However, the pattern in Table 5 has (1000
), which is not shown in Figure 4, cannot be used as is. Therefore, we studied the Japanese character segment pattern and changed it to the combination of the 5th character. The combination patterns at this time are as shown in @Table 2 and Table 3. The patterns in Table 3 can be displayed because they are all included in the patterns in FIG. X in ai-H4 in Table 4 and ai-H3 in Table 5 represents 1 or O, meaning that there are both cases with a decimal point and cases without a decimal point.

(5) As with this device, the number of LCD drive signals is reduced and the number of package pins is reduced, which is especially true for film carriers (TAB: Tape Automa).
When manufacturing LSI packages using ted bonding, it is possible to improve the terminal arrangement, which is effective in reducing the number of pitches in the film and, in turn, reducing material costs. FIG. 12 shows an example of the arrangement of a conventional LILEM carrier LSI. Terminal 20 for LCD and KEY is
They are arranged parallel to each other in the longitudinal direction of the tape 21, and the LSI
is always the width of tape 21 (actually, the width of sprocket 2
2) was determined by the effective width W) excluding... The length of one LSI 23 is determined by increasing or decreasing the number of pitches, that is, the number of sprockets 22, depending on the number of terminals 20, . The number of terminals 20 that can be installed in one pitch is roughly determined by the accuracy of mounting, but for example, if the terminal pitch is 0.9 n as shown in Figure 12, 31 terminals 20 are lined up. For this purpose, 27.9 silks are required and 6 pitches are required. On the other hand, the number of terminals of this device is 26 as shown in Figure @6, so 23.4ff is required. This corresponds to 5 pitches, but the effective length of the tape 21 in the width direction is 25 pitches.
．． 11, it is possible to line up the terminals 20 in the width direction. In the tape 21 shown in FIG. 12, the power supply terminals and component mounting pads are arranged in the width direction, and there was a margin in this area, but in FIG. It is possible that it will be packed up to. Therefore, the number of film pitches can be halved compared to 5 pitches in the conventional structure, resulting in significant material savings and cost reductions.

[Effects of the Invention] Since the liquid crystal driving device of the present invention has a liquid crystal display bag driven with a 1/n duty and a binary voltage as described above, it can exhibit the following effects.

(1) Operation with a single power supply eliminates the need for a booster circuit, simplifying the circuit configuration. Therefore, there is no need for a capacitor in the external pressure circuit, the number of parts can be reduced, and the chip size of the LSI can be reduced and the cost can be reduced accordingly.

(2) Compared to conventional devices, fewer LCD drive terminals are required, and the LSI package can be made smaller. This makes it possible to reduce the cost of LSI and downsize the device.

(3) Since an external pressure circuit is not required, the driving voltage can be lowered, and the power consumed by the LSI and LCD is reduced. Therefore, it is possible to reduce the size and cost of the power supply device.

[Brief explanation of drawings]

1 to 6 show an embodiment of the present invention, in which V(a) and (b) are circuit diagrams of a liquid crystal display device, and FIG. 2 is a circuit diagram of a liquid crystal display device, and FIG. and a timing chart showing the output signals of the ring counter; @3 is a timing chart showing the signals of the clock generator, ROM, and segment shift register/latch shown in FIG. 1; 44th (a) and (b) and (C) are timing charts showing examples of common waveforms, segment waveforms, and applied voltage waveforms, Fig. 5 is a wiring diagram of a 1/4 duty segment pattern, and Fig. 6 shows the configuration of the liquid crystal display device on the tape. The explanatory diagrams shown in FIGS. 7 to 12 show conventional examples, and (a), (b), and (c) in FIG.
8 is a timing chart showing examples of common waveforms, segment waveforms, and applied voltage waveforms in the 1/3 duty/1/3 bias driving method, and FIG. 8 is a timing chart showing drive signals in the 1/2 duty pulse driving method. Figure 9 is a timing chart showing drive signals in the 1/3 duty pulse drive system, Figures 10 (a) and (b).
), (c) is the circuit diagram of the 1/4 y' unique/1/3 bias common waveform generation circuit, Figure 11 is the wiring diagram of the 1/4 duty segment pattern, and Figure 12 is the liquid crystal display on the tape. FIG. 2 is an explanatory diagram showing the configuration of the device. 1 is a clock generator, 2 is a divider, 3 is a ring counter, 4 is a common driver, 5 is a ROM, 5a is a data address decoder, 5b is a main ROM, 6 is a shift register/lunch for segments, 6 is a shift register for alri segments, 6b is the segment lunch, 7
is a segment driver. Agent Patent attorney Takeshi Sugiyama (and 1 other person) Figure 2 is) φ□ Figure 3 (h) hsn timing h117I ink (Xin (Op) = 64512-8 / l ink)
Figure 4 (a) Figure 4 (.) 0011-1---F-101o1-ro]--f sea olto'g5Figure 0111
-shi-]1"-ichishi1110 -m-"-1-bottom-1111-shi-m-"- Figure 6'$7Figure (a) Figure 7 (b) T
<c hunn) d*j:
011) Figure 8 (() Seg(01) IE(d)H'''
″5e91-I- (OFF) Figure 9 (b) H2, w IE (c)
H co-3-2L-■-]-(d) S
eg(O1]) -ri1111(9) t-t, -5e9 thousand aim%咄17 (ON) (a) Figure 10 α) (K) 11th
figure? 2′p! J12 figure chief [ 1■

Claims (1)

[Claims] A liquid crystal display device that is driven with a 1, 1/n duty and a binary voltage, and when the effective value of the driving voltage is E, the voltage of the effective value [√3/(n+1)]·E when turned on. of,
A liquid crystal display device comprising means for applying a voltage of an effective value [√1/(n+1)]·E when turned off.