JPS62231516A - Input signal converter - Google Patents

Abstract

PURPOSE:To improve the noise margin of a signal source against an input signal without incurring the deterioration of the response by providing at least one of an input signal offset circuit and a reference voltage offset circuit to a comparator circuit in a signal converter converting the input signal from the signal source into a binary signal. CONSTITUTION:When the input signal from the signal source exceeds a reference voltage, the input signal is offset relatively to the reference voltage by an input signal offset circuit M2 by a sawtooth voltage decreased gradually higher to the reference voltage and/or when input signal from the signal source is lower than the reference voltage, the reference voltage is offset relatively higher by the reference voltage offset circuit M3 by the sawtooth voltage decreased gradually to the input signal. Thus, the comparator comparing the input signal and the reference voltage keeps a stable output according to the input signal of the signal source.

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention [Field of Industrial Application] The present invention relates to an input signal conversion device, and more particularly, to a signal source,
The present invention relates to an input signal conversion device used to detect an input signal from, for example, an electromagnetic pickup coil as a voltage signal.

[Prior Art] As an input signal converter for detecting a voltage signal of a signal source, for example, an electromagnetic pickup coil mounted on a vehicle, an input signal converter detects a sound signal superimposed on a signal line of an electromagnetic pickup coil, such as ignition noise or vibration noise of an internal combustion engine. , or a C-R type filter circuit that removes flux noise etc. and this C-R filter circuit.
A device is known that includes a comparator or the like that compares a voltage signal of an electromagnetic pickup coil whose waveform has been shaped by an R-type filter circuit with a predetermined reference voltage. However, the time constant of the C-R type filter circuit that removes noise signals superimposed on the signal line has problems such as detection responsiveness and cannot be increased unnecessarily just to remove noise signals. As a solution to this problem, the special public
580 "manual buffer circuit device" and the like have been proposed.

In this manual buffer circuit device, a predetermined pulse signal is applied to the comparator in accordance with the output signal of the comparator that compares the input signal and the reference voltage to increase the differential pressure between the input signal and the reference voltage, so-called hysteresis.

(Problems to be Solved by the Invention) Although the devices shown in the above human buffer circuit device have good detection response and strong noise resistance, they still have the following problems.

When a predetermined pulse signal is applied to the comparator according to the output signal of the comparator that compares the input signal and the reference voltage, the C-R type filter circuit becomes a differentiating circuit from the perspective of the side applying the pulse signal, so the pulse It was thought that the problem was that an undershoot necessarily occurs at the falling edge of the signal, causing the output of the comparator to output a low level when it should be a high level, causing the detection. The timing offset shown in FIG. 4 shows this state, and the input signal at the falling edge of the superimposed pulse signal causes undershoot. This causes the output signal to be erroneously detected.

The present invention has been made with the object of solving these problems and providing an input signal conversion device with good responsiveness and excellent noise resistance.

[Means for solving the problem] The input signal conversion device of the present invention, as illustrated in FIG. 1, compares an input signal from a signal source with a reference voltage having a predetermined noise margin. In an input signal converting device that converts an input signal from a signal source into a binary signal, the input signal converter includes a comparator circuit (Ml) that converts an input signal from a signal source into a binary signal, wherein when the input signal exceeds the reference voltage, the input signal is gradually reduced by a sawtooth wave voltage. An input signal offset circuit (M
2) and a reference voltage offset circuit (M3) that offsets the input signal relatively low by a sawtooth wave voltage that gradually decreases the reference voltage when the input signal falls below the reference voltage.
) and at least one of the following.

In Fig. 1, the switches 31 and 32 are exclusively turned on and off, and the resistor is used to generate a sawtooth voltage based on the sawtooth wave current from the constant current source. be.

Here, the input signal offset circuit (M2) means that when the input signal exceeds the reference voltage, the input signal is offset relatively higher by the sawtooth wave voltage that gradually decreases with respect to the reference voltage.
In other words, the circuit may be any circuit that superimposes a voltage that does not have a sharp fall relative to the reference voltage on the input signal, or may superimpose a gradually decreasing sawtooth wave voltage on the input signal, or , the reference voltage side may be lowered from the reference voltage by a gradually decreasing sawtooth voltage.

The reference voltage offset circuit (M3) is a sawtooth wave voltage that gradually decreases with respect to the input signal when the input signal becomes lower than the reference voltage. It is sufficient if the circuit superimposes a voltage that does not have a sharp fall relative to the input signal, it may superimpose a gradually decreasing sawtooth wave voltage on the reference voltage, or it may superimpose a voltage on the input signal side may be dropped from the input signal by a tapering sawtooth voltage.

The input signal offset circuit (M2) and the reference voltage offset circuit (M3) need only have a configuration in which the comparator circuit (Ml) includes at least one of them, or may have a configuration in which both of them are included.

[Function] The input signal conversion device of the present invention includes an input signal offset circuit (M2>) or a reference voltage offset circuit (M3).
Since at least one of the following is provided, the operation is as follows. That is, the input signal conversion device of the present invention includes an input signal offset circuit (
M2) offsets the input signal higher relative to the reference voltage by a gradually decreasing sawtooth voltage, and/or when the input signal from the signal source is below the reference voltage, the reference voltage offset 1 ~ circuit (M3) acts to offset the reference voltage relatively high by the sawtooth voltage valve which gradually decreases with respect to the input signal. Thereby, the comparator that compares the input signal with the reference voltage maintains a stable output according to the input signal of the signal source.

[Example] Next, embodiments of the present invention will be described in detail.

FIG. 2 is a circuit diagram showing an input signal conversion device according to an embodiment of the present invention.

The input signal conversion device of this embodiment which detects the input signal @Vin from the electromagnetic pickup coil L mainly includes a noise filter circuit 1. which removes noise from the input signal Vin. Compares input signal ■in with reference voltage and outputs comparison output signal vou
Comparison circuit that outputs t2. The offset circuit 3 supplies sawtooth waveform flows 1a and Ib whose slopes are proportional to the angular frequency of the electromagnetic pickup coil L to the comparator 2, respectively.

The noise filter circuit 1 includes resistors R1, R2 and a capacitor C1, and has a terminal Xa connected to both ends of an electromagnetic pickup coil L.

A resistor R1 and a capacitor C1 are connected in parallel to xb, and one end of the resistor R2 is connected to a terminal><a.

The comparison circuit 2 includes an operational amplifier OP1 as a comparator, input resistors R3 and R4, a voltage dividing resistor R5°R6 that generates a reference voltage vb for comparison, and an operational amplifier OP1.
Buffer circuit B buffers and outputs the output of 1.
F1 and two diodes Di, D2 and transistor T
It is composed of RI. Here, the diode Di,
D2 is a sawtooth wave type flow Ia from an offset circuit 3 which will be described later.
.

In order to supply Ib, their output sides are connected to the input negative side and the input negative side of the operational amplifier OPI, respectively. Further, the transistor TRI is used with its emitter grounded, and its collector is connected to the negative input side of the operational amplifier OP1, and the base is connected to the output side of the operational amplifier OP1. Therefore, the potential on the input side of the operational amplifier OPI is IQ? - When the output of the operational amplifier OPI becomes higher than the voltage vb and becomes a high level, the transistor TR1 turns on and works to lower the reference voltage Vb, that is, to provide hysteresis in the detection level of the signal from the electromagnetic pickup coil L. .

The offset circuit 3 includes resistors R7, R8, R9, transistors TR2, TR3, TR4, TR5, TR6, TR7.
, TR8, TR9, inverter circuit IN1. IN2. I
N3, content 1°C2, diode D3. D4. D
5. D6. D7. D8, operational amplifier OP2. OP3, a frequency-voltage converter FV that outputs a predetermined voltage VF according to the frequency of the comparison output signal yout output from the operational amplifier OP1 of the comparison circuit 2, a constant current source circuit C11, CI2 that generates a constant current according to the predetermined voltage VF, It consists of an analog switch As that is turned on when the output of the operational amplifier OP1 is at a low level. Of this offset circuit 3, operational amplifier OP2. OP3, diode D3. D4
．． D5. D6. D7. D8, resistor R9, capacitor C
2. Frequency-voltage converter FV, inverter circuit IN3,
Constant current source circuit C11, CI2 and analog switch AS
is the comparison output signal QVou output from the operational amplifier OP1
This constitutes a trapezoidal wave generation circuit 4 that generates a trapezoidal wave according to the frequency of t. Also, resistor R7, transistor T
R8 and TR9 are a sawtooth wave flow 1a output circuit 5 that supplies a sawtooth wave flow Ja that gradually decreases according to the trapezoidal wave generated by the trapezoidal wave generation circuit 4, and is also connected to a resistor R8 and a transistor TR.
3, TR4, TR5°TR6 is a sawtooth wave flow Ib output circuit 6 that supplies a sawtooth wave flow 1b that gradually decreases according to the trapezoidal wave. Further, the transistors TR2 and T'R7 constitute a so-called current switch 7. The connection relationship of the above offset circuit 3 is as follows.

First, the output side of the operational amplifier OPI of the comparator circuit 2 is connected to the inverter circuit IN2. IN3. It is connected to the frequency-voltage converter FV, and the output side of the inverter circuit IN2 is connected to the base of the transistor TR2 via the inverter circuit IN1.

The emitter of this transistor TR2 is grounded, and its collector is connected to the input side of the diode D2 of the comparator circuit 2. The output side of the inverter circuit 2 is also connected to the base of a transistor TR7 whose emitter is grounded, and the collector thereof is connected to the input side of the diode D1 of the comparison circuit 2. Further, the collectors of radiators 1 to TR2 and the collector of transistor TR3 are connected.

Further, the emitters and bases of transistors TR3 and TR4 are connected to each other. Further, the output side of the inverter circuit IN3 of the trapezoidal wave generating circuit 4 is connected to the gate of the analog switch AS.

The trapezoidal wave generating circuit 4 of the A offset circuit 3 has the following connection relationship.

Diode D8. D7. Resistor R9, diode D6.
D5 is connected in series between the power supply vCC and the ground GND, and is connected to two reference voltages. Generate vshi. The reference voltages VH and VL are connected to the input side of the operational amplifier OP3 and the input side of the operational amplifier OP2, respectively. As a result, the potential on the input brass side of the operational amplifier OP2 is changed to the potential of the diode D6. Forward voltage drop of D5 (
In this embodiment, the potential (hereinafter simply referred to as clamp low voltage) of approximately 1.2 V is maintained at V, and the potential on the input side of the operational amplifier OP3 is changed from the potential of the power supply ycc to the diode D8.
．． A potential (hereinafter simply referred to as a clamp high voltage) Vl-1 that is lower than the forward voltage drop of D7 (approximately 1°2 V)
is maintained. On the other hand, the output side of operational amplifier OP2 is
It is connected to the output side of the operational amplifier OP3 via diodes D3 and D4, and a connection point between the diodes D3 and D4 (hereinafter simply referred to as a connection point Xd) reaches the negative input side of the operational amplifiers OP2 and OR3. This diode D3 makes valid only the high level output of the operational amplifier OP2, and the diode D4 makes valid only the low level output of the operational amplifier OP2. In addition, the connection point xb is
It is connected to the output side of constant current source circuit CI2 and grounded via capacitor C2, and further connected to the input side of constant current source circuit CII via analog switch As. The constant current source circuits C11 and CI2 each output a predetermined constant current i and (k-1)Xi (k is a constant k>1) in accordance with a predetermined voltage VF output from the frequency-voltage converter FV. . As a result, the capacitor C2 starts charging when the output of the operational amplifier OP1 of the comparator circuit 2 becomes high level, and is discharged by the action of the analog switch AS when the output of the operational amplifier OP1 becomes low level. . As a result, the trapezoidal wave generating circuit 4 generates a trapezoidal wave having the same frequency as the frequency of the comparison output signal yout of the operational amplifier OP1, whose maximum value is the clamp high voltage VH and the minimum value is the clamp low voltage VL, to the connection point Xd. It causes it to occur.

The sawtooth wave type IA output circuit 5 has the following connection relationship.

The emitter of the transistor R8 is connected to the power supply Vcc through a resistor R7, its base reaches the emitter of the transistor 9, and its collector connects to the transistor TR7.
is connected to the collector.

Further, the base of the i-transistor TR9 and the connection point Xd of the trapezoidal wave generating circuit 4 are connected, and the collector of the transistor TR9 is grounded.

The sawtooth wave type 1b output circuit 6 has the following connection relationship.

Connection point Xd of trapezoidal wave generation circuit 4 and 1 to transistor TR6
The collector of the transistor TR6 reaches the emitter of the transistor TR4, and the emitter of the transistor TR6 is connected to the base of the transistor TR5. Further, the collector of the transistor TR5 and the base of the transistor TR4 are connected, and the emitter of the transistor TR5 is grounded via a resistor R8.

'The above sawtooth wave type Ja output circuit 5. A sawtooth current Ia generated by the sawtooth current Ib output circuit 6.

Ib is switched between transistors TR7 and TR2 and is supplied to the input positive side and negative side of the operational amplifier OPI of the comparison circuit 2, respectively.

The operation of the input signal converter of this embodiment having the configuration described in detail above will be explained with reference to the timing chart shown in FIG.

The input signal (which is the voltage generated by the electromagnetic pickup coil L)
FIG. 3 Timing Chart The input signal y in) vin is waveform-shaped by the noise filter circuit 1 and input to the input brass side of the operational amplifier OP1. Here, this operational amplifier OP
Let the potential on the input side of the operational amplifier OP1 be the input voltage Va, and let the potential on the negative side of the input of the operational amplifier OP1 be the reference voltage vb. Reference voltage Vb is determined by resistors R4, R5, R6, sawtooth current Ib and transistor TRI. now,
If input voltage ya < reference voltage vb, operational amplifier O
Since the output of P1 is low level, the transistor TR1
is in the off state. If the influence of the sawtooth waveform flow Ib is excluded at this time, the reference voltage vb becomes Vbh=[R5/(R5+R6)]xVcc. Here, when the input voltage va becomes a signal exceeding the reference voltage vbh, the output of the operational amplifier OP1 becomes high level, the transistor TRI is turned on, and the potential of the reference voltage vb falls to Vold.

Vbl=R6xRonxVcc/ [R5X (R4+
R6+ROn)+R6X (R4+ROn)] (However, R
(On is the on-resistance of the transistor TR1) On the other hand, the output of the operational amplifier OP1 goes high, and the base voltage of the transistor TR7 goes low by the inverter circuit IN2, turning it off. With the transistor TR7 turned off, the sawtooth wave current Ia begins to flow to the input side of the operational amplifier OP1. Therefore, the input voltage Va is Vah=Vin+Ia x (R2+R3). This sawtooth waveform flow Ha is set by the input signal guarantee circuit 3 as follows.

When the output of the operational amplifier OP1 becomes high level, the potential of the connection point Xd (hereinafter simply referred to as connection point voltage) Vd
is the sum of the base-emitter voltages vbe of transistors TR5 and TR6, 2xVbe (approximately 1.2V in this example)
is consistent with Further, this voltage 2 x 1be also coincides with the clamp low potential VL. In addition, in this example,
The base-emitter voltages Vbe of the transistors TR1 to TR9 are all the same (approximately 0.
6V).

From this state, the capacitor C2 starts charging with the constant current 1 supplied from the constant current source circuit CI2 (the analog switch As is turned off). Therefore, the connection point voltage Vd is expressed as Vd = 2xVbe+ i xt/C2 (
However, t represents time and C2 represents the capacitance of capacitor C2). As a result, the connection point voltage Vd increases with time, and its maximum value reaches the clamp high voltage VH (Fig. 2 timing diagram A-to connection point potential Vd).
. On the other hand, as the input voltage Va at the input image @vin becomes lower than the reference voltage Vl)1, the output of the operational amplifier OP1 becomes low level, the analog switch AS turns on, the capacitor C2 starts discharging, and the connection point voltage Vd decreases. It decreases with time t and finally reaches the clamp low/high voltage VL. As a result, the connection point voltage yd becomes a trapezoidal wave having the same period as the input signal Vin, as shown in the connection point voltage Vd in the timing chart of FIG.

This connection point voltage ■d, resistor R7, transistor TR8
, the sawtooth waveform flow Ia is determined by the base-emitter voltage Vbe of TR9, and can be expressed by the following equation.

Ia = (Vcc-Vd-2xVbe) /R7=
(Vcc-4xybe-ixt/C2>/R7=
(Vcc-4xVbe) /R7-i xt/C2XR
7 Also, the constant current i supplied from the constant current source circuit CI2 is
It is a current value proportional to the frequency of the comparison output signal Volt of the operational amplifier OP1, and in this embodiment, the comparison output signal @yo
Around ut! It is set so that the sawtooth wave flow Ia = O at about 1/2 of IT. As a result, from the moment the input voltage Vaffi, which is the input signal Vin, exceeds the standard voltage vbh, the voltage represented by fax (R2+R3) is further applied to the input voltage Va. Moreover, this sawtooth waveform flow ■a decreases with the slope of i/C2XR7, and the input image @
v! It has a frequency that becomes zero at the timing when n becomes lower than the reference voltage vb+ (Fig. 3 timing chart ψ
−1 to sawtooth current Ia).

Next, the sawtooth wave flow Ib will be explained.

When the input voltage Va becomes lower than the reference voltage ■b1,
The output of the operational amplifier OP1 becomes low level, the transistor TR1 turns off, and the transistor TR2
, R7 are turned off and on, respectively. As a result, the sawtooth waveform flow Ib begins to flow to the negative input side of the operational amplifier OP1. This sawtooth wave flow 1b, like the sawtooth wave flow Ha, has a connection point voltage Vd, a resistor R8, and a transistor TR5.
It can be expressed as the following equation with the base-emitter voltage Vbe of ゜TR6.

Ib = (Vd-2xVbe)/R8 Also, since the connection point voltage Vd is the potential of the capacitor C2 that is discharged from the clamped high voltage VH state (analog switch A
S on), constant current discharge of constant current source circuit C11 (k-1)
xi (where k is a constant k>1) is expressed by the following equation.

Vd = VH-(k-1) x i xt/C
2= (VCC-2XVbe) - (k-1) −
1) x i xt/C2. As a result, from the moment the input voltage Va becomes lower than the base QN pressure V, the reference voltage vb is changed to It)x [R4+
A voltage represented by R5XR6/(R5-1-R6)] is further applied. At this time, the reference voltage v
b can be expressed as b = R6xVcc/(R5+R6) 1 Ib X [R4+R5XR6/(R5+R6)]. This sawtooth wave flow 1b is (k-1>
It has a frequency that decreases with a slope of xi/C2 and becomes zero at the timing when the input signal ■in exceeds the reference voltage vbh (Figure 3 timing 11-to sawtooth wave current 1b)
.

When the voltages due to the sawtooth waveforms Ia and Ib described in detail are applied to the input signal vin and the reference voltage vb, respectively, that is, the output of the operational amplifier OPI as a comparator becomes high level (see Fig. 3 timing diagram comparison). Output signal vout
), voltage 1a x (R2+R3
) is superimposed on the input signal @Vink-, and the operational amplifier OP1
When the output becomes low level (timing chart comparison output signal Vout in FIG. 2), the voltage Ib x [R4+R5XR6/ (R5+R6
)] is superimposed on the reference voltage vbh.

According to the input signal conversion device of the present embodiment described in detail above, the input signal Vin of the operational amplifier OP1 as a comparator is
The noise margin for the input signal Vin is improved, and since each of the sawtooth wave flows 1a and Ib does not involve a sudden fall, no undershoot occurs in the input signal Vin. Therefore, the input signal conversion device can output a stable output signal yout to the output terminal XC based on the input signal Vin from the electromagnetic pickup coil L.

Effects of the Invention According to the input signal conversion device of the present invention, the noise margin for the input signal of the signal source is improved without causing a decrease in response, and since a gradually decreasing sawtooth wave voltage is used, the input signal is not undershot. It is possible to output a binary signal in accordance with the input signal from the signal source without having to do so.

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating the basic configuration of an input signal converter according to the present invention, FIG. 2 is a circuit diagram illustrating an input signal converter according to the present invention, and FIG. 3 is a block diagram showing various parts of the input signal converter according to the present invention. FIG. 4 is a graph showing the input signal and output signal when a predetermined pulse signal is superimposed on the input signal of the input signal converter. Ml... Comparison circuit M2... Input signal offset circuit M3... Reference voltage offset circuit L... Electromagnetic pickup coilt... Noise filter circuit 2... Comparison circuit 3... Offset circuit 4...・Trapezoidal wave generation circuit 5...Sawtooth wave current 1a output circuit 6...Sawtooth wave current lb output circuit 7...Current switch

Claims (1)

[Scope of Claims] An input signal conversion device that includes a comparison circuit that compares an input signal from a signal source with a reference voltage having a predetermined noise margin, and converts the input signal from the signal source into a binary signal, comprising: an input signal offset circuit that offsets the input signal relatively high with respect to the reference voltage by a sawtooth wave voltage that gradually decreases the input signal when the input signal exceeds the reference voltage; an input signal conversion device comprising at least one of the following: a reference voltage offset circuit that offsets the input signal relatively low by an amount of a sawtooth voltage that gradually reduces the reference voltage.