JPH09107255A - Input signal level adjustment circuit - Google Patents

Abstract

The present invention relates to an input signal level adjusting circuit for adjusting an output level according to the level of an input signal such as a microphone signal, and an object thereof is to easily reduce distortion of an output signal. A peak value of an output waveform from an amplifier 13 that amplifies an input signal is held by a capacitor C ₄ , and a transistor Q ₁ is operated when the level of the input signal is high based on the peak value to input the input signal. Attenuate the level of. In addition, for the transistor Q ₁ , the amplifier 1
A self-bias is supplied from the output side of 3 by a variable resistor VR and a capacitor C ₅ .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input signal level adjusting circuit for adjusting an output level according to the level of an input signal such as a microphone signal.

[0002]

2. Description of the Related Art When amplifying a microphone signal input by microphone recording or the like, a limiter circuit is added so that the input waveform is not clipped when the input signal is overlevel. In this case, it is necessary to remove signal distortion when the limiter is off.

FIG. 4 shows a conventional input signal level adjustment.
The circuit diagram of an adjustment circuit is shown. Input signal level adjustment shown in FIG.
The circuit 11 is connected from the input terminal 12 to which a signal is input.
Sensor C₁, Resistance R_Two, Capacitor C_TwoAmplifier 1 through
3 is connected to the non-inverting input terminal of the capacitor C₁And resistance R
₁Power supply + V at the connection point_DIs the resistance R_Two, R_ThreePartial pressure with
Voltage is resistance R_FourConnected to be applied via
You. Also, the resistance R₁And capacitor C_TwoFE at the connection point
T (field effect transistor) type transistor Q ₁The de
Rain is connected and the source is capacitor C_ThreeConnect through
Ground. This transistor Q₁Constitutes the limiter circuit
I do.

The non-inverting input terminal of the amplifier 13 has a resistor R._FiveThrough
And grounded, and the inverting input terminal has a resistor R ₆Is grounded through
You. The output terminal of this amplifier 13 is connected to the output terminal 14.
And the resistance R₇Connected to the inverting input via
You. In addition, the output from the amplifier 13 is a resistor R₈, Conden
Sa C_Three, Forward diode D₁, Resistance R₉Through
Transistor Q₁Connected to bias the gate of
The diode D₁Is the resistance R_TenConnect through
As the grounded, the cathode has a resistance R₁₁And capacitor C
_FourIs grounded through a parallel circuit.

Transistor Q₁The gate of the resistor R₁When
Capacitor C_TwoVariable resistor VR and capacitor C at the connection point of
_FiveForward diode D_Two
Limiter switch S via₁Connected to the common terminal of
You. This limiter switch S ₁ON terminal is opened,
OFF terminal is -V_DConnected to power supply. The limiter
Switch S₁Forward from other channels to the common terminal of
Diode D_ThreeConnected via

Therefore, FIG. 5 explains the input / output level of FIG.
A clear view is shown. Input signal level adjusting circuit 1 shown in FIG.
1 is the limiter switch S₁Is on and the resistance R
₈And resistance R_TenThe resistance value of R is₈≫R_TenThen,
The peak value of the output of pump 13 is resistance R_Two, R_ThreePartial voltage of
Value Vref (reference voltage value) and transistor Q₁The pinch of
Voltage V_PDifference (Vref-V_P) When it gets bigger
Transistor Q₁Starts operating and the input terminal 12
Even if the bell signal is input, as shown by the broken line in FIG.
The output of the pump 13 is not proportional to the input level and the resistance R₁When
Transistor Q ₁Compressed by attenuation by
Output level is output.

6 and 7 show waveform diagrams of the input / output characteristics of the limiter circuit of FIG. The reference voltage shown in FIG. 4 is Vref, and the pinch-off voltage of the transistor Q ₁ is Vref.
_{If P} (= V + ΔV _P (ΔV _P <0)) and the peak value of the output of the amplifier 13 is V _G0 (the gate voltage of the transistor Q ₁ when the ground potential is 0 V, Vref> V _G0 ), 6 transistors Q ₁ through V _G0 -I _D characteristic shown in (a) acts as an attenuator for the input signal, V _P <
At V _G0 , the resistance value decreases as V _G0 increases, and V _P
When ≧ V _G0 , the transistor Q ₁ is turned off.

[0008] In this case, those resistors R _8, R ₁₁ is to determine the time constant of the charging and discharging of the capacitor C _4, respectively, diodes D ₁ and capacitor C ₄ is the input signal as shown in FIG. 6 (B) + side Peak detection is performed only for half waves. The variable resistor VR and the capacitor C ₅ are for improving the distortion during the limiter operation (operation of turning on the transistor Q ₁ ).

That is, as shown in FIG. 7A, the reference voltage Vref is set to 0V, and the gate voltage is set to _VGS (= _VG0- V).
ref), the AC input signal V from the input terminal 12
_{When S} is input, the reference voltage Vref becomes the sum of the output voltage V _{0 of the} amplifier 13 and the AC input signal V _S, and accordingly the gate voltage V _GS of the transistor Q ₁ is centered around the operating point A. Amplitude in the ± direction, which results in a drain current I
_{The value at D} is also a value that is oscillated in the ± directions around the operating point A. Therefore, due to the non-linearity of the characteristic diagrams of FIGS. 7A and 6A, the amplitude a ₂ on the − side is compressed compared to the amplitude a ₁ on the + side, and the symmetry of the output waveform deteriorates. To do.

Therefore, the variable resistor VR and the capacitor C ₅
By applying a self-bias to the transistor Q ₁ according to the above, the operating point is changed according to the change in the AC input signal V _S , and the amplitudes a ₁ on the + side and − side are made the same as shown in FIG. 7B. It is possible to improve the symmetry of the output waveform.

[0011]

However, when the limiter switch S ₁ is in the off state, the transistor Q ₁ is in the off state, but the ripple in the capacitor C ₄ (see FIG. 6).
(B) is added to the capacitor C ₅ and the variable resistor VR via the resistor R ₉ and returns to the input side of the amplifier 13, so that it is difficult to reduce the ripple to zero in consideration of the recovery time and the like. . The variable resistor VR is high level of the input signal, capacitor C _5, causing distortion will be partially flows to -V _D power supply via the diode D ₂ and the switch S _1.

This distortion can be prevented by omitting the diode D ₂ (short-circuited state). However, when a single limiter switch S _{1 is used} for multichannel limiter operation, the diode D ₂ (D ₃ ) is required.
Further, although the distortion can be reduced to some extent by selecting a constant such as a resistance value, it is difficult to design because there are restrictions on the design of attack time, recovery time, etc. However, there is a problem that some distortion is likely to occur on the surface.

Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide an input signal level adjusting circuit that easily reduces distortion of an output signal.

[0014]

In order to solve the above-mentioned problems, in claim 1, an amplifying means for amplifying an input signal, a peak holding means for detecting and holding a peak value of the input signal, and a peak holding means. And a switching means for operating the peak value from the holding means as a control signal to attenuate the level of the input signal, and a self-biasing means for biasing the switching means based on the output signal from the amplifying means. An input signal level adjusting circuit is configured.

In the second aspect, the self-biasing means according to the first aspect makes the bias value variable according to the gain of the amplifying means. As described above, in the invention of claim 1, the switching means for attenuating the level of the input signal based on the peak value of the input signal is biased by the self-biasing means based on the output signal from the amplifying means. As a result, the ripple generated in the peak hold means is not input to the amplifying means, so that the distortion of the output signal from the amplifying means can be easily reduced.

According to the second aspect of the present invention, the bias applied to the switching means by the self-biasing means is variably set according to the gain of the amplifying means. As a result, the level of the input signal can be surely adjusted according to the gain of the amplification means, and the distortion of the output signal can be easily reduced.

[0017]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. FIG. 1 shows an input signal level adjusting circuit 21 according to the present invention. The same components as those in FIG. 4 are designated by the same reference numerals. The input signal level adjusting circuit 21 of FIG. 1 is an amplifier 1 which is an amplifying means from the input terminal 12 to which a signal is input via the capacitor C ₁ , the resistor R ₂ and the capacitor C _2.
3 is connected to the non-inverting input terminal, and has a capacitor C ₁ and a resistor R
The connection point ₁ is connected so that a voltage obtained by dividing the power source + V _D by the resistors R ₂ and R ₃ is applied via the resistor R ₄ .

Further, the drain of a FET (field effect transistor) type transistor Q ₁ which is a switching means is connected to the connection point of the resistor R ₁ and the capacitor C ₂ , and the source is grounded via the capacitor C ₃ . This transistor Q ₁ constitutes a limiter circuit.

The non-inverting input terminal of the amplifier 13 has a resistor R._FiveThrough
And grounded, and the inverting input terminal has a resistor R ₆Is grounded through
You. The output terminal of this amplifier 13 is connected to the output terminal 14.
And the resistance R₇Connected to the inverting input via
You. In addition, the output from the amplifier 13 is peak hold means.
Resistor R₈, Capacitor C_Three， Forward dio
Code D₁, Resistance R₉Through transistor Q₁Gate of
Connected to bias the diode D₁No
Node is resistance R_TenGrounded through and cathode
Is the resistance R₁₁And capacitor C_FourGrounded through the parallel circuit of
Is done.

Further, the output from the amplifier 13 is connected to bias the gate of the transistor Q ₁ through a variable resistor VR and a capacitor C ₅ which constitute a self-biasing means, and also through a diode D _{2 in the} forward direction. Connected to the common terminal of the limiter switch S ₁ . The ON terminal of the limiter switch S ₁ is opened and the OFF terminal is connected to the -V _D power supply. The limiter switch S ₁
Is connected to the common terminal of the other channel through a diode D _{3 in the} forward direction.

In such an input signal level adjusting circuit 21, as a premise, the resistors R ₈ and R ₁₀ are set to R as described above.
₈ >> R ₁₀ , and when the limiter switch S ₁ is on, the limiter operation by the transistor Q ₁ is possible. Therefore, a high level signal is input to the input terminal 12 and the reference voltage Vref generated by the resistors R ₂ and R ₃ is applied.
The difference in pinch-off voltage V _P of the transistor Q ₁ is then the transistor Q ₁ is operated when it is smaller than the peak value of the output of the amplifier 13 attenuates the level of the input signal and.

That is, the output signal of the amplifier 13 is a capacitor C ₄ (resistors R ₈ and R ₁₁ ), and the output signal from the diode D ₁ is +
Side half-wave peak value is held, and when it biases the gate of the transistor Q ₁ , when the difference between the reference voltage Vref and the pinch-off voltage V _P is smaller than the peak hold value, the transistor Q 1 is held. By performing the attenuation by _1, the level of the output signal from the amplifier 13 is compressed.

In this case, the amplitude of the reference level of the bias to the gate of the transistor Q ₁ (variation of operating points) is
Variable resistance VR (may be fixed resistance) and capacitor C
Adjustment can be made by self-biasing with ₅ , and the symmetry of the + and-side output waveforms can be minimized. In this sense, the same applies when the resistor R ₉ is a variable resistor. The self-bias is supplied from the output side of the amplifier 13, but the output impedance can be lowered by configuring the amplifier 13 with an operational amplifier, and the distortion of the output waveform can be reduced to a negligible level. . At this time, it is necessary to adjust the value based on the self-bias according to the gain of the amplifier 13. For example, when the gain is 1 or more, by adjusting the capacitance of the capacitor C _{5 and} the resistance value by the variable resistor VR, as described above. In addition, the distortion of the output waveform can be reduced to a negligible level and reduced.

On the other hand, when the limiter switch S ₁ is off, the gate of the transistor Q ₁ is a diode D ₂
The transistor Q ₁ in a state of being biased by -V _D power supply via the always turned off, the attenuation operation for the input signal is not performed. In this case, the peak value of the capacitor C ₅ by the output of the amplifier 13, a variable resistor VR for self-bias, the capacitor C ₅ is the amplifier 13
Since it is obtained from the output side of the above, it is not supplied to the input side of the amplifier 13 and the ripple of the output waveform can be prevented.

Even if a high-level input signal is input, the output impedance of the amplifier 13 is low,
Part of the current does not flow to the −V _D power supply, so that distortion can be prevented and distortion can be reduced as a whole. In this way, the distortion of the output waveform can be reduced easily and without cost by simply changing the wiring for supplying the resistor (VR) and the capacitor (C ₅ ) for self-bias from the output side of the amplifier 13. It can be done.

FIG. 2 shows a circuit diagram of the amplifier input circuit to which FIG. 1 is applied. The components corresponding to those in FIG. 1 are designated by the same reference numerals. The amplifier input circuit 31 shown in FIG. 2 is a circuit to which an input signal such as microphone recording in a digital audio device is supplied, and is a balanced output (for example, connected to a balanced amplifier via an A / D converter in the next stage). )belongs to.

In FIG. 2, an input terminal 12 (one of which is GN
D) is the capacitor C₁, Resistance R₁, Capacitor C_TwoThrough
And is connected to the non-inverting input terminal of the amplifier 13a. on the other hand,
+ V _D(Eg + 5V) to resistance R₂₀Through the resistor R_{twenty one}
And variable resistance R_{twenty two}(R_TwoEquivalent to) and resistance R_ThreePartial pressure by
Voltage (reference voltage) is resistance R₄₁, R₄₂(Resistance R_FourEquivalent to)
Resistor R so that it can be added to the input signal via₁And
Indexer C_TwoConnected to the connection point. Also, this connection point
Has a transistor Q₁The drain of the
Jista Q₁Source is grounded (GND). In addition,
Anti-R₄₁, R₄₂Is the connection point of capacitor C_ThreeGrounded through
It is.

The output terminal of the amplifier 13a is connected to the inverting input terminal via the parallel circuit of the resistor R ₇ and the capacitor C ₁₁ , and is also grounded via the resistor R ₆ and the capacitor C ₁₂ . The output terminal of the amplifier 13a is connected to the capacitor C.
It is grounded through _3a and resistor R _10a , and at the same time, resistor R
_It is connected to the inverting input terminal of the amplifier 13b via _100, and the other output terminal (output B) via the capacitor C _B.
14 _B is connected. The output terminal of the amplifier 13a is connected to the gate of the transistor Q ₁ via the capacitor C ₅ and the resistor R _VR (corresponding to the variable resistor VR in FIG. 1 and thus may be a variable resistor) so as to be self-biased. To be done.

The non-inverting terminal of the amplifier 13b is + V_DPower supply
From resistance R₂₀Through the resistor R₁₀₁, R₁₀₂(Resistance R₁₀₂
Has a capacitor C₁₆Is connected in parallel)
Are connected so as to be applied. This divided voltage is
Resistance R_FiveApplied to the non-inverting input terminal of the amplifier 13a via
Output terminal 14_A, 14 _B
Resistor R connected between₁₀₃, R₁₀₄Applied to the connection point of
To be connected. Also, the output end of the amplifier 13b is
Indexer C₁₃And resistance R₁₀₅Inverting input via parallel circuit
The capacitor C is connected to the end_AOne through the other
Output terminal 14_AConnected to. In addition, the + of the amplifier 13b
Power supply end (+ V_D) And-power supply terminal (GND)
Densa C₁₄, C_FifteenParallel circuit is interposed. Also, Ann
The output terminal of capacitor 13b is capacitor C_3bAnd resistance R_10bThrough
And grounded.

The capacitor C _3a on the output side of the amplifier 13a and the resistor R _10a are connected to the non-inverting input terminal of the amplifier 32 via the diode D _{1a in the} forward direction, and the capacitor C on the output side of the amplifier 13b. It is connected to the non-inverting input terminal of the amplifier 32 through the diode D _{1b in the} forward direction from the connection point of _3b and the resistor R _10b . In addition, amplifier 3
The non-inverting input terminal of 2 is grounded through a parallel circuit of a resistor R ₁₀₆ and a capacitor C ₁₇ . A capacitor C is provided between the + power supply terminal (+ V _D ) and the −power supply terminal (−V _D ) of the amplifier 32.
₁₈ are intervened.

The output terminal of the amplifier 32 is connected to its own inverting input terminal (just functions as an amplifier),
It is connected so as to bias the gate of the transistor Q ₁ through the diode D ₃ and the resistors R ₈ and R ₉ . The connection point of the resistors R ₈ and R ₉ is grounded via the parallel circuit of the capacitors C ₄ and C ₁₉ and the resistor R ₁₁ .

Further, the gate of the transistor Q ₁ is connected to the collector of the NPN type transistor Q ₂ via the diode D ₂ , and the emitter of the transistor Q ₂ is connected to the −V _D power source (for example, −5 V). To be done. The base of the transistor Q ₂ is intended to be connected to the + V _D supply via a resistor R ₁₀₇ and a limiter switch S _1, the limiter switch S ₁ is connected to the + V _D supply in the off state. The base of the transistor Q ₂ and -V _D
A parallel circuit of a resistor R ₁₀₈ and a capacitor C ₂₀ is interposed between the power supplies.

Such an amplifier input circuit 31 is configured to perform balanced output as compared with the circuit of FIG. 1, whereby peak output of both output waveforms is detected by the capacitor C ₄ , and good response is obtained. . Also, the amplifier 13
In order to reduce the influence on the output of a, an amplifier 32 is provided before the peak detection. The input of this amplifier 32 detects both waveforms of the balanced output by the diodes D _1a and D _1b.
Have gone through. Further, the limiter operation by the limiter switch S ₁ is performed via the transistor Q ₂ . Further, the reference voltage is adjusted by the resistor R ₂₂ to absorb the variation in the operating point of the transistor Q ₁ ,
In addition to having the role of the variable resistor VR shown in FIG.
The injection of the reference voltage to the transistor Q ₁ is performed by interposing a resistor R ₄₂ between the drain and the source to reduce the influence on the audio line.

In the amplifier input circuit 31, when the limiter switch S ₁ is on, the input terminal 12
Inputted input signal is output after being amplified by the amplifier 13a, which is inverted is balanced output from the output terminal 14 _A, 14 _B by the gain 1 by the amplifier 13b to. In this case, the amplifier 13b operates on a single power supply, and divides the reference voltage by the resistors R ₁₀₁ and R ₁₀₂ (for example, V _D / 2) and supplies it to the non-inverting input terminal.

The respective outputs from the amplifiers 13a and 13b
Power is capacitor C_3a, C_3bDC component is cut by
+ Side of input signal is diode D_1aRectified by
The diode D on the negative side_1bRectification is detected by. this
If the resistance R_10a, R_10bIs the capacitor C_3a, C_3bNegative
It becomes a load resistance, and by this, each amplifier 13a, 13b
The output signal is moved in ± directions around 0V.
You. The capacitor C ₁₇Has the detected distortion component
To prevent the influence on other circuits when the waveform to be
It becomes a kind of low-pass filter that
It plays the role of a condenser.

The waveforms detected by the diodes D _1a and D _1b are amplified by the amplifier 32, and the peaks are detected by the diode D ₃ and the capacitors C ₄ and C ₁₉ . Where resistance R
₈ determines the attack time (delay), and the resistor R ₁₁ determines the recovery (discharge). The peak waveform biases the transistor Q ₁ through the resistor R ₉ and operates when the peak value becomes higher than the pinch-off voltage. When the input signal is at a high level, the transistor Q ₁ operates to output the output terminal 14 _A , 14
_The output signal output from _B is compressed.

In this case, the output waveform of the amplifier 13a directly biases the transistor Q ₁ (self-bias) by the capacitor C _{5 for} removing the DC component and the resistor R _VR , and the bias amount is determined by the resistors R _VR and R _9. It is something. As a result, the non-linear distortion (waveform symmetry) of the transistor Q ₁ can be reduced.

On the other hand, when the limiter switch S ₁ is off, the transistor Q ₂ is on, the base of the transistor Q ₁ is -V _D (-5V), and the transistor Q ₁ is off. . At this time, amplifier 1
Since the resistor R _VR is connected to the output terminal of 3a, the output of the amplifier 13a (amplifier 13b) is the transistor Q.
It is not affected by the gate of ₁ .

In FIG. 2, the amplifier 32 (diode
Do D_Three) Is omitted, the diode D _1a, D_1bMore directly
Resistance R₈, R₉Through transistor Q₁Biased
You may. Next, FIG. 3 is a circuit diagram of another embodiment of the present invention.
Is shown. FIG. 3 shows the input signal level adjusting circuit 21.
Variable resistor for self-biasing shown in Fig. 1.
VR and capacitor C_FiveFrom the output end of the amplifier 13
Anti-R₇Connected to be supplied via
Other configurations are the same as those in FIG.

The input signal level adjusting circuit 2 shown in FIG.
1 is that the resistance R ₇ is R ₇ << VR, or the resistance R ₆ is R ₆
<< VR, the same as in FIG. 1 when the limiter switch S ₁ is in the ON state (limiter operating state), but when the limiter switch S ₁ is in the OFF state, the capacitor C ₄
Although the ripple due to is flowing to the input side of the amplifier 13, there is no practical problem, and the distortion of the output waveform of the amplifier 13 can be reduced to a negligible level. This utilizes the characteristics of the operational amplifier in the amplifier 13, and it is possible to prevent the amplifier 13 from being affected by setting the resistors R ₆ and R ₇ and the variable resistor VR.

[0041]

As described above, according to the first aspect of the present invention,
The switching means that attenuates the level of the input signal based on the peak value of the input signal is biased by the self-biasing means based on the output signal from the amplifying means, so that the ripple generated in the peak hold means is not input to the amplifying means. Therefore, the distortion of the output signal from the amplifier can be easily reduced.

According to the second aspect of the present invention, the bias to the switching means by the self-biasing means is variably set according to the gain of the amplifying means, so that the level of the input signal is surely changed according to the gain of the amplifying means. Adjustment becomes possible, and distortion of the output signal can be easily reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a circuit diagram of an amplifier input circuit to which FIG. 1 is applied.

FIG. 3 is a circuit diagram of another embodiment of the present invention.

FIG. 4 is a circuit diagram of a conventional input signal level adjusting circuit.

5 is an explanatory diagram of input / output levels in FIG.

6 is a waveform diagram (1) of input / output characteristics by the limiter circuit of FIG.

7 is a waveform diagram (2) of input / output characteristics by the limiter circuit of FIG.

[Explanation of symbols]

12 input terminals 13, 13a, 13b, 32 amplifiers 14, 14 _A , 14 _B output terminals 21 input signal level adjusting circuit 31 amplifier input circuit

Claims (2)

[Claims] 1. An amplification means for amplifying an input signal, a peak hold means for detecting and holding a peak value of the input signal, a peak value from the peak hold means for operating as a control signal, An input signal level adjusting circuit comprising: switching means for attenuating the level; and self-biasing means for biasing the switching means based on an output signal from the amplifying means. 2. The input signal level adjusting circuit according to claim 1, wherein the bias value is variable according to the gain of the amplifying means.