JPS62229972A - Compound semiconductor device and its manufacturing method - Google Patents

Abstract

PURPOSE:To manufacture a high speed semiconductor device at low source resistance with ohmic electrode arranged adjoining a gate electrode in self alignment with low contact resistance by a method wherein the topmost layer of the compound semiconductor in contact with the ohmic gate is formed of indium gallium arsenide. CONSTITUTION:An undoped GaAs layer 2, an N type AlyGa1-yAs layer 3 are successively grown on a semiinsulating GaAs substrata 1; an N type or N<+> type indium gallium arsenide (InxGa1-xAs) layer 4 is grown; and a source metallic layer 5 for drain electrode is deposited on the layer 4. Next, after forming a resist pattern 7 with an opening and removing the metallic layer 5 for electrode and the InxGa1-xAs layer 4 on said opening, another metallic layer 6 for gate electrode is deposited on the resist pattern 7. Finally, a field- effect transistor is completed by lifting off the metallic film 6 and the resist 7 excluding the opening part.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a compound semiconductor transistor.

In particular, the present invention relates to a compound semiconductor device having an ohmic electrode suitable for increasing speed and reducing noise, and a method for manufacturing the same.

[Conventional technology]

Compound semiconductor field effect transistor, e.g. GaAs
MESFET or AQ Ga As / Ga
For the formation of ohmic electrodes in field effect transistors using heterojunctions such as A s, A
The most commonly used technique is to use an alloy and perform an alloying process with a compound semiconductor layer. In addition, a method is known in which ohmic contact is obtained without using an alloying process by placing an n+ germanium (n''Ge) layer in contact with the lower part of the metal layer for ohmic electrode (Japanese Patent Application Laid-Open No.
O-84882).

[Problem that the invention seeks to solve]

The source resistance Rs (= It is desirable to minimize Rc+R's).@To reduce R's, the distance (I, s) between the ohmic electrode and the gate electrode can be shortened, but A u G e is chemically Since etching is difficult, the process usually involves forming a batten using lithography and then performing lift-off.

With the above method, it is difficult to process a fine structure with good reproducibility, and it is difficult to reduce Ls. Furthermore, during the alloying process, the semiconductor layer under the ohmic electrode undergoes metamorphosis.

The resistance becomes low and the gate breakdown voltage deteriorates.

There are problems such as the substrate current flowing easily6 or n
``When a Ge layer is used, a sufficiently low contact resistance cannot be obtained because a potential barrier exists for conduction electrons at the interface between the Ge and the metal for the ohmic electrode and the lower semiconductor layer such as GaAs. An object of the present invention is to provide a compound semiconductor device having a new ohmic electrode structure and a method for manufacturing the same, which solves the problems of the prior art described above.

[Means for solving problems]

The key point of the present invention is that the top layer of the compound semiconductor in contact with the ohmic electrode is made of indium gallium arsenide (InxGa
l-xAs), the contact resistance Re is low,
In addition, the ohmic electrode is placed adjacent to the gate i'ttti in a self-aligned manner, realizing a high-speed compound conductor device with a low source resistance Rs. The phenomenon that the contact resistance of the electrode metal to the lower semiconductor layer is reduced by providing a layer is applied to a compound semiconductor transistor to reduce parasitic resistance.

The details of the present invention will be described with reference to FIG. 1 in the case where it is implemented in a field effect transistor (HEAT) using an As/GaAs heterojunction. In Figure 1, 1 is a semi-insulating Ga As substrate, 2 is a G
a As layer, 3 is AnyG a 1- y A
It is the s layer. Usually, the GaAs layer 2 is undoped, AQ
, the Ga air As layer 3 is n-type doped, and the GaAs layer 2 and the AILyGat-yAs Ma
A two-dimensional electronic layer is formed at the interface with. 4 is n-type I
It is an nxGa1-xAs layer. However, the mixed crystal ratio X is Al
ly G a 1- y A 8 In the vicinity of the interface with layer 3, x ~ O.

Near the interface with the GaAs3 plate 1, 0.8x≦1 (J, M, Woodall et al.
l, Journal of Vacuum Science and Technology
5science and Technology) 1
9(3), (1081) p, 626-p, 627
).

Note that 5 is a source and drain electrode, and 6 is a gate electrode. Here, the source and drain electrodes 5 are formed adjacent to the gate electrode 6 in a self-aligned manner.

Next, a method of manufacturing a field effect transistor having the above structure will be explained with reference to FIG. A semi-insulating GaAs substrate 1, an undoped GaAs layer 2, an n-type A(ly
G az -y As layers 3 are grown sequentially as shown in FIG. 2(a), and then n-type or n-type InxG is grown.
At-X A 8 layer 4 is grown, and the source
A metal layer 5 for the drain electrode is deposited as shown in FIG. 2(b). However, the mixed crystal ratio X of the In, Ga1-xAs layer 4 is x~0 near the junction with the n-type AfiyGa1-2As layer 3, and 0.8x near the junction with the electrode metal layer 5.
Make sure that ≦1. Next, a resist pattern 7 having an opening is formed, and after removing the electrode metal layer 5 and the InxGa, -xAs layer 4 in the opening, the gate electrode metal layer 6 is formed as shown in FIG. 2(c). accumulate. Finally, by lifting off the metal layer 6 other than the openings together with the resist 7, a field effect transistor as shown in FIG. 1 is completed.

Next, a case where the present invention is implemented in a GaAs MESFET will be explained using FIG. As shown in FIG. 3(a), a p-type GaAs layer 1 is formed on a semi-insulating GaAs substrate 1.
1, n-type Ga As layer 12 and n-type M Ga
A s layer 13 is formed. Then Inx Gal-
XAs layer 4 and source/drain electrode metal layer 5
is formed as shown in FIG. 3(b). However, Inx
Ga1-, the mixed crystal ratio X of the As layer 4 is n-type Aa Ga
A resist pattern 7 having an opening is formed, and Inx
Ga1-xAs layer 4, electrode metal layer 5 and n-type M G
After removing the aAsAlB 12, a gate electrode metal 6 is deposited as shown in FIG. 3(Q). Finally, by lifting off the metal layer 6 other than the openings together with the resist, GaAs ME is formed as shown in FIG. 3(d).
SFET is completed.

[Effect]

In Fig. 1 and Fig. 3(d) above, InxG a
x −x As The mixed crystal ratio X of the s layer 4 is A11yGa1−
yAsAsF3 is an n-type A (by setting x to 0 near the junction with the lGaAs layer 13, the above M, G
The conduction band gap at the interface with the AayGal-yAsAsF3 interface is minimized, and a good epitaxial film with fewer defects at the AayGal-yAsAsF3 interface can be formed. Further, the mixed crystal ratio X of the InxGa-8As layer 4 is 0.8 and x≦1 near the junction with the source/drain electrode metal layer 5.
It becomes. Therefore, the height of the barrier to conduction electrons, the so-called Schottky barrier, is ~OeV. Therefore, the source/drain electrode 5 can form an ohmic junction with an extremely low contact resistance with the underlying semiconductor layer without performing a thermal process such as alloying. Furthermore, when a field effect transistor is formed based on the steps shown in FIGS. 2 and 3, the source/drain electrode 5 is placed very close to the gate electrode 6 in a self-aligned manner. can be formed. As a result, the series resistance R'
s can be reduced, and a high-speed and low-noise element can be realized.

Here, the source resistance Rs of the FET according to the present invention shown in FIG. 1 and the conventional GaAs MESFET shown as an example in FIG. 4 will be compared. In the conventional example shown in Fig. 4,
Rs is given by the following formula.

Rs=Rc+R's R's=ρ5-Ls/W Rcw FI)T/W However, R's is the series resistance between the source and gate, R
e is the contact resistance of the source electrode, ρS is the sheet resistance of the n+ layer 20, pc is the contact specific resistance of the source electrode, Ls is the distance between the source and gate, and W is the gate width @n''A20
and the series resistance between the gate and n”A20 and n111
Contact resistance between the two is not considered. Here, the n+ layer 20 is
a A s, and typical values when the source electrode 5 is made of A u G e metal by lift-off processing are ρ5 = 200Ω/mouth Ls = 21M W = 101! m, in which case R'5==20Ω Rs≧20Ω In an actual element, the contact resistance Re of the A u G e electrode with respect to n+ is added in addition to the above Rs.

On the other hand, when n'' Ge is used as the n+ layer 20, even if Ls=0 (R's=O), Rs=Rc
= 17Ω However, here Rcw 1.4 x 10-”
Ωd (Proceedings of the 45th Japan Society of Applied Physics Conference, p549
).

However, according to the present invention, Ls=O1, that is, R's=
O, and the value of pc is about 3×10 −′Ωd, so Rs=Rc group 8Ω, and the value of Rs can be reduced to one-half or less compared to the conventional case.

In addition, InGaAs is used as the lower semiconductor layer for AIL G
When it comes into contact with aAs, it is possible to selectively dry-etch the Aa Ga As by using a chlorine-based gas, so it has excellent workability.

Further, the present invention does not require an alloying process.

In conventional ohmic junction methods that require diffusion of metal materials through thermal processes such as alloying or sintering, a low-resistance layer is formed below and around the source/drain electrodes. When formed adjacent to an electrode, the gate withstand voltage deteriorates and substrate current flows more easily, causing problems such as a short channel effect when the channel length becomes short.

However, the present invention does not require an alloying process.

The above problems can be avoided. others.

Deterioration of other parts of the element during heat treatment in the alloying process can be prevented. Further, the source/drain electrodes have an excellent feature that they do not require a lift-off process and can be formed in a self-aligned manner by an extremely simple process.

In addition, AaGaAs/G shown in FIGS. 1 and 2
When implemented in a field effect transistor using an a As heterojunction, the structure of the layers below the In, Ga□-xAs layer 4 may be slightly different. For example, M G a A s
The n-type doping of layer 3 may be non-uniform in the depth direction. Furthermore, in order to form FETs with different threshold voltages on the same wafer, the MGaAs layer 3 is replaced with GaAs.
The same applies to the case of a multilayer structure of S and All Ga As. In this case, part of the All Ga As layer 3 will also be etched during etching of the resist opening.

Furthermore, when implemented in the GaAs MESFET shown in FIG. 3, the p-type GaAs layer is not directly related to the present invention and may be omitted, and the AQ GaAs layer 1
3 acts as a stopper for the upper layer when etching the resist opening, but it may be omitted, or the MGaAs 113 may be left without being etched when etching the opening.

〔Example〕

Next, embodiments according to the present invention will be described in more detail with reference to the drawings. 1 and 2 (a) to (c) show a first embodiment of the present invention, MyGa, -, As /G
A cross-sectional view showing a field effect transistor having an aAs heterojunction and the manufacturing process. FIGS. 3(a) to 3(d) are cross-sectional views showing the manufacturing process when implemented in a GaAs MESFET according to a second embodiment of the present invention. . Figures 1 and 2
In Figure (a), p −(~5×10” am
-'') GaAs layer 2 is grown to about 11M.
Type ^ (L, Ga knee 2As (usually y is 0.2 to 0.3
layer 3 (used in the range). -The concentration of n-type impurity is about 2X10"(!m-", and the film thickness is 50na+
degree. Next, an InxGa-xAs layer 4 and a metal layer 5 for source/drain electrodes are deposited as shown in FIG. 2(b). However, InxGa1-, the mixed crystal ratio X of the As layer 4 is n-type Aa.

Ga1−, x ”O near the junction with the As layer 3, 0.8 near the junction with the source/drain electrode metal layer 5=x
≦1, the total film thickness is 200 nm, and the concentration is approximately 5×1.
SL was doped with 0"cs-'. The above-mentioned mixed crystal ratio X needs to be changed almost continuously, but the rate of change does not have to be particularly uniform. 10
After growing an amount of about 0n, X may be gradually increased. Electrode metal M! Any type of metal may be used for the source/drain electrodes of I5, and in this example, aluminum (All) with a film thickness of 1100 nm was used. Next, after isolation between elements is performed by mesa etching, a resist pattern 7 having an opening corresponding to the gate pattern is formed, and the electrode metal layer 5 and the InxGa1-xAs layer 4 in the opening are removed by chemical etching. Thereafter, a gate electrode metal 6 is deposited as shown in FIG. 2(c). The gate electrode metal 6 is Au/Pt/Ti (100na+/5
0nm/50nm). Finally, the metal layer 6 other than the opening was lifted off together with the resist 7 to complete a field effect transistor as shown in FIG. According to the above embodiment, the source/drain electrodes can be formed very close to the gate electrode in a self-aligned manner, and the contact resistance Re is also extremely small (~3
X10''''Ωd) The source resistance Rs can be reduced, and a high-speed, low-noise device can be realized. Sources that require traditional alloying processes.

When using a drain electrode, if the electrode is brought close to the gate electrode, the gate withstand voltage will deteriorate, substrate current will more easily flow under the gate, and other parts of the device will deteriorate during the thermal process in the alloying process. There were some problems such as
Since the present invention does not require an alloying process, the above problems can be avoided, and InGaAs is
Since it is possible to selectively remove a A s, a high-speed device as shown in this embodiment can be stably manufactured.

In this example, a conventional HEMT in which the AnGaAs layer is uniformly doped with n-type is shown.

In addition, Afl Ga A improves gate breakdown voltage.
The same holds true when a part of the AQGaAs layer is undoped for the purpose of improving the mobility of the two-dimensional electron gas in the s/GaAs junction. Also FET
The same holds true when the AmGaAs layer is replaced with a multilayer of GaAs layers and AaGaAs layers for the purpose of forming FETs with different threshold voltages on the same wafer.

Next, in the second embodiment shown in FIG. 3, as shown in FIG. 3(a), a p-type GaA
s layer 11 (~I Xl017an-' Be doped, film thickness ~ IIIm), n-type GaAs layer 12 (~5
10"3-", Si doped, film thickness ~10100n and n-type nGaAs layer 13 (~5 x 101017
a', Si doped, i thickness ~30 nm) are formed respectively. Next, an InxGax-xAs layer 4 and a metal layer 5 for source/drain electrodes are formed as shown in FIG. 3(b). However, the mixed crystal ratio of the Ga, -, As layers
x = O near the junction with the n-type AQ Ga A 5N13, 0.8 (x≦1, and the film thickness is 200 mm or less near the junction with the metal layer 5 for source/drain electrodes. Then, mesa etching After performing isolation between elements, a resist pattern 7 having an opening corresponding to a gate button is formed, and the electrode metal layer 5 and InxG in the opening are formed.
The a1-xAs layer 4 is removed using the n-type u Ga A 8 layer 13 as a stopper, and then the n-type M Ga A 8
After removing the layer 13, Au is used as the gate electrode metal 6.
/Pt/Ti (100nm/ 50nm/ 50nm)
are deposited as shown in FIG. 3(c). Finally, by lifting off the metal layer 6 other than the opening along with the resist, GaAs ME S is formed as shown in FIG. 3(d).
FET is completed.

According to this embodiment, as in the case of the first embodiment, the source/drain electrode 5 can be formed very close to the gate electrode 6 in a self-aligned manner.

Since the contact resistance is low, the source resistance Rs can be reduced, and a high-speed, low-noise device can be manufactured. Note that the AaG&AsWI 13 in this embodiment is formed by forming the InxGal-xAs layer 4 during etching of the gate opening.
The Aa Ga A 8 layer 13 may be left in place during etching of the opening, although it acts as a stopper for the metal 7795 for the source and drain electrodes. Also,
The above AaGaAs JFl13 may be undoped.

〔Effect of the invention〕

As described above, the compound semiconductor device and the manufacturing method thereof according to the present invention provide source and drain electrodes by providing an indium gallium arsenide layer between the ohmic electrode metal layer and the main semiconductor layer below the metal layer. The contact resistance Rc of the electrode is extremely low.

Since the source and drain electrodes are arranged adjacent to the gate electrode in a self-aligned manner, the series resistance R's is low, and as a result, the source resistance Rs (=Rc+R's) can be reduced. Since no deterioration occurs in the underlying semiconductor layer, high-speed, low-noise compound semiconductor field effect transistors can be stably manufactured.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of a compound semiconductor device according to the present invention, FIGS. 2(a) to (c) are cross-sectional views showing the manufacturing process of the above embodiment, and FIG. FIG. 4 is a cross-sectional view showing the manufacturing process in the second embodiment, and a perspective view showing a structural example of a conventional GaAs MESFET. 1...GaAs substrate 2...-Undoped GaAs layer 3, 13--AaGaAs layer
4-I nxGal-xAs layer 5...Source-drain electrode metal 6...Gate electrode metal 11...p-type Ga A
s layer 12-n type GaAs layer

Claims (1)

[Claims] 1. Indium gallium arsenide (In_x
A compound semiconductor device provided with a Ga_1_-_xAs) layer. 2. The indium gallium arsenide layer has a mixed crystal ratio x of 0.8≦x≦1 on the side of the ohmic electrode metal layer, and x near the junction with the main semiconductor layer. The compound semiconductor device according to claim 1, wherein the compound semiconductor device is 0 to 0. 3. The compound semiconductor device according to claim 1, wherein the compound semiconductor device is a field effect transistor. 4. Step of forming an active layer in a field effect transistor, and forming In_xGa_1_-_x on top of the active layer.
Step of forming an As layer and the above In_xGa_1_-_
a step of forming a metal layer for sources and drains in contact with the upper part of the xAs layer; a step of forming a resist layer having an opening corresponding to a gate pattern on the upper part of the metal layer for sources and drains; Metal for source and drain electrodes and In_xG in the opening
a_1_-_x A method for manufacturing a compound semiconductor device, comprising the steps of removing the As layer, and after depositing the gate electrode metal layer, removing the gate electrode metal layer on the resist layer together with the resist layer.