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JPS62227296A - A/d conversion system - Google Patents

A/d conversion system

Info

Publication number
JPS62227296A
JPS62227296A JP61071755A JP7175586A JPS62227296A JP S62227296 A JPS62227296 A JP S62227296A JP 61071755 A JP61071755 A JP 61071755A JP 7175586 A JP7175586 A JP 7175586A JP S62227296 A JPS62227296 A JP S62227296A
Authority
JP
Japan
Prior art keywords
video signal
signal
converter
period
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61071755A
Other languages
Japanese (ja)
Inventor
Tomoaki Hayashi
智明 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61071755A priority Critical patent/JPS62227296A/en
Publication of JPS62227296A publication Critical patent/JPS62227296A/en
Pending legal-status Critical Current

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Landscapes

  • Analogue/Digital Conversion (AREA)
  • Color Television Systems (AREA)

Abstract

PURPOSE:To improve resolution in the digitization of a video signal, by setting a voltage at a value corresponding to the maximum and the minimum values of the video signal in the periods of a burst signal and the video signal, and setting the voltage at the value corresponding to the maximum and the minimum values of a color video signal in the period of a synchronizing signal. CONSTITUTION:The video signal inputted from an input terminal l is A/D-converted at an A/D converter 2, then being inputted to a synchronizing signal detection circuit 3. At such a time, the voltage of VRT-VRB1 is impressed from a synchronizing signal period reference voltage generation circuit 5 as the reference voltages 100A and 100B of the A/D converter 2. The circuit 5 is separated from the converter 2 at the completing time of the synchronizing signal, and a burst signal/ video signal period reference voltage generation circuit 6 is connected to the converter 2, and the reference voltages 100A and 100B are switched to a VRT-VRB2. At the completing time of the video signal period, the reference voltages 100a and 100B are switched again to the VRT-VRB1. Hereinafter, the same operation is repeated. Thus, since thc reference voltage of the A/D converter 2 becomes a difference between the maximum value and the minimum value, the resolution of the A/D converter can be utilized over all area.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はA/D変換方式に関し、特にカラービデオ用の
A/D変換方式に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an A/D conversion system, and particularly to an A/D conversion system for color video.

〔従来の技術〕[Conventional technology]

従来、並列型カラービデオ用A/L)コンバータでのデ
ジタル化基準電圧の最高値と最低値の差(分信号で説明
するとビデオ信号の第、高値VlLT乙最低(+ctV
a旧 との間を例えば8ビツトのA/Dコンバータを使
用した場合には256レベルの分解能でもってA/D変
換していた。
Conventionally, the difference between the highest and lowest values of the digitization reference voltage in a parallel color video A/L converter (to explain in terms of minute signals, the highest value of the video signal, VlLT, and the lowest value (+ctV)
For example, when an 8-bit A/D converter was used, A/D conversion was performed with a resolution of 256 levels.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

レベルのレベル分解能を持っているが、状体信号期間(
実際のテレビ1111i面を走査する期間)でも同期信
号に相当するレベルを含めて256レベルの分解能でA
/L)変換するので、映像信号のみのレベル分解能は2
56レベルの約85チのレベル分解能に減少してしまう
という欠点がある。
level resolution, but the body signal period (
Even during the scanning period of the actual TV 1111i screen), A with a resolution of 256 levels, including the level equivalent to the synchronization signal.
/L) conversion, so the level resolution of only the video signal is 2.
The disadvantage is that the level resolution is reduced to approximately 85 inches (56 levels).

〔問題点全解決するための手段〕[Means to solve all problems]

本発明のA/IJ変換方式は、カラービデ第1.−;号
信号)と映像信号の期間中は映像信号の最高値と最低値
とに応じた電圧とすることと、同期信号の期間中はカラ
ービデオ信号の最高値と最低値とに応じた電圧とするこ
ととを備えて構成さnる。
The A/IJ conversion method of the present invention is based on the color bidet first . - during the period of the signal) and the video signal, the voltage shall be set according to the highest and lowest values of the video signal, and during the period of the synchronization signal, the voltage shall be set according to the highest and lowest value of the color video signal. It is configured with the following features.

〔実施例〕〔Example〕

第1図は本発明をA/L)変換器へ適用したー実施91
jの構成を示すブロック図、第2図はビデオ信号の概要
を示す図表である。
Figure 1 shows the application of the present invention to an A/L) converter - Implementation 91
FIG. 2 is a block diagram showing the configuration of the video signal.

まず、第2図を見るに入力するビデオ信号は同期信号2
0とバースト信号(副搬送波基準信号)21と映像信号
22とで構成され、先行した映像信号のフロントポーチ
期間23を経過し死後に1フレームのビデオ信号が続い
ている。一般に、vRT  vttnt  で表わされ
るビデオ信号のうち、同期信号20の最低値とバースト
信号21および映像信号22の最低値との差すなわちV
RBI  VRBIは、VxtT VRBI02/14
となっている。従ッて従来VRT  VRBI kあら
かじめ定められたレベル数(例えば8ビツトでデジタル
化する場合は256レベル)の分解能でデジタル化して
いるものを、同期信号期間中はVltr −VRBI 
>あらかじめ定められたレベル数の分解能で、バースト
信号と映像信号期間中はVR’l’  VRBIをあら
かじめ定められた分解能でデジタル化することによって
、のである。
First, looking at Figure 2, the input video signal is synchronization signal 2.
0, a burst signal (subcarrier reference signal) 21, and a video signal 22, and one frame of video signal continues after the front porch period 23 of the preceding video signal has elapsed. In general, the difference between the lowest value of the synchronizing signal 20 and the lowest values of the burst signal 21 and the video signal 22, that is, V
RBI VRBI is VxtT VRBI02/14
It becomes. Therefore, conventional VRT VRBI k is digitized with a resolution of a predetermined number of levels (for example, 256 levels when digitizing with 8 bits), but during the synchronization signal period, VLTr - VRBI
>VR'l' during the burst signal and video signal period with a predetermined resolution of a predetermined number of levels.By digitizing VRBI with a predetermined resolution.

次に不発明を適用した一実施例を第1図を参照して説明
する。ビデオ信号入力端子lから入力されるビデオ信号
は、A/Dコンバータ2でA/D変換され変換された例
えば8ビットティジタル信号は、ビデオ信号出力端子L
Aに出力するとともに同期信号検出回路3に入力される
。この時〜巾コンバータ2の基準電圧100A・1oo
B(浴電圧が印加される。同期信号検出回路3で検出さ
れた同期信号は、タイミング発生回路4に入力ざnる。
Next, an embodiment to which the invention is applied will be described with reference to FIG. The video signal input from the video signal input terminal L is A/D converted by the A/D converter 2, and the converted 8-bit digital signal, for example, is output from the video signal output terminal L.
A and is also input to the synchronization signal detection circuit 3. At this time, the reference voltage of the width converter 2 is 100A/1oo
B (bath voltage is applied. The synchronization signal detected by the synchronization signal detection circuit 3 is input to the timing generation circuit 4.

タイミング発生回路4は、同期信号終了時(バースト信
号・映像信号発生期間の始まり)よりアナログスイッチ
切断信号をアナログスイッチ7A・7Cに印加してこれ
を切断し1同期信号期間用基準電圧1発生回路5をA/
L)コンバータ2から切り離す。また、アナログスイッ
チ切断信号tインバータ8に印加しその出力tアナログ
スイッチ接続信号とし、アナログスイッチ7B・7Dに
印加してこれを接続してバースト信号・映像信号期間用
基準電圧発生回路6 f A / Dコンバータ2に接
続し基準電圧100A−100Bをva’r−VRBI
  (バースト信号・映像信号期間用)に切り換える。
The timing generation circuit 4 applies an analog switch disconnection signal to the analog switches 7A and 7C at the end of the synchronization signal (the beginning of the burst signal/video signal generation period) to disconnect them, and generates a reference voltage 1 for one synchronization signal period. 5 as A/
L) Disconnect from converter 2. Further, an analog switch disconnection signal t is applied to the inverter 8, and its output t is used as an analog switch connection signal, and this is applied to the analog switches 7B and 7D to connect them to the burst signal/video signal period reference voltage generation circuit 6 f A / Connect to D converter 2 and set reference voltage 100A-100B to va'r-VRBI
(for burst signal/video signal period).

映像信号期間終了時(すなわち第2図のフロントポーチ
期間23)でタイミング発生回路4の出力がアナログス
イッチ接続信号となり、上述と逆の動作で再び基準電圧
100A−100B’kVRr  VRBI  (同期
信号期間用)に切換える。
At the end of the video signal period (i.e., front porch period 23 in FIG. 2), the output of the timing generation circuit 4 becomes an analog switch connection signal, and the reference voltage 100A-100B'kVRr VRBI (for the synchronization signal period) is generated again by the reverse operation to the above. ).

以後この操作を縁り返し、同期信号期間では基準電圧(
V+ζT −VRHI  )で、バースト信号・映像信
号期間中は基準電圧(VRT −VRn*  )でA/
L)変換を行う。
After that, this operation is repeated, and the reference voltage (
V + ζT - VRHI), and the reference voltage (VRT - VRn*) during the burst signal/video signal period.
L) Perform the conversion.

以上のようにして映像信号期間中でもA/IJコニyバ
−タ2(D%準電圧(VRT  VRBI  ) カe
(&(Rt号の最大値と最小値の差となるのでA/Dコ
ンバータの分解能を全域にわたって活用することになる
As described above, even during the video signal period, the A/IJ converter 2 (D% quasi-voltage (VRT VRBI)
(&(Since it is the difference between the maximum value and the minimum value of Rt, the resolution of the A/D converter is utilized over the entire range.

〔発明の効果〕〔Effect of the invention〕

以上1ilツ」したように本発明は、ビデオ信号iA/
DコンバータでA/D変換するとき、映像信号期間に映
像(N号の最大値と最小値の差の基準電圧を供船し、て
あらかじめ定められたA/Dコンバータのレベル数の分
解能をほぼ100チ映像信号(実際のテレビ走査)期間
で使用できることにより、テレビ画面で映像を再生した
ときに従来と比較してテレビ画質が向上するという効果
がある。
As described above, the present invention provides video signal iA/
When performing A/D conversion with a D converter, a reference voltage of the difference between the maximum and minimum values of the video signal (N) is provided during the video signal period, and the resolution of the predetermined number of levels of the A/D converter is approximately the same. Since it can be used in a 100-inch video signal (actual television scanning) period, it has the effect of improving the television picture quality when playing back images on a television screen compared to the conventional method.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発りL!?A/D変換器へ適用した一実施例
の構成を示すブロック図、第2図はビデオ信号の概要を
示す図表。 1・・・・・・ビデオ信号入力端子、lA・・・・・・
ビデオ信号出力端子、2・・・・・・A/Dコンバー・
夕、3・・・・・・同期信号検出回路、4・・・・・・
タイミング発生回路、5・・・・・・同期信号期間用基
準電圧発生回路、6・・・・・・バースト信号・映像信
号期間用基準電圧発生回路、7A〜7D・・・・・・ア
ナログスイッチ、8・・・・・・インバータ。
Figure 1 is the original L! ? FIG. 2 is a block diagram showing the configuration of an embodiment applied to an A/D converter, and FIG. 2 is a chart showing an outline of a video signal. 1...Video signal input terminal, lA...
Video signal output terminal, 2...A/D converter
Evening, 3... Synchronous signal detection circuit, 4...
Timing generation circuit, 5... Reference voltage generation circuit for synchronization signal period, 6... Reference voltage generation circuit for burst signal/video signal period, 7A to 7D... Analog switch , 8... Inverter.

Claims (1)

【特許請求の範囲】[Claims] カラービデオ信号のA/D変換方式において、デジタル
化基準電圧の最高値と最低値との差を、バースト信号(
副搬送波基準信号)と映像信号との期間中は映像信号の
最高値と最低値とに応じた電圧とすることと、同期信号
の期間中はカラービデオ信号の最高値と最低値とに応じ
た電圧とすることとを備えてなるA/D変換方式。
In the A/D conversion method for color video signals, the difference between the highest and lowest values of the digitized reference voltage is expressed as a burst signal (
During the period between the subcarrier reference signal) and the video signal, the voltage is set according to the highest and lowest values of the video signal, and during the period of the synchronization signal, the voltage is set according to the highest and lowest value of the color video signal. An A/D conversion method that includes converting to voltage.
JP61071755A 1986-03-28 1986-03-28 A/d conversion system Pending JPS62227296A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61071755A JPS62227296A (en) 1986-03-28 1986-03-28 A/d conversion system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61071755A JPS62227296A (en) 1986-03-28 1986-03-28 A/d conversion system

Publications (1)

Publication Number Publication Date
JPS62227296A true JPS62227296A (en) 1987-10-06

Family

ID=13469667

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61071755A Pending JPS62227296A (en) 1986-03-28 1986-03-28 A/d conversion system

Country Status (1)

Country Link
JP (1) JPS62227296A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51150911A (en) * 1975-06-19 1976-12-24 Matsushita Electric Ind Co Ltd Multiple video signal digital converter
JPS616994A (en) * 1984-06-21 1986-01-13 Casio Comput Co Ltd Color video signal A/D converter

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51150911A (en) * 1975-06-19 1976-12-24 Matsushita Electric Ind Co Ltd Multiple video signal digital converter
JPS616994A (en) * 1984-06-21 1986-01-13 Casio Comput Co Ltd Color video signal A/D converter

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