JPS62217668A - Semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] In order to sufficiently reduce the source/drain region resistance and the gate electrode wiring resistance in MIS type semiconductor devices, the present invention includes the formation of a silicide layer and a tunnel insulating film. The present invention provides a semiconductor device structure that also uses a structure in which metal layers are laminated via a metal layer T-layer.

[Industrial application field]

The present invention relates to a semiconductor device, and particularly to an MIB type semiconductor device.

In MIS type semiconductor devices, signal propagation delays due to wiring parasitic resistance are becoming more prominent as the integration becomes higher, and reducing the layer resistance, especially in gate electrode wiring and source/drain regions, is an important issue.

[Conventional technology]

One of the methods conventionally proposed to achieve the above-mentioned problem is silicide technology. In this method, a high-melting point metal such as Mo, W, or Ti that can form silicide is coated with the north drain region and gate polysilicon layer surface exposed, and silicide is formed only on the exposed silicon surface through a solid phase reaction. This is a technique in which the remaining metal is removed, and silicide R for lowering resistance is formed only in necessary locations.

[Problem that the invention seeks to solve]

In conventional silicide technology, silicide of equal thickness is formed on the source/drain regions and the gate polysilicon surface.

Since the reaction of the underlying silicon contributes to the formation of silicide, the silicide layer is formed by penetrating into the silicon. On the other hand, the source/drain regions become difficult to achieve due to high density, and have a junction depth of only about 800 nm, for example. If silicide progresses to this shallow junction, there is a possibility that the junction will be completely short-circuited and destroyed. On the other hand, since the gate polysilicon layer is used as a long word line, the requirement for low resistance is even stronger, so a silicide layer that is thin enough not to affect the source/drain junction is similarly formed. In view of the above points, the present invention aims to provide a structure in which the resistances of the source/drain regions and the gate electrode wiring can be sufficiently reduced.

[Means to resolve issues]

In the present invention, a metal silicide layer is formed on the surface of the north drain region, and a metal layer is further laminated on the silicide formed in the same manner for the gate electrode wiring via a tunnel insulating film.

[For production]

With the above configuration, the resistance in the υ, gu) III pole arrangement is lower than that in the source/drain region by the metal layer, so
Both can be made as low as necessary and sufficient.

〔Example〕

Figure ag1 is a cross-sectional view of the structure of the embodiment of the present invention.
2 is a silicon substrate, 2 is a source/drain region, 8 is a north/drain low concentration region, 3 is a silicide layer, 4 is a gate insulating film, 5 is polysilicon, 6 is a tunnel insulating film, 7 is a metal layer, 8 , 9 is an insulating film, and 10 is an AI electrode.

FIGS. 2(a) to 2) are diagrams showing the manufacturing process of an embodiment of the present invention, and the same numbers as in FIG. 1 indicate the same parts.

Next, embodiments of the present invention will be explained along the manufacturing process.

First, after forming a field insulating film (not shown) and a gate insulating film 4t on a substrate 1, a polysilicon layer pattern 5 (about 20 nm thick) forming a part of the gate electrode wiring is formed.
- Form a low concentration source/drain n-type layer 8 of polysilicon? It is formed by As ion implantation using a mask. After that, apply C to a thickness of about PIJm 8 ve200mm on the entire surface.
It is grown by the VD method (Fig. 2(a)).

Next, the entire surface of the insulating film is etched using the glnIE method, leaving only the polysilicon sidewall portion in the form of a so-called sidewall. Here, ion implantation is performed to form high concentration source/drain regions 2. After that, a high melting point metal 11, for example Ta, is applied to a thickness of 10
~2Qnm (Fig. 2)).

Next, the substrate is heated in an oxidizing atmosphere to create silicide by solid-phase reaction, and a Tad compound r with a thickness of 2 to 3 nra is formed.
Formed in lA6. The heat treatment for silicidation may be performed separately in a non-oxidizing atmosphere.

Thus, as shown in FIG. 2(C), a tunnel insulating film 6 made of silicide 8 and Ta oxide is formed.

Unreacted Ta1l remains in areas other than the exposed silicon parts.Next, high melting point metal (Mo, W, etc.)? Approximately 200n
It is deposited to a thickness of m and patterned into a gate electrode pattern. Furthermore, the exposed Ta oxide film 6 and TaglJl
After removal by lt-etching, the structure shown in FIG. 2(d) is obtained.

After this, an interlayer insulating film 9 is deposited, contact holes are formed, and electrode wiring 10 is formed, resulting in the structure shown in FIG.

In the completed structure shown in FIG. 1, a tunnel insulator 86 is interposed between the metal layer 7 and the lower silicide layer 8 and the polysilicon layer 5, but the two are in a conductive state due to the flow through the tunnel, and an integral conductive layer is formed. functions as Effective guidance 1!
Since the conductivity r is given by the gold R layer 7, it is not only higher than that of polysilicon, but also can be increased by one to two orders of magnitude even when the entire structure is made of a silicide layer.

〔Effect of the invention〕

According to the present invention, in addition to lowering the resistance by forming a thin silicide layer in the source/drain regions where there is a risk of junction breakdown, it is possible to further reduce the resistance in the gate electrode wiring part by laminating gold 8. The effect of improving operating speed with high integration density ICVC is remarkable.

[Brief explanation of drawings]

FIG. 1 is a structural sectional view of an embodiment of the present invention, and FIG. 2 is a structural cross-sectional view of an embodiment of the present invention! ! ! FIG. 2...Source/drain region 8...Silicide 5...Polysilicon...Tunnel insulating film 7...Metal film JIT city UQ mouth diagram 1

Claims (1)

[Claims] The silicide layer (3) is on the surface of the source/drain region (2).
) is formed, and the gate electrode wiring is a polysilicon layer (5).
a silicide layer (3) thereon, and a metal layer (7) laminated on the silicide layer via a tunnel insulating film (6).
1. A semiconductor device comprising a laminate of.