JPH02283034A - Semiconductor device - Google Patents

Abstract

PURPOSE:To decrease the resistance of a gate electrode wiring, and increase the operating speed of a semiconductor circuit element by a method wherein a high melting point metal silicide is deposited on a silicide layer formed on a polysilicon gate in the self alignment manner. CONSTITUTION:An MOS transistor wherein a gate, a source and a drain are turned into silicide in the self alignment manner is formed in a circuit made on the surface of a semiconductor substrate, thereby decreasing the resistance of a source and a drain. The surface is covered with an interlayer insulating film 3, and flattened. The upper part of a gate 5 only is exposed from the interlayer insulating film, and thereon high melting point metal silicide 8 is deposited. By exposing only the silicide layer on the upper part of the gate from the interlayer insulating film in this manner, and forming the high melting point metal silicide layer 8, the gate wiring resistance can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, and more particularly to a MOS transistor wiring of the device.

(Prior art) Regarding a conventional semiconductor device of this type, FIGS.
This will be explained using figures.

A field insulating film 32 is formed on the surface of the semiconductor substrate 31 . The field insulating film 32 is formed of a thermal oxide film by selective oxidation [FIG. 3(a)], and the active region 33 has a MOS
A transistor is formed. In the MOS transistor, a gate oxide film 34 is formed in an active region 33, a polycrystalline silicon film is formed, a gate electrode 35 is formed, a sidewall spacer 36 is formed [FIG. 3(b)], and a gate electrode 35 is formed. with the source and drain regions 37 as a mask.
is formed [Fig. 3(c)]. Also, the gate and source of a MOS transistor.

A silicide layer is formed on the drain surface in a self-aligned manner. As shown in FIG. 4, the silicide layer 39 is formed in a self-aligned manner by forming a metal thin film 38 on top of the MOS transistor [FIG. 4(a)], and performing heat treatment to bring the metal thin film and silicon into contact. This is done by forming a silicide layer on the exposed portion [FIG. 4(b)], and removing the unreacted metal thin film on the field insulating VX 32 and the sidewall spacer 36 [FIG. 4(C)]. By siliciding the gate, source, and drain of a MOS transistor in a self-aligned manner, the resistance of each of them is reduced, and the speed of the semiconductor circuit element is increased.

(Problem to be Solved by the Invention) In the above structure, the 'I!' of the element. When the source and drain diffusion layers become shallower due to miniaturization, the thickness of the silicide layer formed in a self-aligned manner is the same as that of the source.

It is necessary to make it thinner depending on the depth of the drain diffusion layer.

The silicide layer formed in a self-aligned manner forms the upper part of the gate,
Since the upper part of the source and the upper part of the drain are formed at the same time,
All the thicknesses are about the same. Therefore, when the source and drain diffusion layers become shallower due to miniaturization of devices, the silicide layer above the gate also becomes thinner, and the resistance value of the gate increases to such a level that the effect of lowering resistance due to silicide cannot be fully expected. , speeding up of semiconductor circuit elements cannot be expected. An object of the present invention is to further reduce the resistance of the gate of a MOS transistor in which the gate, source, and drain are silicided in a self-aligned manner as elements become smaller.

(Means for Solving the Problems) In order to solve the above problems, one aspect of the present invention is to provide a gate in a semiconductor circuit formed on the surface of a semiconductor substrate.

The source and drain are self-aligned silicided M
An OS transistor is formed using conventional technology, and the source,
In addition, we have lowered the resistance of the drain.

This is a semiconductor device having a MOS transistor gate structure covered with an interlayer insulating film, planarized, only the upper part of the gate is exposed from the interlayer insulating film, and high melting point metal silicide is deposited on the upper part of the gate.

(Function) With the above structure, the rate is determined by the depth of the source and drain diffusion layers. After depositing an interlayer insulating film on top of the silicide layer on the top of the gate, planarization is performed to expose only the silicide layer from the top 1 to the upper silicide layer from the interlayer insulating film to form a high-melting point total bending silicide layer, thereby forming a gate wiring. The resistance can be further lowered, and the speed of the semiconductor circuit element can be increased.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. Figures 1 and 2 (a) and (b) are.

1A and 1B are a cross-sectional view, a plan view, and a side cross-sectional view of a MOS transistor, respectively. In the figure, 1 is, for example, a P-type silicon substrate, 2 is a field insulating film, 3 is a planarized interlayer insulating film, 4 is a sidewall spacer, 5 is a polycrystalline silicon gate, and 6 is a polycrystalline silicon gate formed in a self-aligned manner. A silicide layer above the crystalline silicon gate, 7 a gate oxide film, 8 a refractory metal silicide gate, and 9 source and drain regions silicided in a self-aligned manner.

The present invention can be applied not only to P-type silicon substrates but also to N-type silicon substrates, and also to CMOS transistor circuits.

(Effects of the Invention) As explained above, a semiconductor device according to the present invention is produced by depositing a high melting point metal silicide on a polycrystalline silicon gate on which a silicide layer is formed in a self-aligned manner. This has the effect of lowering the resistance of the gate electrode wiring and increasing the speed of the semiconductor circuit element.

[Brief explanation of drawings]

1, 2(a) and 2(b) are a cross-sectional view, a plan view, and a side sectional view thereof, respectively, of a MOS transistor of a semiconductor device according to the present invention, and FIG. 3 shows a simple manufacturing method of the MOS transistor. FIG. 4 is a diagram showing a method for forming a self-aligned silicide layer. 1... Semiconductor substrate (P-type silicon substrate), 2...
- Field insulating film, 3... Flattened interlayer insulating film, 4... Side wall spacer, 5... Gate electrode (polycrystalline silicon). 6. Silicide layer formed in a self-aligned manner. 7... Gate oxide film, 8... High melting point metal silicide gate, 9... Source, drain region. Patent applicant: Matsushita Electronics Co., Ltd. f3'u(hia%"jt7; v y'a m
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Claims (1)

[Claims] A field insulating film is formed on the surface of the semiconductor substrate, a MOS transistor is formed in the active region, a silicide layer is formed in a self-aligned manner on the gate, source, and drain surfaces of the MOS transistor, and the source and drain are covered with an interlayer insulating film. 1. A semiconductor device characterized in that the gate is flattened, only the upper part of the gate is exposed from the interlayer insulating film, and a refractory metal silicide is deposited on the upper part of the gate.