JPS62205Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a substrate bias generation device that applies a reverse bias to a semiconductor substrate on which a semiconductor element such as a MOS memory is mounted.

In the case of dynamic type MOS memory, in order to prevent minority carriers from being injected into the substrate due to undershoot and entering the charge storage area and destroying the stored information, or by changing the substrate potential and increasing the juncture capacitance. The substrate is reverse biased for the purpose of preventing an increase in the current. At this time, supplying bias power from the outside naturally increases the number of pins, so a charge pump type substrate bias generator is provided within the chip to generate the bias power within the chip.

By the way, the operating mode of a device equipped with a substrate bias generator is not always constant; for example, a dynamic MOS memory may operate at the highest frequency, may only be read occasionally, or may operate in page mode. There is. For this reason,
If the reverse bias application conditions of the substrate bias generator are adapted to the highest operating frequency where maximum performance is required, if readouts are performed only occasionally, charge pumping will be excessive and the substrate potential will shift too deep. In addition to power consumption, problems such as variations in the threshold voltage Vth of the element occur. In the opposite case, charge pumping is naturally insufficient, resulting in an inconvenient rise in substrate potential. Therefore, in order to apply the optimum reverse bias to each state of the device, it is possible to solve this problem by using multiple substrate bias generators and operating each one with its own signal. This is not preferable because it reduces the space of the main body.

In order to improve this point, the present invention provides a semiconductor device chip equipped with a substrate bias generator with a plurality of signal sources, an oscillator, and a control circuit for driving the substrate bias generator. The substrate bias generator is characterized in that the outputs of the signal source and the oscillator are combined in time series, or the substrate bias generator is driven by a signal selected according to priority. This will be explained in detail with reference to an example.

FIG. 1 is a schematic block diagram showing an embodiment of the present invention. Reference numeral 1 is a charge pump type substrate bias generator that generates a bias voltage _VBB , and is installed in a part of a chip on which a group of memory cells, etc. are mounted. . The generator 1 typically generates a signal from one signal source or one
However, in the present invention, the control circuit 5 receives several signals (clocks) supplied to the chip from the outside and the outputs of one or more oscillators built into the chip. The generator 1 is controlled and driven. 2 and 3 are signal sources that convert the level of external signals, and 4 is an oscillator 1 provided on the chip.
It is one. The outputs φ ₁ and φ of these signal sources 2 and 3
₂ and the output OSC of the oscillator 4 are led to a control circuit 5 and converted into a signal φ ₃ that drives the substrate bias generator 1 . The control circuit 5 selects the signals φ ₁ , φ ₂ , and OSC according to one priority, or synthesizes them in time series to generate the signal φ ₃ .
An example of the latter is shown in FIG.

The control circuit 5 in the figure has signals φ ₁ , φ
_2. Three circuits 51, 52, 53 that detect changes to the L (low) level with OSC as each input, and a NAND gate that synthesizes these outputs φ ₁ ′, φ ₂ ′, and OSC′ in time series. 54, the gate 54
The output becomes the variable drive signal _φ3 for the substrate bias generator 1. The change point detection circuits 51 to 53 have the same configuration; for example, in the case of the detection circuit 51, an inverter INV that inverts the input _φ1 and its inverted output
₁ and input φ ₁ , and outputs a change point signal φ ₁ ' (return "H") of a constant width that rises with a constant delay after the fall of input φ ₁ . FIG. 3 shows the signal waveforms of each part, and the final output φ ₃ is φ ₁ ', φ ₂ ', OSC', and includes all the information of the inputs φ ₁ , φ ₂ , and OSC. Therefore, if the oscillator 4 always oscillates, the signal φ ₃ is the signal OSC itself if the signals φ ₁ and φ ₂ are not present, and the substrate bias generator 1
Drive with the longest period. Therefore, in this case, the charge from the substrate on which elements such as memory cells are mounted is not so much extracted. On the other hand, when the signals φ ₁ and φ ₂ are added, the wave number of the signal φ ₃ increases and the frequency becomes higher, so that the substrate bias generator 1 frequently repeats charge pumping and strengthens the negative substrate bias operation. If the signals φ ₁ and φ ₂ are level-converted drive clocks for the MOS memory (memory chips that reduce the number of pins by using address signal terminals in a time-division manner use two-phase clocks), then that chip can be selected. Sometimes the substrate charge is extracted at high speed. Then, when the chip becomes unselected and the signals φ ₁ and φ ₂ disappear, the frequency of the signal φ ₃ becomes
Returning to the OSC itself, it can thus always provide an optimal bias to the substrate.

For priority selection, select the control circuit 5, for example, a circuit that cuts off the signal that has been driving the substrate bias generation circuit and switches to the new signal when a new signal is generated, or selects a signal with a higher frequency. It may be a circuit etc. that

As described above, the present invention has the advantage of being able to generate an optimal bias voltage suited to the operating state of the device without increasing the number of substrate bias generators.

[Brief explanation of drawings]

Fig. 1 is a schematic block diagram showing one embodiment of the present invention, Fig. 2 is a block diagram showing an example of the control circuit of Fig. 1, and Fig. 3 is a signal waveform diagram of each part. In the figure, 1 is a substrate bias generator, 2 and 3 are signal sources, 4 is an oscillator, and 5 is a control circuit.

Claims (1)

[Scope of utility model registration request] A semiconductor device chip equipped with a substrate bias generator is provided with a plurality of signal sources, an oscillator, and a control circuit for driving the substrate bias generator,
A substrate bias generator characterized in that the control circuit drives the substrate bias generator using a signal obtained by chronologically combining the outputs of the signal source and the oscillator, or by a signal selected according to priority. Device.